Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.11	96.58	92.46	100.00	86.36	94.67	98.84	96.88

Total test records in report: 1269

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1774960183			Dec 24 12:30:22 PM PST 23	Dec 24 12:30:47 PM PST 23	163712889 ps
T1252	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3741017786			Dec 24 12:31:20 PM PST 23	Dec 24 12:31:50 PM PST 23	423693683 ps
T1253	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.32917150			Dec 24 12:27:21 PM PST 23	Dec 24 12:27:27 PM PST 23	351841540 ps
T1254	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.423973365			Dec 24 12:28:04 PM PST 23	Dec 24 12:28:19 PM PST 23	73815166 ps
T1255	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2757915023			Dec 24 12:27:35 PM PST 23	Dec 24 12:27:39 PM PST 23	401802549 ps
T1256	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3212534511			Dec 24 12:27:23 PM PST 23	Dec 24 12:27:30 PM PST 23	40322786 ps
T1257	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.846435840			Dec 24 12:28:00 PM PST 23	Dec 24 12:28:16 PM PST 23	975590183 ps
T1258	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3404790269			Dec 24 12:31:24 PM PST 23	Dec 24 12:31:52 PM PST 23	127043417 ps
T1259	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1930101695			Dec 24 12:28:45 PM PST 23	Dec 24 12:28:57 PM PST 23	361628115 ps
T1260	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2204597151			Dec 24 12:28:40 PM PST 23	Dec 24 12:28:47 PM PST 23	16169366 ps
T1261	/workspace/coverage/cover_reg_top/23.kmac_intr_test.1969465648			Dec 24 12:27:44 PM PST 23	Dec 24 12:27:56 PM PST 23	91744155 ps
T1262	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3325967126			Dec 24 12:27:15 PM PST 23	Dec 24 12:27:20 PM PST 23	113078005 ps
T1263	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3110379494			Dec 24 12:29:31 PM PST 23	Dec 24 12:29:43 PM PST 23	29530806 ps
T1264	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1639285494			Dec 24 12:28:54 PM PST 23	Dec 24 12:29:07 PM PST 23	533250073 ps
T1265	/workspace/coverage/cover_reg_top/24.kmac_intr_test.3150779168			Dec 24 12:28:22 PM PST 23	Dec 24 12:28:33 PM PST 23	35006278 ps
T1266	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1886427963			Dec 24 12:27:41 PM PST 23	Dec 24 12:27:45 PM PST 23	39127678 ps
T1267	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1106900234			Dec 24 12:27:19 PM PST 23	Dec 24 12:27:24 PM PST 23	19257238 ps
T1268	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2819099929			Dec 24 12:30:16 PM PST 23	Dec 24 12:30:41 PM PST 23	28209085 ps
T1269	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.209580617			Dec 24 12:27:35 PM PST 23	Dec 24 12:27:38 PM PST 23	88047880 ps

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.555061366
Short name	T1
Test name
Test status
Simulation time	22032349 ps
CPU time	1.06 seconds
Started	Dec 24 12:28:32 PM PST 23
Finished	Dec 24 12:28:40 PM PST 23
Peak memory	215736 kb
Host	smart-bf3f8a55-dc18-421a-9023-bb4c3b305e77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555061366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_ errors.555061366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.2015572984
Short name	T14
Test name
Test status
Simulation time	25755989126 ps
CPU time	437.69 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:59:52 PM PST 23
Peak memory	303372 kb
Host	smart-d9f5396f-5040-4b1c-95af-70c8b1fcc608
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2015572984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2015572984 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.653790067
Short name	T81
Test name
Test status
Simulation time	293571561 ps
CPU time	2.58 seconds
Started	Dec 24 12:28:47 PM PST 23
Finished	Dec 24 12:29:01 PM PST 23
Peak memory	223004 kb
Host	smart-bcecd0a3-c25c-43b8-a1c3-25aa0fbcf3c3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653790067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_ shadow_reg_errors_with_csr_rw.653790067 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.2818524815
Short name	T83
Test name
Test status
Simulation time	762066569 ps
CPU time	3.19 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:23 PM PST 23
Peak memory	215644 kb
Host	smart-a6dc9f6f-d944-4a2c-bfaf-d48ede389a47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818524815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2818524815 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.4202780755
Short name	T91
Test name
Test status
Simulation time	15027376 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:25 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	206972 kb
Host	smart-07da6f51-3352-41bd-8e5f-7d78dc29fe90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202780755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4202780755 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.491907268
Short name	T8
Test name
Test status
Simulation time	2240667262 ps
CPU time	31.34 seconds
Started	Dec 24 12:48:45 PM PST 23
Finished	Dec 24 12:49:18 PM PST 23
Peak memory	253580 kb
Host	smart-4832234c-ba77-4091-9640-7740af424c87
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491907268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.491907268 +enable_masking =0 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1759428380
Short name	T114
Test name
Test status
Simulation time	1266625047 ps
CPU time	5.33 seconds
Started	Dec 24 12:27:27 PM PST 23
Finished	Dec 24 12:27:35 PM PST 23
Peak memory	207188 kb
Host	smart-f2db9cc4-9060-471b-b6e8-f30d65d65adc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759428380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1759 428380 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/45.kmac_error.2029643853
Short name	T32
Test name
Test status
Simulation time	55416349298 ps
CPU time	310.52 seconds
Started	Dec 24 12:53:11 PM PST 23
Finished	Dec 24 12:58:24 PM PST 23
Peak memory	253472 kb
Host	smart-395ccad6-3f39-4494-bd9d-a54e6d8f2df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029643853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2029643853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.1969374829
Short name	T29
Test name
Test status
Simulation time	353731714466 ps
CPU time	2081.71 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 01:26:05 PM PST 23
Peak memory	314140 kb
Host	smart-6dda295a-d821-48f4-b5b7-ca2e4e0e7495
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1969374829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.1969374829 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1257506402
Short name	T103
Test name
Test status
Simulation time	50624043 ps
CPU time	2.54 seconds
Started	Dec 24 12:29:17 PM PST 23
Finished	Dec 24 12:29:29 PM PST 23
Peak memory	223612 kb
Host	smart-3643d5ee-99ee-4562-9fdf-30a10f6c17f9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257506402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.1257506402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.3189304673
Short name	T181
Test name
Test status
Simulation time	226593681237 ps
CPU time	4313.98 seconds
Started	Dec 24 12:49:33 PM PST 23
Finished	Dec 24 02:01:29 PM PST 23
Peak memory	563608 kb
Host	smart-cb490f5a-fc47-4803-a3ce-057defee9723
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3189304673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3189304673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_key_error.1754834076
Short name	T6
Test name
Test status
Simulation time	1854574702 ps
CPU time	5.28 seconds
Started	Dec 24 12:50:13 PM PST 23
Finished	Dec 24 12:50:24 PM PST 23
Peak memory	207280 kb
Host	smart-a7930bf5-9851-47e2-929c-7036d4a87580
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754834076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1754834076 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3177598203
Short name	T112
Test name
Test status
Simulation time	348837789 ps
CPU time	4.87 seconds
Started	Dec 24 12:28:05 PM PST 23
Finished	Dec 24 12:28:22 PM PST 23
Peak memory	215440 kb
Host	smart-84ff1bec-85da-4f04-9806-f45df2a9c68b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177598203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3177 598203 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2075122084
Short name	T133
Test name
Test status
Simulation time	32524818 ps
CPU time	1.12 seconds
Started	Dec 24 12:28:20 PM PST 23
Finished	Dec 24 12:28:32 PM PST 23
Peak memory	215396 kb
Host	smart-5af32a9e-7d3b-44b5-b925-b3f42fcf1c9e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075122084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.2075122084 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.288796324
Short name	T171
Test name
Test status
Simulation time	19971552 ps
CPU time	0.9 seconds
Started	Dec 24 12:27:43 PM PST 23
Finished	Dec 24 12:27:50 PM PST 23
Peak memory	207036 kb
Host	smart-50a95caf-e76c-4747-bf14-2151e218e9c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288796324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.288796324 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.407495095
Short name	T22
Test name
Test status
Simulation time	20167131567 ps
CPU time	1299.22 seconds
Started	Dec 24 12:48:10 PM PST 23
Finished	Dec 24 01:09:52 PM PST 23
Peak memory	404064 kb
Host	smart-fc7a4b6e-913a-476f-bf40-2397eda196d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=407495095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.407495095 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3796500858
Short name	T104
Test name
Test status
Simulation time	422277464 ps
CPU time	1.27 seconds
Started	Dec 24 12:29:55 PM PST 23
Finished	Dec 24 12:30:21 PM PST 23
Peak memory	215704 kb
Host	smart-eb614edd-4ef3-4e79-8f43-c0774f1c451b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796500858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3796500858 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.119204896
Short name	T19
Test name
Test status
Simulation time	37846969733 ps
CPU time	752.7 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 01:02:41 PM PST 23
Peak memory	293256 kb
Host	smart-5036c35d-ef49-4591-8d8b-0c617629d7a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=119204896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.119204896 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3731267
Short name	T117
Test name
Test status
Simulation time	525050665 ps
CPU time	3.08 seconds
Started	Dec 24 12:28:08 PM PST 23
Finished	Dec 24 12:28:25 PM PST 23
Peak memory	215448 kb
Host	smart-7bc4ce28-2e78-44a8-8dae-6fb98aa1e3c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3731267 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.3083627073
Short name	T61
Test name
Test status
Simulation time	26938708 ps
CPU time	0.74 seconds
Started	Dec 24 12:27:31 PM PST 23
Finished	Dec 24 12:27:33 PM PST 23
Peak memory	206988 kb
Host	smart-359fcb37-9603-4049-9116-3b1064a9e7c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083627073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3083627073 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2919076966
Short name	T154
Test name
Test status
Simulation time	822840475 ps
CPU time	4.92 seconds
Started	Dec 24 12:30:02 PM PST 23
Finished	Dec 24 12:30:33 PM PST 23
Peak memory	215444 kb
Host	smart-0c8a3af1-524c-4b96-b562-0f8a97cb041d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919076966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.29190 76966 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/12.kmac_key_error.915379495
Short name	T24
Test name
Test status
Simulation time	1135415842 ps
CPU time	5.33 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	207232 kb
Host	smart-8d25b37d-4427-447c-be7b-40ddca5fc040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915379495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.915379495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_error.3666699553
Short name	T355
Test name
Test status
Simulation time	17203838214 ps
CPU time	358.14 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 12:55:21 PM PST 23
Peak memory	256608 kb
Host	smart-a01edafb-e9ef-4cb7-b3ce-14caba171d6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666699553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3666699553 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.1214522199
Short name	T59
Test name
Test status
Simulation time	80397906 ps
CPU time	1.26 seconds
Started	Dec 24 12:49:22 PM PST 23
Finished	Dec 24 12:49:25 PM PST 23
Peak memory	215616 kb
Host	smart-76822d67-7d41-40e1-a19e-f55c28565a50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214522199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1214522199 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.2155101123
Short name	T279
Test name
Test status
Simulation time	41611603 ps
CPU time	0.76 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 12:49:18 PM PST 23
Peak memory	205188 kb
Host	smart-dc60298d-390a-4a00-9ff4-bc634e58bc4c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155101123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2155101123 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2405865524
Short name	T139
Test name
Test status
Simulation time	33639134 ps
CPU time	0.89 seconds
Started	Dec 24 12:27:55 PM PST 23
Finished	Dec 24 12:28:07 PM PST 23
Peak memory	215116 kb
Host	smart-e2ce2e33-01de-4e12-9e82-8544899148dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405865524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2405865524 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.2458139982
Short name	T956
Test name
Test status
Simulation time	9349286479 ps
CPU time	98.36 seconds
Started	Dec 24 12:48:00 PM PST 23
Finished	Dec 24 12:49:41 PM PST 23
Peak memory	228228 kb
Host	smart-137b82b0-a06f-41b7-8fe2-f1e930700ef7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458139982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2458139982 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.2958484958
Short name	T147
Test name
Test status
Simulation time	4983090848 ps
CPU time	116.84 seconds
Started	Dec 24 12:48:01 PM PST 23
Finished	Dec 24 12:50:00 PM PST 23
Peak memory	232684 kb
Host	smart-fb1ad046-edf1-48a4-8de1-fc0b6313e72c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958484958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2958484958 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.4286689779
Short name	T144
Test name
Test status
Simulation time	633221000932 ps
CPU time	3981.74 seconds
Started	Dec 24 12:48:53 PM PST 23
Finished	Dec 24 01:55:17 PM PST 23
Peak memory	562976 kb
Host	smart-45878cda-f4b9-4336-aae3-5ac03888b52a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4286689779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.4286689779 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3987411280
Short name	T1246
Test name
Test status
Simulation time	821613703 ps
CPU time	5.44 seconds
Started	Dec 24 12:27:12 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	207080 kb
Host	smart-6e797deb-5995-4040-a27c-85e3285382d5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987411280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3987411 280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.289373558
Short name	T1191
Test name
Test status
Simulation time	1211471828 ps
CPU time	16.09 seconds
Started	Dec 24 12:29:39 PM PST 23
Finished	Dec 24 12:30:20 PM PST 23
Peak memory	207176 kb
Host	smart-4100cf73-fcea-428e-9188-2cfd95893843
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289373558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.28937355 8 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.308112933
Short name	T1241
Test name
Test status
Simulation time	30065542 ps
CPU time	0.98 seconds
Started	Dec 24 12:28:15 PM PST 23
Finished	Dec 24 12:28:29 PM PST 23
Peak memory	206968 kb
Host	smart-ad80a3b9-51b7-42f0-8922-93097300c1fc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308112933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.30811293 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1679239571
Short name	T1229
Test name
Test status
Simulation time	78725393 ps
CPU time	1.34 seconds
Started	Dec 24 12:27:42 PM PST 23
Finished	Dec 24 12:27:50 PM PST 23
Peak memory	215368 kb
Host	smart-c3c86d72-0671-4f75-9fc4-853a4ca7c797
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679239571 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.1679239571 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2942089429
Short name	T1166
Test name
Test status
Simulation time	17407416 ps
CPU time	1.09 seconds
Started	Dec 24 12:27:20 PM PST 23
Finished	Dec 24 12:27:24 PM PST 23
Peak memory	207220 kb
Host	smart-c29d726a-8efa-4fb3-ac4f-83d3fd8e3e58
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942089429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2942089429 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2385092846
Short name	T94
Test name
Test status
Simulation time	21942495 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:54 PM PST 23
Finished	Dec 24 12:29:10 PM PST 23
Peak memory	207000 kb
Host	smart-5441f4b2-9ed9-406f-9628-2db8ba43973d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385092846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2385092846 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1681301165
Short name	T126
Test name
Test status
Simulation time	67367743 ps
CPU time	1.36 seconds
Started	Dec 24 12:28:09 PM PST 23
Finished	Dec 24 12:28:25 PM PST 23
Peak memory	215388 kb
Host	smart-6b8963d1-3e50-44d0-ba24-84b01dd07842
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681301165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.1681301165 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.600813407
Short name	T1245
Test name
Test status
Simulation time	50517482 ps
CPU time	0.71 seconds
Started	Dec 24 12:27:50 PM PST 23
Finished	Dec 24 12:28:00 PM PST 23
Peak memory	207028 kb
Host	smart-3d062f0e-0c62-4e50-b22a-e67bf87db8c0
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600813407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.600813407 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1511224245
Short name	T1214
Test name
Test status
Simulation time	43410512 ps
CPU time	1.42 seconds
Started	Dec 24 12:28:50 PM PST 23
Finished	Dec 24 12:29:03 PM PST 23
Peak memory	214964 kb
Host	smart-72057f3a-3de9-442a-b430-e43ca7f2b139
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511224245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1511224245 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.358570980
Short name	T1202
Test name
Test status
Simulation time	137481582 ps
CPU time	2.99 seconds
Started	Dec 24 12:30:14 PM PST 23
Finished	Dec 24 12:30:40 PM PST 23
Peak memory	215756 kb
Host	smart-d6e8d8e4-6191-481d-a5cc-41ead26e7e82
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358570980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.358570980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3361096954
Short name	T1206
Test name
Test status
Simulation time	24700888 ps
CPU time	1.61 seconds
Started	Dec 24 12:28:13 PM PST 23
Finished	Dec 24 12:28:29 PM PST 23
Peak memory	215588 kb
Host	smart-4c115d20-9cd3-47fb-8e29-59e4337062b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361096954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3361096954 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3316688156
Short name	T121
Test name
Test status
Simulation time	4049991680 ps
CPU time	10.54 seconds
Started	Dec 24 12:27:14 PM PST 23
Finished	Dec 24 12:27:27 PM PST 23
Peak memory	207420 kb
Host	smart-ad421158-1292-43e9-b381-4b7289844aa8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316688156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3316688 156 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2543624260
Short name	T1209
Test name
Test status
Simulation time	684151347 ps
CPU time	15.03 seconds
Started	Dec 24 12:27:56 PM PST 23
Finished	Dec 24 12:28:24 PM PST 23
Peak memory	207220 kb
Host	smart-b11db05c-50fe-4751-aee9-a66469e45a53
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543624260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2543624 260 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3308295734
Short name	T1200
Test name
Test status
Simulation time	68836837 ps
CPU time	1.04 seconds
Started	Dec 24 12:29:15 PM PST 23
Finished	Dec 24 12:29:21 PM PST 23
Peak memory	206136 kb
Host	smart-56e08e7d-cbb7-463d-841a-d95f223ef54d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308295734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3308295 734 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1486208489
Short name	T164
Test name
Test status
Simulation time	34123339 ps
CPU time	2.03 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:19 PM PST 23
Peak memory	223304 kb
Host	smart-1cc49c84-aed9-4778-af7a-1845caf21b6f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486208489 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1486208489 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.4262623624
Short name	T138
Test name
Test status
Simulation time	108038937 ps
CPU time	1.07 seconds
Started	Dec 24 12:27:42 PM PST 23
Finished	Dec 24 12:27:46 PM PST 23
Peak memory	207196 kb
Host	smart-f08ff110-6c5e-49bc-94a1-0b5be407e348
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262623624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4262623624 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.3075419390
Short name	T169
Test name
Test status
Simulation time	23507253 ps
CPU time	0.76 seconds
Started	Dec 24 12:27:57 PM PST 23
Finished	Dec 24 12:28:10 PM PST 23
Peak memory	207032 kb
Host	smart-024f7792-3d4e-4e46-81a6-0ae7c408cb65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075419390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3075419390 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.17124506
Short name	T132
Test name
Test status
Simulation time	55577471 ps
CPU time	1.12 seconds
Started	Dec 24 12:28:24 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	215208 kb
Host	smart-cf8cd6aa-b3d4-477e-9c30-baedbe3f678c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_ access.17124506 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.978283331
Short name	T1176
Test name
Test status
Simulation time	23608281 ps
CPU time	0.7 seconds
Started	Dec 24 12:30:01 PM PST 23
Finished	Dec 24 12:30:28 PM PST 23
Peak memory	206908 kb
Host	smart-1c630a0f-b522-462b-addd-7cca4461f2b0
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978283331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.978283331 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.98877447
Short name	T1194
Test name
Test status
Simulation time	51278691 ps
CPU time	1.48 seconds
Started	Dec 24 12:27:51 PM PST 23
Finished	Dec 24 12:28:01 PM PST 23
Peak memory	215308 kb
Host	smart-62c6ba78-0301-411f-a0fc-b9ffcc159cea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98877447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_o utstanding.98877447 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.489558644
Short name	T100
Test name
Test status
Simulation time	117285185 ps
CPU time	1.13 seconds
Started	Dec 24 12:29:54 PM PST 23
Finished	Dec 24 12:30:21 PM PST 23
Peak memory	215736 kb
Host	smart-a25b937a-2c14-4212-9f35-79b055098855
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489558644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e rrors.489558644 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.843479183
Short name	T106
Test name
Test status
Simulation time	143424074 ps
CPU time	3 seconds
Started	Dec 24 12:29:15 PM PST 23
Finished	Dec 24 12:29:23 PM PST 23
Peak memory	223132 kb
Host	smart-421e257e-3281-4da6-b2c6-71c3e2a779e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843479183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.843479183 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.26323897
Short name	T55
Test name
Test status
Simulation time	1164877500 ps
CPU time	3.3 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:22 PM PST 23
Peak memory	215584 kb
Host	smart-36af3c52-5d4e-4d15-a2e3-38ece668bcd0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.26323897 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1400249165
Short name	T159
Test name
Test status
Simulation time	248629993 ps
CPU time	4.88 seconds
Started	Dec 24 12:28:04 PM PST 23
Finished	Dec 24 12:28:21 PM PST 23
Peak memory	207372 kb
Host	smart-ecfa937c-1cdc-4cb2-8aa9-ccdda016fa3a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400249165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.14002 49165 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1650110955
Short name	T88
Test name
Test status
Simulation time	210631888 ps
CPU time	1.51 seconds
Started	Dec 24 12:27:19 PM PST 23
Finished	Dec 24 12:27:24 PM PST 23
Peak memory	215440 kb
Host	smart-d695a963-310d-4507-940c-3dd85ae9a0bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650110955 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1650110955 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.496005858
Short name	T1230
Test name
Test status
Simulation time	31936983 ps
CPU time	1.18 seconds
Started	Dec 24 12:28:24 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	207136 kb
Host	smart-3fa5bcb8-065d-4ed2-9d41-29ab1cd3263f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496005858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.496005858 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2893618114
Short name	T1169
Test name
Test status
Simulation time	172521375 ps
CPU time	0.77 seconds
Started	Dec 24 12:28:07 PM PST 23
Finished	Dec 24 12:28:21 PM PST 23
Peak memory	207108 kb
Host	smart-c22545fc-b740-4667-a2a1-f5f557414d9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893618114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2893618114 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3233483123
Short name	T1177
Test name
Test status
Simulation time	185591733 ps
CPU time	2.31 seconds
Started	Dec 24 12:27:18 PM PST 23
Finished	Dec 24 12:27:24 PM PST 23
Peak memory	207228 kb
Host	smart-48d13c8e-0ca6-4487-9251-2c03578ad59b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233483123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.3233483123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2085131603
Short name	T175
Test name
Test status
Simulation time	37302411 ps
CPU time	1.15 seconds
Started	Dec 24 12:28:11 PM PST 23
Finished	Dec 24 12:28:27 PM PST 23
Peak memory	215728 kb
Host	smart-2699df2f-2fab-4a12-beae-afb24f9afe32
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085131603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.2085131603 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3662746996
Short name	T97
Test name
Test status
Simulation time	91840430 ps
CPU time	2.45 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:27 PM PST 23
Peak memory	215808 kb
Host	smart-4a0f7593-e3ce-42bd-9e7e-9ce7b569dfea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662746996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.3662746996 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2947888169
Short name	T116
Test name
Test status
Simulation time	299762930 ps
CPU time	3.53 seconds
Started	Dec 24 12:27:23 PM PST 23
Finished	Dec 24 12:27:31 PM PST 23
Peak memory	215324 kb
Host	smart-1135455e-d826-4a07-852c-539235b69d7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947888169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2947888169 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.969625390
Short name	T166
Test name
Test status
Simulation time	72648263 ps
CPU time	1.92 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	223504 kb
Host	smart-68d476aa-5a90-47a9-af81-ba81599e5b97
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969625390 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.969625390 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.602582248
Short name	T178
Test name
Test status
Simulation time	200320864 ps
CPU time	1.1 seconds
Started	Dec 24 12:30:17 PM PST 23
Finished	Dec 24 12:30:40 PM PST 23
Peak memory	207140 kb
Host	smart-05b50996-77dd-42a6-8b13-af255e4b5cac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602582248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.602582248 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.3586362160
Short name	T1197
Test name
Test status
Simulation time	13182275 ps
CPU time	0.75 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	207340 kb
Host	smart-c606579c-a9e2-4c49-864d-d08240453d8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586362160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3586362160 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3933110885
Short name	T136
Test name
Test status
Simulation time	43264415 ps
CPU time	2.32 seconds
Started	Dec 24 12:28:04 PM PST 23
Finished	Dec 24 12:28:19 PM PST 23
Peak memory	215420 kb
Host	smart-a497bff9-d7ea-40fe-9d01-e09d7f9c59ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933110885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.3933110885 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2107231035
Short name	T102
Test name
Test status
Simulation time	27822734 ps
CPU time	1.01 seconds
Started	Dec 24 12:28:28 PM PST 23
Finished	Dec 24 12:28:37 PM PST 23
Peak memory	215452 kb
Host	smart-b8d0d098-8dd0-480e-a785-cb53070d4aa1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107231035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.2107231035 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1002197433
Short name	T1205
Test name
Test status
Simulation time	256417616 ps
CPU time	1.72 seconds
Started	Dec 24 12:27:12 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	223176 kb
Host	smart-db078ccf-032d-4a6d-acdc-498e814d08d1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002197433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.1002197433 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.423973365
Short name	T1254
Test name
Test status
Simulation time	73815166 ps
CPU time	2.33 seconds
Started	Dec 24 12:28:04 PM PST 23
Finished	Dec 24 12:28:19 PM PST 23
Peak memory	215564 kb
Host	smart-3f212ee4-beed-43d3-91e3-b722bbdd0d63
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423973365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.423973365 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1774960183
Short name	T1251
Test name
Test status
Simulation time	163712889 ps
CPU time	2.45 seconds
Started	Dec 24 12:30:22 PM PST 23
Finished	Dec 24 12:30:47 PM PST 23
Peak memory	217944 kb
Host	smart-9a4d7307-24e5-4fa8-bc61-1193dbc95025
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774960183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1774 960183 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.408939060
Short name	T1180
Test name
Test status
Simulation time	24689425 ps
CPU time	1.45 seconds
Started	Dec 24 12:28:25 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	215444 kb
Host	smart-631bc36c-ac12-4b87-a002-08e68c92b5c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408939060 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.408939060 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2277789069
Short name	T1165
Test name
Test status
Simulation time	38581717 ps
CPU time	1.08 seconds
Started	Dec 24 12:29:17 PM PST 23
Finished	Dec 24 12:29:27 PM PST 23
Peak memory	215504 kb
Host	smart-1a248c0d-5bdf-40e0-b7c8-0f17638d2617
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277789069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2277789069 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.2758393557
Short name	T1223
Test name
Test status
Simulation time	27000858 ps
CPU time	0.72 seconds
Started	Dec 24 12:28:55 PM PST 23
Finished	Dec 24 12:29:06 PM PST 23
Peak memory	206892 kb
Host	smart-3054a39f-58ee-4801-bd39-104a7c96cff8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758393557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2758393557 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3212534511
Short name	T1256
Test name
Test status
Simulation time	40322786 ps
CPU time	2.23 seconds
Started	Dec 24 12:27:23 PM PST 23
Finished	Dec 24 12:27:30 PM PST 23
Peak memory	215484 kb
Host	smart-bd520c34-8d2e-465f-9f38-521b1399e693
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212534511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.3212534511 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2762879169
Short name	T1162
Test name
Test status
Simulation time	64327914 ps
CPU time	0.83 seconds
Started	Dec 24 12:28:56 PM PST 23
Finished	Dec 24 12:29:07 PM PST 23
Peak memory	207056 kb
Host	smart-39033953-f6fa-41c5-a6e8-b2e0eccce0b2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762879169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.2762879169 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.544524329
Short name	T108
Test name
Test status
Simulation time	49621204 ps
CPU time	1.65 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	223796 kb
Host	smart-22f5c41f-f1dd-4232-8e1d-d73987914e37
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544524329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac _shadow_reg_errors_with_csr_rw.544524329 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2237030417
Short name	T89
Test name
Test status
Simulation time	66809725 ps
CPU time	2.29 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:28:56 PM PST 23
Peak memory	215568 kb
Host	smart-89cb45e0-c0dc-4dec-a023-e6043e62cfc6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237030417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2237030417 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1117988330
Short name	T158
Test name
Test status
Simulation time	153639415 ps
CPU time	2.89 seconds
Started	Dec 24 12:29:35 PM PST 23
Finished	Dec 24 12:29:52 PM PST 23
Peak memory	215228 kb
Host	smart-d07b0a46-2372-46f2-a042-60df39fa6dc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117988330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1117 988330 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.209580617
Short name	T1269
Test name
Test status
Simulation time	88047880 ps
CPU time	2 seconds
Started	Dec 24 12:27:35 PM PST 23
Finished	Dec 24 12:27:38 PM PST 23
Peak memory	223788 kb
Host	smart-c35e4e0d-fda2-46f2-a8fd-649c314802ab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209580617 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.209580617 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.1359827154
Short name	T1193
Test name
Test status
Simulation time	115096645 ps
CPU time	1.17 seconds
Started	Dec 24 12:28:13 PM PST 23
Finished	Dec 24 12:28:28 PM PST 23
Peak memory	207280 kb
Host	smart-c94334c8-5dd6-4c11-8dda-5cae430398db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359827154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1359827154 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1924123861
Short name	T1238
Test name
Test status
Simulation time	54132228 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:10 PM PST 23
Finished	Dec 24 12:28:26 PM PST 23
Peak memory	207060 kb
Host	smart-69c3a7d7-ae34-45b0-a92a-7e44bb5330e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924123861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1924123861 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.404705543
Short name	T1192
Test name
Test status
Simulation time	53854529 ps
CPU time	1.7 seconds
Started	Dec 24 12:27:19 PM PST 23
Finished	Dec 24 12:27:24 PM PST 23
Peak memory	215348 kb
Host	smart-72b37273-bcc3-446b-ac00-d07f8eec4634
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404705543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr _outstanding.404705543 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.520786518
Short name	T1150
Test name
Test status
Simulation time	18070972 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	207040 kb
Host	smart-9ca65ae4-748f-4772-9e4b-ff349c4c26ab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520786518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_ errors.520786518 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.846435840
Short name	T1257
Test name
Test status
Simulation time	975590183 ps
CPU time	2.95 seconds
Started	Dec 24 12:28:00 PM PST 23
Finished	Dec 24 12:28:16 PM PST 23
Peak memory	215768 kb
Host	smart-043328d5-3876-4468-9060-a0b09e2ab99e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846435840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac _shadow_reg_errors_with_csr_rw.846435840 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2720802852
Short name	T1218
Test name
Test status
Simulation time	202834594 ps
CPU time	5.12 seconds
Started	Dec 24 12:29:35 PM PST 23
Finished	Dec 24 12:29:54 PM PST 23
Peak memory	207192 kb
Host	smart-e99d0aa1-f7d2-4c01-915b-782519dda8ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720802852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2720 802852 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.250892944
Short name	T1190
Test name
Test status
Simulation time	23622827 ps
CPU time	1.38 seconds
Started	Dec 24 12:27:22 PM PST 23
Finished	Dec 24 12:27:28 PM PST 23
Peak memory	215328 kb
Host	smart-a48eeb95-7322-4669-8a9a-d368fbe4bb5a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250892944 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.250892944 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.2262342839
Short name	T135
Test name
Test status
Simulation time	23731871 ps
CPU time	0.79 seconds
Started	Dec 24 12:27:18 PM PST 23
Finished	Dec 24 12:27:23 PM PST 23
Peak memory	207172 kb
Host	smart-82c8b969-03f3-460e-ab7b-0157bf4c5e94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262342839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2262342839 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2710151188
Short name	T1201
Test name
Test status
Simulation time	1092704519 ps
CPU time	2.85 seconds
Started	Dec 24 12:28:37 PM PST 23
Finished	Dec 24 12:28:46 PM PST 23
Peak memory	215380 kb
Host	smart-c7b1da4c-7753-4500-983c-b8e4927a141d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710151188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.2710151188 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.306760228
Short name	T1221
Test name
Test status
Simulation time	41017799 ps
CPU time	0.95 seconds
Started	Dec 24 12:30:24 PM PST 23
Finished	Dec 24 12:30:49 PM PST 23
Peak memory	215580 kb
Host	smart-184dba64-b6d4-48b3-bb28-ea5354cd5f8c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306760228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_ errors.306760228 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1261446449
Short name	T1183
Test name
Test status
Simulation time	312670341 ps
CPU time	1.9 seconds
Started	Dec 24 12:28:10 PM PST 23
Finished	Dec 24 12:28:27 PM PST 23
Peak memory	215780 kb
Host	smart-1506c9e0-c41d-4cbd-a2ae-010551938c6f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261446449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.1261446449 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.2688928411
Short name	T115
Test name
Test status
Simulation time	150145176 ps
CPU time	1.75 seconds
Started	Dec 24 12:28:17 PM PST 23
Finished	Dec 24 12:28:30 PM PST 23
Peak memory	215560 kb
Host	smart-172e8dc3-7566-4c5c-bb6d-0e53f96ec786
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688928411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2688928411 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1123062949
Short name	T160
Test name
Test status
Simulation time	320576088 ps
CPU time	2.53 seconds
Started	Dec 24 12:27:13 PM PST 23
Finished	Dec 24 12:27:18 PM PST 23
Peak memory	207096 kb
Host	smart-458d1d15-6051-4997-8f4a-83837d27e070
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123062949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1123 062949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2922693314
Short name	T1243
Test name
Test status
Simulation time	31449990 ps
CPU time	1.74 seconds
Started	Dec 24 12:28:26 PM PST 23
Finished	Dec 24 12:28:36 PM PST 23
Peak memory	223588 kb
Host	smart-214fa14b-763a-46f1-be99-d347d143b4eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922693314 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2922693314 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.691087116
Short name	T1158
Test name
Test status
Simulation time	44503851 ps
CPU time	0.99 seconds
Started	Dec 24 12:27:22 PM PST 23
Finished	Dec 24 12:27:28 PM PST 23
Peak memory	206872 kb
Host	smart-e4c84e38-21ae-4b94-8c55-a03dfff2fedb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691087116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.691087116 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.471839505
Short name	T1186
Test name
Test status
Simulation time	33272510 ps
CPU time	0.74 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	206736 kb
Host	smart-a5f71cb6-da98-4a3b-8e47-ef6da5efb3ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471839505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.471839505 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.32917150
Short name	T1253
Test name
Test status
Simulation time	351841540 ps
CPU time	2.56 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:27 PM PST 23
Peak memory	215432 kb
Host	smart-776e9b24-bd99-48b1-a21f-6729c823f740
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32917150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_ outstanding.32917150 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3406636867
Short name	T98
Test name
Test status
Simulation time	171962264 ps
CPU time	1.08 seconds
Started	Dec 24 12:29:23 PM PST 23
Finished	Dec 24 12:29:33 PM PST 23
Peak memory	215692 kb
Host	smart-42192d7c-df67-40ab-8b36-b6fac4adcab7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406636867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.3406636867 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4253656272
Short name	T1151
Test name
Test status
Simulation time	99928497 ps
CPU time	2.71 seconds
Started	Dec 24 12:27:32 PM PST 23
Finished	Dec 24 12:27:36 PM PST 23
Peak memory	223788 kb
Host	smart-0a91804d-8f0c-462b-b993-0074f879c610
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253656272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.4253656272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3708267482
Short name	T86
Test name
Test status
Simulation time	20819861 ps
CPU time	1.38 seconds
Started	Dec 24 12:27:27 PM PST 23
Finished	Dec 24 12:27:31 PM PST 23
Peak memory	215396 kb
Host	smart-af0c75a5-eafa-4af5-a130-fe257ee957c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708267482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3708267482 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2757915023
Short name	T1255
Test name
Test status
Simulation time	401802549 ps
CPU time	2.83 seconds
Started	Dec 24 12:27:35 PM PST 23
Finished	Dec 24 12:27:39 PM PST 23
Peak memory	215448 kb
Host	smart-d04db738-2db6-4ff0-b137-0d87b594bbc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757915023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2757 915023 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2819099929
Short name	T1268
Test name
Test status
Simulation time	28209085 ps
CPU time	2.13 seconds
Started	Dec 24 12:30:16 PM PST 23
Finished	Dec 24 12:30:41 PM PST 23
Peak memory	223516 kb
Host	smart-d503d480-8e74-401b-bbb5-60593143c70e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819099929 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2819099929 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.3883114201
Short name	T1168
Test name
Test status
Simulation time	20072511 ps
CPU time	0.94 seconds
Started	Dec 24 12:27:54 PM PST 23
Finished	Dec 24 12:28:02 PM PST 23
Peak memory	206988 kb
Host	smart-1736235b-b636-4045-9dc4-7af0de8465f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883114201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3883114201 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3813589225
Short name	T1174
Test name
Test status
Simulation time	17794505 ps
CPU time	0.77 seconds
Started	Dec 24 12:27:54 PM PST 23
Finished	Dec 24 12:28:02 PM PST 23
Peak memory	206884 kb
Host	smart-9ed8d758-f9a1-4272-98d0-1546bda1623b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813589225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3813589225 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2876526638
Short name	T122
Test name
Test status
Simulation time	38372343 ps
CPU time	2.13 seconds
Started	Dec 24 12:28:42 PM PST 23
Finished	Dec 24 12:28:50 PM PST 23
Peak memory	215436 kb
Host	smart-e6e42b63-2061-45b3-9948-9a7d1f07af36
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876526638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.2876526638 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.204985994
Short name	T1249
Test name
Test status
Simulation time	124665754 ps
CPU time	1.18 seconds
Started	Dec 24 12:28:49 PM PST 23
Finished	Dec 24 12:29:01 PM PST 23
Peak memory	216108 kb
Host	smart-1186b10e-b472-4d31-b910-55f36a0d7cf7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204985994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_ errors.204985994 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1711346227
Short name	T105
Test name
Test status
Simulation time	282650457 ps
CPU time	1.92 seconds
Started	Dec 24 12:27:27 PM PST 23
Finished	Dec 24 12:27:31 PM PST 23
Peak memory	215744 kb
Host	smart-b8ab2224-efcd-4c4b-89e7-c1334408da83
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711346227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1711346227 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.699858547
Short name	T87
Test name
Test status
Simulation time	26520679 ps
CPU time	1.66 seconds
Started	Dec 24 12:28:06 PM PST 23
Finished	Dec 24 12:28:20 PM PST 23
Peak memory	215544 kb
Host	smart-1f2f31c1-0378-4937-a838-edac7ea911f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699858547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.699858547 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1627412172
Short name	T1157
Test name
Test status
Simulation time	1016980332 ps
CPU time	5.03 seconds
Started	Dec 24 12:28:35 PM PST 23
Finished	Dec 24 12:28:47 PM PST 23
Peak memory	207288 kb
Host	smart-bd783866-730f-477e-a375-58d5f88c83f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627412172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1627 412172 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2762244258
Short name	T82
Test name
Test status
Simulation time	29478043 ps
CPU time	1.51 seconds
Started	Dec 24 12:29:28 PM PST 23
Finished	Dec 24 12:29:40 PM PST 23
Peak memory	215488 kb
Host	smart-6fcf4999-7a9f-4169-9880-878a45419235
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762244258 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2762244258 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1106900234
Short name	T1267
Test name
Test status
Simulation time	19257238 ps
CPU time	1.09 seconds
Started	Dec 24 12:27:19 PM PST 23
Finished	Dec 24 12:27:24 PM PST 23
Peak memory	215716 kb
Host	smart-55212f0e-1f17-4d87-9cfb-af2372a368bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106900234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1106900234 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.4088627118
Short name	T1228
Test name
Test status
Simulation time	42041056 ps
CPU time	0.74 seconds
Started	Dec 24 12:27:22 PM PST 23
Finished	Dec 24 12:27:27 PM PST 23
Peak memory	206852 kb
Host	smart-9ac7c46f-20dc-49b2-a072-bdfd8f868207
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088627118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.4088627118 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.844926536
Short name	T1172
Test name
Test status
Simulation time	593054363 ps
CPU time	1.79 seconds
Started	Dec 24 12:30:19 PM PST 23
Finished	Dec 24 12:30:42 PM PST 23
Peak memory	215332 kb
Host	smart-0ef0f900-bd37-474e-a80d-9e786eaf4461
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844926536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr _outstanding.844926536 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2477834151
Short name	T1167
Test name
Test status
Simulation time	86086175 ps
CPU time	1.11 seconds
Started	Dec 24 12:28:26 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	215840 kb
Host	smart-8d6140dc-60a7-41a2-8fca-336036c2d535
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477834151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.2477834151 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1642391515
Short name	T2
Test name
Test status
Simulation time	34017248 ps
CPU time	1.45 seconds
Started	Dec 24 12:30:15 PM PST 23
Finished	Dec 24 12:30:39 PM PST 23
Peak memory	215332 kb
Host	smart-cffd2445-f6d4-4c72-b3e7-017b08108491
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642391515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.1642391515 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3548183366
Short name	T124
Test name
Test status
Simulation time	79952773 ps
CPU time	1.59 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:26 PM PST 23
Peak memory	223668 kb
Host	smart-bd3ca9de-f3c4-4edb-9513-6fc6295f4627
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548183366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3548183366 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4043334493
Short name	T156
Test name
Test status
Simulation time	558449892 ps
CPU time	6.05 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:30 PM PST 23
Peak memory	215304 kb
Host	smart-b0baa4f7-09ce-4481-97ae-f2363baccf98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043334493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4043 334493 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3959622195
Short name	T1240
Test name
Test status
Simulation time	31463958 ps
CPU time	1.55 seconds
Started	Dec 24 12:28:32 PM PST 23
Finished	Dec 24 12:28:41 PM PST 23
Peak memory	215396 kb
Host	smart-0e96db7f-740c-412e-97f2-b609739d633a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959622195 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3959622195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.2270298481
Short name	T3
Test name
Test status
Simulation time	37110815 ps
CPU time	1 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:55 PM PST 23
Peak memory	207024 kb
Host	smart-a22871cf-b9ba-4e1d-ac4c-1f04638a1d6a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270298481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2270298481 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.1926290552
Short name	T165
Test name
Test status
Simulation time	49806455 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:39 PM PST 23
Finished	Dec 24 12:29:59 PM PST 23
Peak memory	207060 kb
Host	smart-5e460ead-1ec7-41e2-b26e-00eca3b17501
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926290552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1926290552 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.261101500
Short name	T1181
Test name
Test status
Simulation time	186092247 ps
CPU time	2.29 seconds
Started	Dec 24 12:28:31 PM PST 23
Finished	Dec 24 12:28:41 PM PST 23
Peak memory	215508 kb
Host	smart-f24a6097-63a5-4cb9-9920-9045a86205c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261101500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr _outstanding.261101500 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4137069604
Short name	T167
Test name
Test status
Simulation time	306630311 ps
CPU time	1.92 seconds
Started	Dec 24 12:27:59 PM PST 23
Finished	Dec 24 12:28:14 PM PST 23
Peak memory	215772 kb
Host	smart-4af5e9ec-1336-464c-9614-827ed8d91903
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137069604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.4137069604 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3611488917
Short name	T1203
Test name
Test status
Simulation time	99304995 ps
CPU time	1.68 seconds
Started	Dec 24 12:27:54 PM PST 23
Finished	Dec 24 12:28:07 PM PST 23
Peak memory	215636 kb
Host	smart-3916e2c5-1539-437a-a4af-ef937c1f0561
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611488917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3611488917 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.238817820
Short name	T155
Test name
Test status
Simulation time	53608013 ps
CPU time	2.54 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:55 PM PST 23
Peak memory	217936 kb
Host	smart-3a79519c-c742-48c4-852e-4d11a97787c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238817820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.23881 7820 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2615284828
Short name	T52
Test name
Test status
Simulation time	168040386 ps
CPU time	1.32 seconds
Started	Dec 24 12:27:27 PM PST 23
Finished	Dec 24 12:27:31 PM PST 23
Peak memory	215336 kb
Host	smart-6241b737-51d8-45fd-b0d9-b5a9f4991379
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615284828 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2615284828 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.3033630260
Short name	T80
Test name
Test status
Simulation time	65709664 ps
CPU time	0.95 seconds
Started	Dec 24 12:27:17 PM PST 23
Finished	Dec 24 12:27:22 PM PST 23
Peak memory	206968 kb
Host	smart-04809a59-55e2-45d1-928c-3de042bc5b03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033630260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3033630260 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.1722979251
Short name	T1210
Test name
Test status
Simulation time	54323268 ps
CPU time	0.76 seconds
Started	Dec 24 12:28:31 PM PST 23
Finished	Dec 24 12:28:39 PM PST 23
Peak memory	207004 kb
Host	smart-39a078e6-3b3b-4941-ab91-1fdf6a1c4ec1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722979251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1722979251 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.909984633
Short name	T1235
Test name
Test status
Simulation time	76264872 ps
CPU time	1.48 seconds
Started	Dec 24 12:27:39 PM PST 23
Finished	Dec 24 12:27:41 PM PST 23
Peak memory	215484 kb
Host	smart-e15315fa-8871-4a0a-a16d-74c5bb07719e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909984633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.909984633 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3921215145
Short name	T1224
Test name
Test status
Simulation time	36605187 ps
CPU time	1.39 seconds
Started	Dec 24 12:30:45 PM PST 23
Finished	Dec 24 12:31:12 PM PST 23
Peak memory	214312 kb
Host	smart-09738bbd-7bc0-4bad-b259-18c2c92529a7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921215145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.3921215145 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.244059957
Short name	T1233
Test name
Test status
Simulation time	83977618 ps
CPU time	1.59 seconds
Started	Dec 24 12:30:07 PM PST 23
Finished	Dec 24 12:30:33 PM PST 23
Peak memory	215528 kb
Host	smart-612effcb-bb76-4392-b395-210d11b0cf16
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244059957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac _shadow_reg_errors_with_csr_rw.244059957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.4151382699
Short name	T174
Test name
Test status
Simulation time	199039091 ps
CPU time	1.51 seconds
Started	Dec 24 12:28:30 PM PST 23
Finished	Dec 24 12:28:39 PM PST 23
Peak memory	215464 kb
Host	smart-ef2b9a72-4fbe-4cca-9b7d-90ce7600b87f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151382699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4151382699 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.246781463
Short name	T1171
Test name
Test status
Simulation time	457924435 ps
CPU time	5.35 seconds
Started	Dec 24 12:28:30 PM PST 23
Finished	Dec 24 12:28:43 PM PST 23
Peak memory	207248 kb
Host	smart-87f0ca7d-9267-4647-b0c3-aa51e32a1beb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246781463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.24678146 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3124784530
Short name	T1155
Test name
Test status
Simulation time	626355334 ps
CPU time	8.16 seconds
Started	Dec 24 12:28:54 PM PST 23
Finished	Dec 24 12:29:12 PM PST 23
Peak memory	206356 kb
Host	smart-50d57709-a885-4cde-83d9-efa10346c9b8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124784530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3124784 530 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.426902191
Short name	T1216
Test name
Test status
Simulation time	60721864 ps
CPU time	0.92 seconds
Started	Dec 24 12:27:11 PM PST 23
Finished	Dec 24 12:27:15 PM PST 23
Peak memory	206936 kb
Host	smart-4653e5b7-4ba5-4ed5-8699-44fb357b7ba3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426902191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.42690219 1 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4264119202
Short name	T93
Test name
Test status
Simulation time	145022660 ps
CPU time	1.15 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:53 PM PST 23
Peak memory	215464 kb
Host	smart-edac4b47-5574-4780-8bc3-47237bb672be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264119202 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.4264119202 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2205112435
Short name	T1244
Test name
Test status
Simulation time	28201823 ps
CPU time	0.99 seconds
Started	Dec 24 12:28:41 PM PST 23
Finished	Dec 24 12:28:48 PM PST 23
Peak memory	207344 kb
Host	smart-15dfa2ed-0e92-47c0-8022-cdd221bf5c5b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205112435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2205112435 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3950756893
Short name	T1239
Test name
Test status
Simulation time	14598248 ps
CPU time	0.71 seconds
Started	Dec 24 12:29:56 PM PST 23
Finished	Dec 24 12:30:23 PM PST 23
Peak memory	206992 kb
Host	smart-2fb5dd9a-db3b-4ebb-b978-3e0644b43134
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950756893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3950756893 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.3849575236
Short name	T1156
Test name
Test status
Simulation time	120701762 ps
CPU time	0.7 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	207336 kb
Host	smart-c92d2cf4-29bc-46c5-8882-d61b28a69c6e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849575236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3849575236 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2074447786
Short name	T170
Test name
Test status
Simulation time	203002036 ps
CPU time	2.24 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	215356 kb
Host	smart-2b573c62-7099-4e6d-a686-453a71d7eca9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074447786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2074447786 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3361818429
Short name	T1215
Test name
Test status
Simulation time	70307870 ps
CPU time	1 seconds
Started	Dec 24 12:27:13 PM PST 23
Finished	Dec 24 12:27:16 PM PST 23
Peak memory	207148 kb
Host	smart-ddbe77b7-a980-4ab5-b090-a807d32b5683
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361818429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.3361818429 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.254240134
Short name	T1220
Test name
Test status
Simulation time	134658055 ps
CPU time	2.68 seconds
Started	Dec 24 12:27:19 PM PST 23
Finished	Dec 24 12:27:25 PM PST 23
Peak memory	215720 kb
Host	smart-c0560d66-2b73-4ecc-aa15-0f0a063d3963
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254240134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_ shadow_reg_errors_with_csr_rw.254240134 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.261293309
Short name	T56
Test name
Test status
Simulation time	132704141 ps
CPU time	3.12 seconds
Started	Dec 24 12:27:06 PM PST 23
Finished	Dec 24 12:27:14 PM PST 23
Peak memory	215524 kb
Host	smart-44bae259-fd51-46a7-994d-65360a641a6e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261293309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.261293309 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2360066495
Short name	T142
Test name
Test status
Simulation time	2286331814 ps
CPU time	2.68 seconds
Started	Dec 24 12:29:09 PM PST 23
Finished	Dec 24 12:29:15 PM PST 23
Peak memory	215208 kb
Host	smart-ef78a664-ca0f-4b22-bdea-12699c21b69f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360066495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.23600 66495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.1573009300
Short name	T1222
Test name
Test status
Simulation time	131320113 ps
CPU time	0.74 seconds
Started	Dec 24 12:28:27 PM PST 23
Finished	Dec 24 12:28:36 PM PST 23
Peak memory	206968 kb
Host	smart-5d49b164-d576-483a-ad76-735d13a9e825
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573009300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1573009300 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.1969465648
Short name	T1261
Test name
Test status
Simulation time	91744155 ps
CPU time	0.76 seconds
Started	Dec 24 12:27:44 PM PST 23
Finished	Dec 24 12:27:56 PM PST 23
Peak memory	206900 kb
Host	smart-08e39ae6-e06f-401b-8592-13aa22fdae9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969465648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1969465648 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.3150779168
Short name	T1265
Test name
Test status
Simulation time	35006278 ps
CPU time	0.72 seconds
Started	Dec 24 12:28:22 PM PST 23
Finished	Dec 24 12:28:33 PM PST 23
Peak memory	207048 kb
Host	smart-bd44d3e9-7a49-4a88-a234-9ead6687972f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150779168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3150779168 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.3495001974
Short name	T151
Test name
Test status
Simulation time	20650032 ps
CPU time	0.79 seconds
Started	Dec 24 12:27:52 PM PST 23
Finished	Dec 24 12:28:00 PM PST 23
Peak memory	207028 kb
Host	smart-c3f2e7cf-6ea9-46ef-841c-3324cf4788b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495001974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3495001974 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3721812193
Short name	T1164
Test name
Test status
Simulation time	15016520 ps
CPU time	0.75 seconds
Started	Dec 24 12:28:30 PM PST 23
Finished	Dec 24 12:28:38 PM PST 23
Peak memory	206980 kb
Host	smart-1fc2e5dc-718a-4cec-a1f9-32830b9724f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721812193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3721812193 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.430903382
Short name	T1195
Test name
Test status
Simulation time	20359867 ps
CPU time	0.75 seconds
Started	Dec 24 12:27:35 PM PST 23
Finished	Dec 24 12:27:37 PM PST 23
Peak memory	207028 kb
Host	smart-472ef00a-802e-4f1c-b500-42c4bfaa2bd5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430903382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.430903382 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3829880532
Short name	T1161
Test name
Test status
Simulation time	124487249 ps
CPU time	0.72 seconds
Started	Dec 24 12:28:47 PM PST 23
Finished	Dec 24 12:28:57 PM PST 23
Peak memory	206952 kb
Host	smart-ecebd3bb-0acd-4bca-a14c-8099166bfa46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829880532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3829880532 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.458254269
Short name	T1232
Test name
Test status
Simulation time	297662108 ps
CPU time	5.77 seconds
Started	Dec 24 12:27:36 PM PST 23
Finished	Dec 24 12:27:43 PM PST 23
Peak memory	207256 kb
Host	smart-692269bc-24ae-4800-8b40-5603242d2428
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458254269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.45825426 9 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.766522969
Short name	T1152
Test name
Test status
Simulation time	1211592205 ps
CPU time	16.86 seconds
Started	Dec 24 12:28:11 PM PST 23
Finished	Dec 24 12:28:43 PM PST 23
Peak memory	207336 kb
Host	smart-5420b35c-a8e4-48b3-8a22-29a0795c10c5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766522969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.76652296 9 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.217041293
Short name	T141
Test name
Test status
Simulation time	34206238 ps
CPU time	1.2 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:19 PM PST 23
Peak memory	207260 kb
Host	smart-f8fde923-5a21-4a64-8bfd-d9d7136b4e4a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217041293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.21704129 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3161461026
Short name	T1199
Test name
Test status
Simulation time	565674173 ps
CPU time	1.81 seconds
Started	Dec 24 12:29:22 PM PST 23
Finished	Dec 24 12:29:34 PM PST 23
Peak memory	223312 kb
Host	smart-a645425d-c0b9-4413-93b4-660620ff11ba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161461026 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3161461026 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3339544704
Short name	T137
Test name
Test status
Simulation time	62759799 ps
CPU time	1.07 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:28:55 PM PST 23
Peak memory	207300 kb
Host	smart-696f0005-1941-4452-ba83-1bb231d86741
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339544704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3339544704 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.667981754
Short name	T1226
Test name
Test status
Simulation time	42534169 ps
CPU time	0.72 seconds
Started	Dec 24 12:29:34 PM PST 23
Finished	Dec 24 12:29:49 PM PST 23
Peak memory	206988 kb
Host	smart-736e37fc-0747-4201-a431-16c06e05c68c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667981754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.667981754 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1132289972
Short name	T123
Test name
Test status
Simulation time	40562357 ps
CPU time	1.31 seconds
Started	Dec 24 12:28:04 PM PST 23
Finished	Dec 24 12:28:17 PM PST 23
Peak memory	215168 kb
Host	smart-01c8764b-bacb-4ec7-90ab-e66440b4489c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132289972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1132289972 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3110379494
Short name	T1263
Test name
Test status
Simulation time	29530806 ps
CPU time	0.67 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:43 PM PST 23
Peak memory	206940 kb
Host	smart-8bba5700-95fa-4fae-998f-d29ce8c18c7a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110379494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3110379494 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3629533675
Short name	T57
Test name
Test status
Simulation time	128925180 ps
CPU time	1.59 seconds
Started	Dec 24 12:28:48 PM PST 23
Finished	Dec 24 12:28:59 PM PST 23
Peak memory	215500 kb
Host	smart-c2a71891-c764-41e4-a0b3-bfaa1cf6552e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629533675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3629533675 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3141859666
Short name	T101
Test name
Test status
Simulation time	176543396 ps
CPU time	1.22 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:19 PM PST 23
Peak memory	215728 kb
Host	smart-4ea2973c-287f-4626-b71f-64e785af32fb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141859666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.3141859666 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1776744524
Short name	T99
Test name
Test status
Simulation time	29578930 ps
CPU time	1.61 seconds
Started	Dec 24 12:27:11 PM PST 23
Finished	Dec 24 12:27:16 PM PST 23
Peak memory	215792 kb
Host	smart-bc16af7f-cc44-4d13-a1f6-39910261dd82
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776744524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.1776744524 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3881232569
Short name	T85
Test name
Test status
Simulation time	316283312 ps
CPU time	2.17 seconds
Started	Dec 24 12:28:42 PM PST 23
Finished	Dec 24 12:28:51 PM PST 23
Peak memory	215472 kb
Host	smart-500a33fe-8579-4d8a-9777-bd3abbec49fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881232569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3881232569 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2091640871
Short name	T1212
Test name
Test status
Simulation time	100202716 ps
CPU time	2.44 seconds
Started	Dec 24 12:28:02 PM PST 23
Finished	Dec 24 12:28:17 PM PST 23
Peak memory	215412 kb
Host	smart-828c99a2-8d38-47ad-a4f3-bbebfaaac377
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091640871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.20916 40871 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.84595164
Short name	T1250
Test name
Test status
Simulation time	16612097 ps
CPU time	0.75 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:28:53 PM PST 23
Peak memory	207044 kb
Host	smart-c95df11f-2721-4870-bcde-3ab21119c499
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84595164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.84595164 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2111171567
Short name	T53
Test name
Test status
Simulation time	24373927 ps
CPU time	0.76 seconds
Started	Dec 24 12:28:41 PM PST 23
Finished	Dec 24 12:28:48 PM PST 23
Peak memory	206968 kb
Host	smart-4b5b35b6-ae78-41f8-ba50-fd949ccf29f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111171567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2111171567 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.1607973096
Short name	T1179
Test name
Test status
Simulation time	14789200 ps
CPU time	0.76 seconds
Started	Dec 24 12:28:39 PM PST 23
Finished	Dec 24 12:28:45 PM PST 23
Peak memory	207044 kb
Host	smart-05d68f71-f737-47c6-9a27-72654c7324a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607973096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1607973096 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.4231065283
Short name	T172
Test name
Test status
Simulation time	38402101 ps
CPU time	0.76 seconds
Started	Dec 24 12:27:43 PM PST 23
Finished	Dec 24 12:27:55 PM PST 23
Peak memory	207064 kb
Host	smart-8dc1d097-1186-4e53-99a8-fff45291cff6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231065283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.4231065283 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.670988340
Short name	T1207
Test name
Test status
Simulation time	25613440 ps
CPU time	0.84 seconds
Started	Dec 24 12:28:14 PM PST 23
Finished	Dec 24 12:28:28 PM PST 23
Peak memory	206948 kb
Host	smart-11fff354-0db6-4e82-93a2-6aa78ec8ff66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670988340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.670988340 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2255286869
Short name	T1184
Test name
Test status
Simulation time	44510685 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:50 PM PST 23
Finished	Dec 24 12:29:02 PM PST 23
Peak memory	206944 kb
Host	smart-7e99bc05-65c8-4473-a74a-09139b49537d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255286869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2255286869 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.2753667430
Short name	T1185
Test name
Test status
Simulation time	67168084 ps
CPU time	0.75 seconds
Started	Dec 24 12:28:25 PM PST 23
Finished	Dec 24 12:28:35 PM PST 23
Peak memory	206964 kb
Host	smart-87cdee59-e60f-48ac-9f75-870b2113e3b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753667430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2753667430 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.594492163
Short name	T1182
Test name
Test status
Simulation time	15271133 ps
CPU time	0.73 seconds
Started	Dec 24 12:28:01 PM PST 23
Finished	Dec 24 12:28:15 PM PST 23
Peak memory	206984 kb
Host	smart-565e68d9-95ea-4c1e-8874-4b6c756b7ec0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594492163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.594492163 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2142535602
Short name	T1149
Test name
Test status
Simulation time	54732629 ps
CPU time	0.74 seconds
Started	Dec 24 12:28:07 PM PST 23
Finished	Dec 24 12:28:21 PM PST 23
Peak memory	207112 kb
Host	smart-80be2f0a-5713-4c44-af32-eae54275d647
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142535602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2142535602 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.2444842905
Short name	T1159
Test name
Test status
Simulation time	14561594 ps
CPU time	0.77 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:28:54 PM PST 23
Peak memory	207044 kb
Host	smart-a8f88c7b-ee45-4a7a-8837-dd129fdffeed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444842905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2444842905 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.4158366741
Short name	T1234
Test name
Test status
Simulation time	164615374 ps
CPU time	8.37 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:33 PM PST 23
Peak memory	207084 kb
Host	smart-2001e967-f916-48b1-8564-7d9381b8d25b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158366741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.4158366 741 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2964580103
Short name	T1154
Test name
Test status
Simulation time	634159769 ps
CPU time	15.92 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:29:08 PM PST 23
Peak memory	207136 kb
Host	smart-46c500f3-2570-4f58-a9e4-e356a8f0d5b2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964580103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2964580 103 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1574751809
Short name	T92
Test name
Test status
Simulation time	71091421 ps
CPU time	1.01 seconds
Started	Dec 24 12:27:58 PM PST 23
Finished	Dec 24 12:28:12 PM PST 23
Peak memory	207152 kb
Host	smart-0e31a01e-fa6e-44d6-8c7c-1ab553ec1565
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574751809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1574751 809 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2282191728
Short name	T128
Test name
Test status
Simulation time	84699586 ps
CPU time	1.96 seconds
Started	Dec 24 12:28:04 PM PST 23
Finished	Dec 24 12:28:24 PM PST 23
Peak memory	223560 kb
Host	smart-8f860ff5-7a5b-465d-bf8e-a30178081cea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282191728 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2282191728 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.1316523576
Short name	T1153
Test name
Test status
Simulation time	131809709 ps
CPU time	0.97 seconds
Started	Dec 24 12:29:04 PM PST 23
Finished	Dec 24 12:29:12 PM PST 23
Peak memory	207096 kb
Host	smart-5d649ff3-a8b5-4f76-a6a9-66028febcbb7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316523576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1316523576 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.1595156142
Short name	T177
Test name
Test status
Simulation time	22210953 ps
CPU time	0.76 seconds
Started	Dec 24 12:29:50 PM PST 23
Finished	Dec 24 12:30:14 PM PST 23
Peak memory	207100 kb
Host	smart-9329c7a8-566e-4ccd-9916-3da6cc739316
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595156142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1595156142 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.827377342
Short name	T134
Test name
Test status
Simulation time	125893888 ps
CPU time	1.38 seconds
Started	Dec 24 12:27:59 PM PST 23
Finished	Dec 24 12:28:13 PM PST 23
Peak memory	215360 kb
Host	smart-111a9ca0-122b-4ae6-b52d-680624b29f32
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827377342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial _access.827377342 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2166437057
Short name	T130
Test name
Test status
Simulation time	42961177 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:10 PM PST 23
Finished	Dec 24 12:29:14 PM PST 23
Peak memory	207044 kb
Host	smart-3d008d86-e184-44f2-8a7b-a7822e1212a2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166437057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2166437057 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1425014166
Short name	T1237
Test name
Test status
Simulation time	27288100 ps
CPU time	1.38 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	207176 kb
Host	smart-b0fbfeea-b340-42c6-8ca9-bd027496d692
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425014166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.1425014166 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2967215834
Short name	T107
Test name
Test status
Simulation time	36141017 ps
CPU time	1.04 seconds
Started	Dec 24 12:28:55 PM PST 23
Finished	Dec 24 12:29:07 PM PST 23
Peak memory	215720 kb
Host	smart-e51b40cb-2bdd-47b1-8036-b25a9db0cb7c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967215834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2967215834 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3325967126
Short name	T1262
Test name
Test status
Simulation time	113078005 ps
CPU time	2.92 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	215568 kb
Host	smart-c864324b-eb79-491b-8a64-4bf78725193f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325967126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3325967126 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3266532779
Short name	T153
Test name
Test status
Simulation time	220807722 ps
CPU time	4.83 seconds
Started	Dec 24 12:28:55 PM PST 23
Finished	Dec 24 12:29:11 PM PST 23
Peak memory	215388 kb
Host	smart-7b5698dc-d192-4b3c-a028-71a129a38423
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266532779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.32665 32779 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.2076633198
Short name	T152
Test name
Test status
Simulation time	48563135 ps
CPU time	0.71 seconds
Started	Dec 24 12:27:55 PM PST 23
Finished	Dec 24 12:28:07 PM PST 23
Peak memory	207112 kb
Host	smart-1e7c5b6b-727e-4dd9-93a7-c4bd1dc3d369
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076633198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2076633198 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1886427963
Short name	T1266
Test name
Test status
Simulation time	39127678 ps
CPU time	0.73 seconds
Started	Dec 24 12:27:41 PM PST 23
Finished	Dec 24 12:27:45 PM PST 23
Peak memory	207056 kb
Host	smart-2627f233-d732-41ff-b4a8-2269313e4c99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886427963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1886427963 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.3057914338
Short name	T1219
Test name
Test status
Simulation time	15676120 ps
CPU time	0.72 seconds
Started	Dec 24 12:27:57 PM PST 23
Finished	Dec 24 12:28:10 PM PST 23
Peak memory	206972 kb
Host	smart-20b38e7b-384a-4daa-a5e3-2bdc11fa7eee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057914338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3057914338 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.2859478875
Short name	T168
Test name
Test status
Simulation time	13733479 ps
CPU time	0.75 seconds
Started	Dec 24 12:28:21 PM PST 23
Finished	Dec 24 12:28:33 PM PST 23
Peak memory	206972 kb
Host	smart-d89f80eb-8c1c-4acf-8c16-2defe9823edb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859478875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2859478875 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.3028072446
Short name	T127
Test name
Test status
Simulation time	20104794 ps
CPU time	0.73 seconds
Started	Dec 24 12:28:08 PM PST 23
Finished	Dec 24 12:28:28 PM PST 23
Peak memory	207044 kb
Host	smart-e74a8600-f142-4abb-8304-e6eb79189632
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028072446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3028072446 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1799847012
Short name	T1187
Test name
Test status
Simulation time	24936943 ps
CPU time	0.75 seconds
Started	Dec 24 12:27:32 PM PST 23
Finished	Dec 24 12:27:34 PM PST 23
Peak memory	206808 kb
Host	smart-d5e3bf80-5b81-4bf4-a91a-6e326e125478
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799847012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1799847012 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.3418714604
Short name	T1204
Test name
Test status
Simulation time	26695455 ps
CPU time	0.74 seconds
Started	Dec 24 12:28:03 PM PST 23
Finished	Dec 24 12:28:16 PM PST 23
Peak memory	207092 kb
Host	smart-6fdc0d8d-b5d2-4f77-b4e8-d461331a307d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418714604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3418714604 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.1106984932
Short name	T54
Test name
Test status
Simulation time	24780491 ps
CPU time	0.76 seconds
Started	Dec 24 12:30:52 PM PST 23
Finished	Dec 24 12:31:16 PM PST 23
Peak memory	206128 kb
Host	smart-ec93314a-7866-4a71-aae2-2291416f9b61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106984932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1106984932 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2204597151
Short name	T1260
Test name
Test status
Simulation time	16169366 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:40 PM PST 23
Finished	Dec 24 12:28:47 PM PST 23
Peak memory	206988 kb
Host	smart-81ae5579-c841-4314-95aa-a285b70e8abf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204597151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2204597151 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.6420447
Short name	T1188
Test name
Test status
Simulation time	42624587 ps
CPU time	0.78 seconds
Started	Dec 24 12:28:36 PM PST 23
Finished	Dec 24 12:28:43 PM PST 23
Peak memory	207044 kb
Host	smart-0374ec43-7b6f-4c27-a7e5-304ab7fe871e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6420447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.6420447 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.258842224
Short name	T1175
Test name
Test status
Simulation time	26827955 ps
CPU time	1.16 seconds
Started	Dec 24 12:27:33 PM PST 23
Finished	Dec 24 12:27:35 PM PST 23
Peak memory	215360 kb
Host	smart-9d2a7c1f-2bee-4195-a058-3884211443be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258842224 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.258842224 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3353111297
Short name	T118
Test name
Test status
Simulation time	28483636 ps
CPU time	0.95 seconds
Started	Dec 24 12:27:58 PM PST 23
Finished	Dec 24 12:28:13 PM PST 23
Peak memory	206944 kb
Host	smart-b24c99ba-ea1d-45ec-b8f0-740ddb8fb82c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353111297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3353111297 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.2120674926
Short name	T1217
Test name
Test status
Simulation time	17461183 ps
CPU time	0.76 seconds
Started	Dec 24 12:29:25 PM PST 23
Finished	Dec 24 12:29:34 PM PST 23
Peak memory	207004 kb
Host	smart-5da0f171-4e57-4ca5-8e9a-9d73445c7265
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120674926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2120674926 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.729289082
Short name	T173
Test name
Test status
Simulation time	29502909 ps
CPU time	1.41 seconds
Started	Dec 24 12:27:44 PM PST 23
Finished	Dec 24 12:27:57 PM PST 23
Peak memory	207220 kb
Host	smart-8c216954-c38a-440d-b6b7-839567f98baf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729289082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_ outstanding.729289082 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3710255673
Short name	T120
Test name
Test status
Simulation time	97498965 ps
CPU time	1.04 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:56 PM PST 23
Peak memory	215656 kb
Host	smart-cb6317a8-3deb-4f3c-ad3b-4c8e06dacba4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710255673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.3710255673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1639285494
Short name	T1264
Test name
Test status
Simulation time	533250073 ps
CPU time	2.96 seconds
Started	Dec 24 12:28:54 PM PST 23
Finished	Dec 24 12:29:07 PM PST 23
Peak memory	223852 kb
Host	smart-3b2d0e12-21c1-41c1-b1e2-924ff37a0241
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639285494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.1639285494 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.2839868835
Short name	T1163
Test name
Test status
Simulation time	55363776 ps
CPU time	1.87 seconds
Started	Dec 24 12:28:51 PM PST 23
Finished	Dec 24 12:29:03 PM PST 23
Peak memory	215536 kb
Host	smart-69d1c574-cceb-4081-96cb-dddb2995409f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839868835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2839868835 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1811090029
Short name	T157
Test name
Test status
Simulation time	205277154 ps
CPU time	2.37 seconds
Started	Dec 24 12:28:53 PM PST 23
Finished	Dec 24 12:29:10 PM PST 23
Peak memory	215320 kb
Host	smart-62aa20af-11c2-4ad3-adbb-da27b6d06af7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811090029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.18110 90029 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2067032107
Short name	T1160
Test name
Test status
Simulation time	32932398 ps
CPU time	1.57 seconds
Started	Dec 24 12:29:24 PM PST 23
Finished	Dec 24 12:29:34 PM PST 23
Peak memory	223672 kb
Host	smart-0af55024-1767-46c8-ada6-05ac8506eac7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067032107 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2067032107 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.4278551745
Short name	T125
Test name
Test status
Simulation time	41612551 ps
CPU time	0.94 seconds
Started	Dec 24 12:28:40 PM PST 23
Finished	Dec 24 12:28:53 PM PST 23
Peak memory	207020 kb
Host	smart-aad838c6-ec6c-447f-965e-13e107a92777
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278551745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.4278551745 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2024759068
Short name	T1248
Test name
Test status
Simulation time	17323614 ps
CPU time	0.72 seconds
Started	Dec 24 12:31:26 PM PST 23
Finished	Dec 24 12:31:53 PM PST 23
Peak memory	206756 kb
Host	smart-2ca09dee-ad14-4643-854f-91c2061d1dc2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024759068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2024759068 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2537527450
Short name	T1170
Test name
Test status
Simulation time	41361098 ps
CPU time	2.36 seconds
Started	Dec 24 12:29:21 PM PST 23
Finished	Dec 24 12:29:34 PM PST 23
Peak memory	207448 kb
Host	smart-7339e585-9470-43fa-975f-76919fe33c9a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537527450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2537527450 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.247465090
Short name	T1208
Test name
Test status
Simulation time	63364308 ps
CPU time	1.13 seconds
Started	Dec 24 12:30:17 PM PST 23
Finished	Dec 24 12:30:41 PM PST 23
Peak memory	215576 kb
Host	smart-025835bc-b558-4fa3-93c0-a86e17c64b30
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247465090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e rrors.247465090 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2788802620
Short name	T1189
Test name
Test status
Simulation time	39907447 ps
CPU time	1.68 seconds
Started	Dec 24 12:27:54 PM PST 23
Finished	Dec 24 12:28:10 PM PST 23
Peak memory	223116 kb
Host	smart-fb04b3f2-c99c-4dcb-9fb8-e950aa3a6a86
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788802620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.2788802620 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3741017786
Short name	T1252
Test name
Test status
Simulation time	423693683 ps
CPU time	3.37 seconds
Started	Dec 24 12:31:20 PM PST 23
Finished	Dec 24 12:31:50 PM PST 23
Peak memory	214196 kb
Host	smart-22d97b2f-60a8-4be9-afdf-0bb78e7eed42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741017786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3741017786 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1930101695
Short name	T1259
Test name
Test status
Simulation time	361628115 ps
CPU time	4.11 seconds
Started	Dec 24 12:28:45 PM PST 23
Finished	Dec 24 12:28:57 PM PST 23
Peak memory	223520 kb
Host	smart-968525c8-e9e4-4171-9d0b-a547432e5f4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930101695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.19301 01695 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3878445715
Short name	T1196
Test name
Test status
Simulation time	72337729 ps
CPU time	1.57 seconds
Started	Dec 24 12:27:14 PM PST 23
Finished	Dec 24 12:27:18 PM PST 23
Peak memory	215320 kb
Host	smart-df6914a4-262d-4ea5-91c8-ed8c602f1949
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878445715 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3878445715 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3192876574
Short name	T90
Test name
Test status
Simulation time	21114009 ps
CPU time	1.05 seconds
Started	Dec 24 12:30:45 PM PST 23
Finished	Dec 24 12:31:12 PM PST 23
Peak memory	206580 kb
Host	smart-6887624e-21b7-47f9-b255-3d53a78c0d60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192876574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3192876574 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.3409152139
Short name	T140
Test name
Test status
Simulation time	77767734 ps
CPU time	0.78 seconds
Started	Dec 24 12:29:14 PM PST 23
Finished	Dec 24 12:29:18 PM PST 23
Peak memory	207024 kb
Host	smart-77d5e0a3-4ebf-48a6-8f31-43c5315ea72e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409152139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3409152139 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1713081176
Short name	T1225
Test name
Test status
Simulation time	146808110 ps
CPU time	1.64 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:20 PM PST 23
Peak memory	215364 kb
Host	smart-5414c59c-2ab6-45df-a32c-915156585abb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713081176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.1713081176 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.291832102
Short name	T1173
Test name
Test status
Simulation time	40082932 ps
CPU time	1.17 seconds
Started	Dec 24 12:28:36 PM PST 23
Finished	Dec 24 12:28:43 PM PST 23
Peak memory	215536 kb
Host	smart-e9ed4317-ee1f-49da-af2e-ed8ca6257a02
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291832102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e rrors.291832102 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1321201285
Short name	T1231
Test name
Test status
Simulation time	108725737 ps
CPU time	3.15 seconds
Started	Dec 24 12:29:27 PM PST 23
Finished	Dec 24 12:29:40 PM PST 23
Peak memory	218864 kb
Host	smart-3557db41-75e5-40e5-8895-8c00ea0bd683
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321201285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1321201285 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1162078535
Short name	T1198
Test name
Test status
Simulation time	55933751 ps
CPU time	2.51 seconds
Started	Dec 24 12:27:57 PM PST 23
Finished	Dec 24 12:28:12 PM PST 23
Peak memory	215452 kb
Host	smart-7b4fa78a-0484-4245-b5ea-7d172ffc5a76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162078535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.11620 78535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2925224243
Short name	T129
Test name
Test status
Simulation time	32947433 ps
CPU time	1.79 seconds
Started	Dec 24 12:27:21 PM PST 23
Finished	Dec 24 12:27:26 PM PST 23
Peak memory	215344 kb
Host	smart-fc1462a3-b03e-41ae-84aa-b76cc7e1efee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925224243 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2925224243 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1624546792
Short name	T1178
Test name
Test status
Simulation time	43461428 ps
CPU time	0.91 seconds
Started	Dec 24 12:28:10 PM PST 23
Finished	Dec 24 12:28:26 PM PST 23
Peak memory	207024 kb
Host	smart-5249cb3f-fb71-4406-b5b2-3b894e48ad60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624546792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1624546792 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.3830545032
Short name	T1211
Test name
Test status
Simulation time	23236161 ps
CPU time	0.74 seconds
Started	Dec 24 12:27:29 PM PST 23
Finished	Dec 24 12:27:32 PM PST 23
Peak memory	206996 kb
Host	smart-df296a96-3ff6-4991-9e37-d2acbf2bc4de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830545032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3830545032 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3710191161
Short name	T176
Test name
Test status
Simulation time	69910073 ps
CPU time	1.67 seconds
Started	Dec 24 12:30:16 PM PST 23
Finished	Dec 24 12:30:40 PM PST 23
Peak memory	215176 kb
Host	smart-5e0c922b-80e7-435a-b5c8-0d4ffb6cd96a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710191161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.3710191161 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.850424324
Short name	T1213
Test name
Test status
Simulation time	47232743 ps
CPU time	1.09 seconds
Started	Dec 24 12:32:02 PM PST 23
Finished	Dec 24 12:32:28 PM PST 23
Peak memory	215724 kb
Host	smart-84f05bb6-1453-4ab9-ac36-1dfb48b71d7e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850424324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e rrors.850424324 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3262782788
Short name	T58
Test name
Test status
Simulation time	522161998 ps
CPU time	3.02 seconds
Started	Dec 24 12:27:16 PM PST 23
Finished	Dec 24 12:27:23 PM PST 23
Peak memory	215824 kb
Host	smart-4c13ea88-db97-4705-83da-b1126c957eb2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262782788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.3262782788 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3404790269
Short name	T1258
Test name
Test status
Simulation time	127043417 ps
CPU time	2.82 seconds
Started	Dec 24 12:31:24 PM PST 23
Finished	Dec 24 12:31:52 PM PST 23
Peak memory	215484 kb
Host	smart-4c411a8b-907b-4cd5-b714-09863307d4b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404790269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3404790269 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2579465085
Short name	T113
Test name
Test status
Simulation time	214336096 ps
CPU time	2.46 seconds
Started	Dec 24 12:28:42 PM PST 23
Finished	Dec 24 12:28:51 PM PST 23
Peak memory	215208 kb
Host	smart-6329e1c7-87f6-4680-b412-fbb01cf7b1ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579465085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.25794 65085 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1619788008
Short name	T84
Test name
Test status
Simulation time	69688028 ps
CPU time	1.92 seconds
Started	Dec 24 12:27:20 PM PST 23
Finished	Dec 24 12:27:26 PM PST 23
Peak memory	223544 kb
Host	smart-175538db-6e9e-4da9-81fa-befba6c04bf0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619788008 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1619788008 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.199795350
Short name	T119
Test name
Test status
Simulation time	84426865 ps
CPU time	1.07 seconds
Started	Dec 24 12:28:41 PM PST 23
Finished	Dec 24 12:28:49 PM PST 23
Peak memory	207096 kb
Host	smart-0edfd972-9e2e-4cae-a1c2-e669ccae8fca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199795350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.199795350 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.2010505450
Short name	T1247
Test name
Test status
Simulation time	12774470 ps
CPU time	0.76 seconds
Started	Dec 24 12:30:05 PM PST 23
Finished	Dec 24 12:30:31 PM PST 23
Peak memory	207052 kb
Host	smart-86b9ced6-f84b-491e-86b5-d6cb90d8294c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010505450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2010505450 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2031634994
Short name	T1236
Test name
Test status
Simulation time	93481206 ps
CPU time	2.55 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:21 PM PST 23
Peak memory	215340 kb
Host	smart-9726c74a-9c03-4b47-8fa3-96ddd5631e63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031634994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.2031634994 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3983503471
Short name	T1227
Test name
Test status
Simulation time	28211576 ps
CPU time	1.09 seconds
Started	Dec 24 12:27:15 PM PST 23
Finished	Dec 24 12:27:19 PM PST 23
Peak memory	215680 kb
Host	smart-67f31ad6-c3b6-4ae3-8e57-17fccc3ecc44
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983503471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.3983503471 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2207058853
Short name	T1242
Test name
Test status
Simulation time	88416520 ps
CPU time	1.51 seconds
Started	Dec 24 12:27:33 PM PST 23
Finished	Dec 24 12:27:36 PM PST 23
Peak memory	215584 kb
Host	smart-bba4a116-f418-4856-abe3-ecdaab4bec5a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207058853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.2207058853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.2664738208
Short name	T131
Test name
Test status
Simulation time	59734842 ps
CPU time	2.04 seconds
Started	Dec 24 12:28:25 PM PST 23
Finished	Dec 24 12:28:36 PM PST 23
Peak memory	215572 kb
Host	smart-d38eca3b-1e0a-46f3-bd41-c7fee3d11e53
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664738208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2664738208 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.1180961432
Short name	T581
Test name
Test status
Simulation time	18598581 ps
CPU time	0.84 seconds
Started	Dec 24 12:48:11 PM PST 23
Finished	Dec 24 12:48:14 PM PST 23
Peak memory	205176 kb
Host	smart-a5ac49f1-acf3-45ba-910c-ad16a055dc74
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180961432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1180961432 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app.1001901136
Short name	T23
Test name
Test status
Simulation time	11127885367 ps
CPU time	273.94 seconds
Started	Dec 24 12:48:02 PM PST 23
Finished	Dec 24 12:52:38 PM PST 23
Peak memory	244444 kb
Host	smart-93725f32-39c8-4793-960e-46b85041433c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001901136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1001901136 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.185416422
Short name	T285
Test name
Test status
Simulation time	17092527873 ps
CPU time	366.57 seconds
Started	Dec 24 12:48:01 PM PST 23
Finished	Dec 24 12:54:10 PM PST 23
Peak memory	227272 kb
Host	smart-82e0e377-5894-4e89-8605-ce4905514a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185416422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.185416422 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.1319230055
Short name	T507
Test name
Test status
Simulation time	1665450685 ps
CPU time	17.43 seconds
Started	Dec 24 12:48:03 PM PST 23
Finished	Dec 24 12:48:22 PM PST 23
Peak memory	215460 kb
Host	smart-5ed8dff4-e0ee-4c84-aae7-3cb2851e1dab
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1319230055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1319230055 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.3794592672
Short name	T237
Test name
Test status
Simulation time	821343275 ps
CPU time	15.15 seconds
Started	Dec 24 12:48:01 PM PST 23
Finished	Dec 24 12:48:18 PM PST 23
Peak memory	223636 kb
Host	smart-70da9c25-444b-47d7-a3c1-900adca5eec3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3794592672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3794592672 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.1198399933
Short name	T976
Test name
Test status
Simulation time	2478207041 ps
CPU time	18.91 seconds
Started	Dec 24 12:48:09 PM PST 23
Finished	Dec 24 12:48:31 PM PST 23
Peak memory	215572 kb
Host	smart-313a33dc-83b3-4de0-9634-e5df5b7df451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198399933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1198399933 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_error.1270596366
Short name	T713
Test name
Test status
Simulation time	1396441224 ps
CPU time	100.29 seconds
Started	Dec 24 12:48:10 PM PST 23
Finished	Dec 24 12:49:53 PM PST 23
Peak memory	240120 kb
Host	smart-793cf875-09ff-406f-b7c0-d37b405b1e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270596366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1270596366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_key_error.3368298438
Short name	T20
Test name
Test status
Simulation time	233055427 ps
CPU time	1.25 seconds
Started	Dec 24 12:48:05 PM PST 23
Finished	Dec 24 12:48:08 PM PST 23
Peak memory	205624 kb
Host	smart-d8e7aa96-4322-4557-82df-39a0ecd5addb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368298438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3368298438 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.3788573575
Short name	T641
Test name
Test status
Simulation time	140572702 ps
CPU time	1.27 seconds
Started	Dec 24 12:48:03 PM PST 23
Finished	Dec 24 12:48:06 PM PST 23
Peak memory	215648 kb
Host	smart-c740b53e-14bf-4438-99d2-e62058dab070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788573575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3788573575 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.2827379536
Short name	T1038
Test name
Test status
Simulation time	170734820024 ps
CPU time	1862.52 seconds
Started	Dec 24 12:47:59 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	393464 kb
Host	smart-96f2701c-148e-482b-8251-394ff223cc40
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827379536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.2827379536 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.2268341506
Short name	T971
Test name
Test status
Simulation time	972271291 ps
CPU time	64.23 seconds
Started	Dec 24 12:48:05 PM PST 23
Finished	Dec 24 12:49:11 PM PST 23
Peak memory	225764 kb
Host	smart-d5f38d26-fe01-4ac8-ae2d-cd7f13fb3b48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268341506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2268341506 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.413319265
Short name	T12
Test name
Test status
Simulation time	4244049758 ps
CPU time	60.59 seconds
Started	Dec 24 12:48:09 PM PST 23
Finished	Dec 24 12:49:13 PM PST 23
Peak memory	266588 kb
Host	smart-f8a9e7a8-d674-44be-ba44-418943334af1
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413319265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.413319265 +enable_masking =0 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.703264950
Short name	T798
Test name
Test status
Simulation time	1593040388 ps
CPU time	117.11 seconds
Started	Dec 24 12:48:17 PM PST 23
Finished	Dec 24 12:50:16 PM PST 23
Peak memory	231128 kb
Host	smart-d7cd7c65-7c32-4ba4-bd38-5456a252d524
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703264950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.703264950 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.1869958542
Short name	T703
Test name
Test status
Simulation time	1908294543 ps
CPU time	14.37 seconds
Started	Dec 24 12:47:58 PM PST 23
Finished	Dec 24 12:48:14 PM PST 23
Peak memory	218976 kb
Host	smart-757855e2-ac08-430b-bdf3-bd37f1a3baa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869958542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1869958542 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all_with_rand_reset.28776210
Short name	T930
Test name
Test status
Simulation time	15816836602 ps
CPU time	354.52 seconds
Started	Dec 24 12:48:15 PM PST 23
Finished	Dec 24 12:54:12 PM PST 23
Peak memory	268540 kb
Host	smart-8b67dfb2-d72f-44de-8171-13996d282be2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=28776210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.28776210 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.526922547
Short name	T1096
Test name
Test status
Simulation time	342871683 ps
CPU time	4.5 seconds
Started	Dec 24 12:48:01 PM PST 23
Finished	Dec 24 12:48:08 PM PST 23
Peak memory	215572 kb
Host	smart-c35ee312-0c13-4b85-82fc-879b8bb9cdf6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526922547 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.kmac_test_vectors_kmac.526922547 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3306712368
Short name	T354
Test name
Test status
Simulation time	2470579612 ps
CPU time	5.49 seconds
Started	Dec 24 12:48:10 PM PST 23
Finished	Dec 24 12:48:18 PM PST 23
Peak memory	209120 kb
Host	smart-255df31f-9fe6-43b7-9dda-b497b6a747b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306712368 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3306712368 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.2265482153
Short name	T309
Test name
Test status
Simulation time	406427692965 ps
CPU time	2067.41 seconds
Started	Dec 24 12:48:09 PM PST 23
Finished	Dec 24 01:22:39 PM PST 23
Peak memory	392752 kb
Host	smart-79d7d291-b5cd-4d25-a57a-ef79b94ef47c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2265482153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2265482153 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.2951562022
Short name	T630
Test name
Test status
Simulation time	37871265916 ps
CPU time	1452.94 seconds
Started	Dec 24 12:48:18 PM PST 23
Finished	Dec 24 01:12:33 PM PST 23
Peak memory	389960 kb
Host	smart-9b502ded-1667-4525-b13b-3fe6b5b5464f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2951562022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2951562022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.1925847922
Short name	T313
Test name
Test status
Simulation time	95828990137 ps
CPU time	1359.85 seconds
Started	Dec 24 12:48:00 PM PST 23
Finished	Dec 24 01:10:43 PM PST 23
Peak memory	335228 kb
Host	smart-e4008e74-4bfe-4d94-92c6-d013b615dcd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1925847922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1925847922 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.2205273444
Short name	T571
Test name
Test status
Simulation time	222511316565 ps
CPU time	1015.13 seconds
Started	Dec 24 12:48:10 PM PST 23
Finished	Dec 24 01:05:08 PM PST 23
Peak memory	295184 kb
Host	smart-2380e2b7-3687-4dd6-a64b-7f88acbdf913
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2205273444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2205273444 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.2994080447
Short name	T591
Test name
Test status
Simulation time	211007637966 ps
CPU time	4160.98 seconds
Started	Dec 24 12:48:20 PM PST 23
Finished	Dec 24 01:57:42 PM PST 23
Peak memory	645604 kb
Host	smart-1a7a97ee-d7d3-41aa-a89e-e4b29655eee6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2994080447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2994080447 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.2772887487
Short name	T310
Test name
Test status
Simulation time	251006526534 ps
CPU time	4335.74 seconds
Started	Dec 24 12:48:22 PM PST 23
Finished	Dec 24 02:00:40 PM PST 23
Peak memory	559104 kb
Host	smart-9a51ad36-f6db-463c-9e04-3b2d7899686c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2772887487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2772887487 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.786010030
Short name	T803
Test name
Test status
Simulation time	56181256 ps
CPU time	0.78 seconds
Started	Dec 24 12:48:07 PM PST 23
Finished	Dec 24 12:48:11 PM PST 23
Peak memory	205196 kb
Host	smart-152195a0-30fb-436b-9a12-71dd1cd439b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786010030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.786010030 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.4238945637
Short name	T277
Test name
Test status
Simulation time	86189157 ps
CPU time	1.41 seconds
Started	Dec 24 12:48:19 PM PST 23
Finished	Dec 24 12:48:21 PM PST 23
Peak memory	220008 kb
Host	smart-82b8ced6-a113-499c-8199-12cac16e6102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238945637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4238945637 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.3119469577
Short name	T540
Test name
Test status
Simulation time	7385941135 ps
CPU time	145.08 seconds
Started	Dec 24 12:48:16 PM PST 23
Finished	Dec 24 12:50:43 PM PST 23
Peak memory	223236 kb
Host	smart-2a104c43-49ca-4d45-916a-8eec5234d535
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119469577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3119469577 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.3544895730
Short name	T915
Test name
Test status
Simulation time	451130583 ps
CPU time	31.13 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 12:48:57 PM PST 23
Peak memory	236972 kb
Host	smart-726a53f6-afe1-4a02-a8c7-ec899777b46d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3544895730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3544895730 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.2585876669
Short name	T1112
Test name
Test status
Simulation time	2704566889 ps
CPU time	35.56 seconds
Started	Dec 24 12:48:02 PM PST 23
Finished	Dec 24 12:48:40 PM PST 23
Peak memory	220084 kb
Host	smart-fa5c711a-2a0b-464d-9726-3456f3ed6064
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2585876669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2585876669 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.3457059863
Short name	T757
Test name
Test status
Simulation time	51214834439 ps
CPU time	53.44 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 12:49:19 PM PST 23
Peak memory	215744 kb
Host	smart-7b056f8e-c8c5-4264-b5cb-f950d83db236
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457059863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3457059863 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.1969611149
Short name	T948
Test name
Test status
Simulation time	1226995652 ps
CPU time	9.62 seconds
Started	Dec 24 12:48:05 PM PST 23
Finished	Dec 24 12:48:16 PM PST 23
Peak memory	223764 kb
Host	smart-a1c1b2de-3f83-4ca4-8c35-4e00a24c7b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969611149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1969611149 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.1200811711
Short name	T920
Test name
Test status
Simulation time	40174470260 ps
CPU time	284.81 seconds
Started	Dec 24 12:48:18 PM PST 23
Finished	Dec 24 12:53:05 PM PST 23
Peak memory	264864 kb
Host	smart-c343f301-9988-484c-bfa2-00f778c2c4e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200811711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1200811711 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.2600113418
Short name	T554
Test name
Test status
Simulation time	14969902037 ps
CPU time	9.67 seconds
Started	Dec 24 12:48:11 PM PST 23
Finished	Dec 24 12:48:23 PM PST 23
Peak memory	207384 kb
Host	smart-483c3b90-183f-4837-85ae-978718aa6562
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600113418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2600113418 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.4009497264
Short name	T762
Test name
Test status
Simulation time	128940008 ps
CPU time	1.34 seconds
Started	Dec 24 12:48:02 PM PST 23
Finished	Dec 24 12:48:05 PM PST 23
Peak memory	219996 kb
Host	smart-415c8914-2709-4e4b-a198-0df755e94e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009497264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.4009497264 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.1947972930
Short name	T198
Test name
Test status
Simulation time	178259258797 ps
CPU time	971.93 seconds
Started	Dec 24 12:48:01 PM PST 23
Finished	Dec 24 01:04:15 PM PST 23
Peak memory	301276 kb
Host	smart-bedd701a-63d7-4925-a0cb-13d067133559
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947972930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.1947972930 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.1328389695
Short name	T783
Test name
Test status
Simulation time	4197715366 ps
CPU time	78.88 seconds
Started	Dec 24 12:48:07 PM PST 23
Finished	Dec 24 12:49:30 PM PST 23
Peak memory	227284 kb
Host	smart-415006db-2794-4774-aef3-2e44a1a8b6ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1328389695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1328389695 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.363420701
Short name	T67
Test name
Test status
Simulation time	20011507267 ps
CPU time	63.15 seconds
Started	Dec 24 12:48:07 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	259808 kb
Host	smart-31e566f4-67f1-4409-b042-1e2dea72ae00
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363420701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.363420701 +enable_masking =0 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/1.kmac_sideload.1532366254
Short name	T631
Test name
Test status
Simulation time	5291311452 ps
CPU time	159.87 seconds
Started	Dec 24 12:48:05 PM PST 23
Finished	Dec 24 12:50:47 PM PST 23
Peak memory	235992 kb
Host	smart-72ffad80-7e25-4ce2-8a67-c2f6d1b62c7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532366254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1532366254 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.2865246399
Short name	T297
Test name
Test status
Simulation time	904719908 ps
CPU time	18.08 seconds
Started	Dec 24 12:48:03 PM PST 23
Finished	Dec 24 12:48:23 PM PST 23
Peak memory	220004 kb
Host	smart-8c359556-708b-4ce0-82f2-9b7337b175c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865246399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2865246399 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.674739674
Short name	T366
Test name
Test status
Simulation time	14825173351 ps
CPU time	331.28 seconds
Started	Dec 24 12:48:12 PM PST 23
Finished	Dec 24 12:53:45 PM PST 23
Peak memory	278936 kb
Host	smart-43210e86-8c19-4652-95c4-a07f3b050a88
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=674739674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.674739674 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.1564350145
Short name	T1090
Test name
Test status
Simulation time	1756842021 ps
CPU time	5.05 seconds
Started	Dec 24 12:48:06 PM PST 23
Finished	Dec 24 12:48:14 PM PST 23
Peak memory	215576 kb
Host	smart-4a95a793-c0da-4e55-94b8-746b25b9790f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564350145 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.kmac_test_vectors_kmac.1564350145 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2360490581
Short name	T359
Test name
Test status
Simulation time	1472194415 ps
CPU time	4.66 seconds
Started	Dec 24 12:48:08 PM PST 23
Finished	Dec 24 12:48:16 PM PST 23
Peak memory	215532 kb
Host	smart-e804e09b-9ac9-4748-8650-6e6d928ae882
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360490581 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2360490581 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.2945557882
Short name	T613
Test name
Test status
Simulation time	65686666928 ps
CPU time	1762.98 seconds
Started	Dec 24 12:48:07 PM PST 23
Finished	Dec 24 01:17:34 PM PST 23
Peak memory	374020 kb
Host	smart-60f5d060-e2de-4541-8b93-7f91b42848cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2945557882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2945557882 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.1025327461
Short name	T330
Test name
Test status
Simulation time	34986002687 ps
CPU time	1388.56 seconds
Started	Dec 24 12:48:06 PM PST 23
Finished	Dec 24 01:11:18 PM PST 23
Peak memory	368572 kb
Host	smart-df833fca-45f4-4961-b53e-62cd1e19d3b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1025327461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1025327461 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.3375916204
Short name	T710
Test name
Test status
Simulation time	552488331691 ps
CPU time	1303.63 seconds
Started	Dec 24 12:48:16 PM PST 23
Finished	Dec 24 01:10:02 PM PST 23
Peak memory	334184 kb
Host	smart-edb3813b-adc8-4378-b95e-66275b58b234
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3375916204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3375916204 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.4018976003
Short name	T451
Test name
Test status
Simulation time	37969218671 ps
CPU time	777.29 seconds
Started	Dec 24 12:48:09 PM PST 23
Finished	Dec 24 01:01:10 PM PST 23
Peak memory	293992 kb
Host	smart-79ecf1ae-33c0-427d-ac0c-181c46b5ec01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4018976003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4018976003 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.3874022668
Short name	T863
Test name
Test status
Simulation time	752625747483 ps
CPU time	4868.32 seconds
Started	Dec 24 12:48:02 PM PST 23
Finished	Dec 24 02:09:13 PM PST 23
Peak memory	656644 kb
Host	smart-cae45028-0e73-46c7-84f2-79e68c270c58
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3874022668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3874022668 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.2453751391
Short name	T773
Test name
Test status
Simulation time	44656941289 ps
CPU time	3444.48 seconds
Started	Dec 24 12:48:02 PM PST 23
Finished	Dec 24 01:45:29 PM PST 23
Peak memory	553488 kb
Host	smart-afd8be03-66ef-4f95-8556-0ef72d7ab377
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2453751391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2453751391 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.420876559
Short name	T682
Test name
Test status
Simulation time	117699648 ps
CPU time	0.83 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:49:04 PM PST 23
Peak memory	205200 kb
Host	smart-0395ba5f-dc6b-41fd-bbc7-b7f2897bfb81
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420876559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.420876559 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_app.132595576
Short name	T629
Test name
Test status
Simulation time	18336288769 ps
CPU time	313.99 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 12:54:18 PM PST 23
Peak memory	247236 kb
Host	smart-04d31f68-6372-4007-8677-5e628831847e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132595576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.132595576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.3426308859
Short name	T1019
Test name
Test status
Simulation time	18635320643 ps
CPU time	425.66 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:56:16 PM PST 23
Peak memory	228376 kb
Host	smart-47ce3dbf-0fbe-47e1-9b9d-4bd664d67de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426308859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3426308859 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.2838768298
Short name	T238
Test name
Test status
Simulation time	1582354313 ps
CPU time	15.29 seconds
Started	Dec 24 12:49:04 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	223668 kb
Host	smart-281522f8-88c2-44a2-a0bc-f46297c8288a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2838768298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2838768298 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.3525985952
Short name	T869
Test name
Test status
Simulation time	5233470886 ps
CPU time	44.72 seconds
Started	Dec 24 12:49:06 PM PST 23
Finished	Dec 24 12:49:53 PM PST 23
Peak memory	223688 kb
Host	smart-eabdf181-0834-4cc1-b306-cedd6972b80c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3525985952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3525985952 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.2611698777
Short name	T1141
Test name
Test status
Simulation time	4269720776 ps
CPU time	118.63 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:51:02 PM PST 23
Peak memory	232224 kb
Host	smart-43f846d1-cb03-48d5-93ef-78d45b513729
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611698777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2611698777 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.1666926485
Short name	T320
Test name
Test status
Simulation time	494194777 ps
CPU time	34.72 seconds
Started	Dec 24 12:49:10 PM PST 23
Finished	Dec 24 12:49:47 PM PST 23
Peak memory	233676 kb
Host	smart-bdae6f5a-68f2-43ec-b6c5-1b602e4332e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666926485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1666926485 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.6736151
Short name	T1034
Test name
Test status
Simulation time	225457572 ps
CPU time	1.06 seconds
Started	Dec 24 12:49:06 PM PST 23
Finished	Dec 24 12:49:10 PM PST 23
Peak memory	206692 kb
Host	smart-e88ec51d-5ebd-4543-95a6-3b90accbc1f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6736151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.6736151 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.2365568172
Short name	T903
Test name
Test status
Simulation time	69920461 ps
CPU time	1.17 seconds
Started	Dec 24 12:49:03 PM PST 23
Finished	Dec 24 12:49:07 PM PST 23
Peak memory	215636 kb
Host	smart-3d5f5a60-9319-4bf0-adcc-db1e0be411bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365568172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2365568172 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.73221904
Short name	T850
Test name
Test status
Simulation time	9851258760 ps
CPU time	223.6 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 12:52:49 PM PST 23
Peak memory	240296 kb
Host	smart-f66f47aa-171b-4b8f-a195-be5e4201647e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73221904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and _output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and _output.73221904 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.2603264421
Short name	T206
Test name
Test status
Simulation time	58489083598 ps
CPU time	389.87 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 12:55:31 PM PST 23
Peak memory	250824 kb
Host	smart-f03c905d-c4f8-44ee-a7c3-4d5a0af98b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603264421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2603264421 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.3244342351
Short name	T799
Test name
Test status
Simulation time	5978685637 ps
CPU time	19.61 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:30 PM PST 23
Peak memory	221168 kb
Host	smart-2411975f-27a0-428f-b793-8a0dbd990ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244342351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3244342351 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.1325095817
Short name	T1015
Test name
Test status
Simulation time	152826489719 ps
CPU time	296.04 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:54:07 PM PST 23
Peak memory	273240 kb
Host	smart-4a084afd-1b5b-4b97-98b9-2f810e5cbcb5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1325095817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1325095817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.2973718181
Short name	T839
Test name
Test status
Simulation time	679676959 ps
CPU time	4.91 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:49:16 PM PST 23
Peak memory	215584 kb
Host	smart-76ca0918-9cd0-4600-8169-d51afbb4fa0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973718181 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.2973718181 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1219450266
Short name	T244
Test name
Test status
Simulation time	68257780 ps
CPU time	4.63 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	215068 kb
Host	smart-15dddc80-d1ed-4be8-a3bc-0966b0a0b85c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219450266 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1219450266 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.4160814812
Short name	T215
Test name
Test status
Simulation time	38269684291 ps
CPU time	1556.2 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 01:14:57 PM PST 23
Peak memory	390080 kb
Host	smart-0c0e3df7-8696-497c-a82d-3b995ffbe517
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4160814812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.4160814812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.882393214
Short name	T224
Test name
Test status
Simulation time	94506819599 ps
CPU time	1861.71 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 01:20:06 PM PST 23
Peak memory	373676 kb
Host	smart-279ca182-503e-4b3b-8b66-9294c48c69a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=882393214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.882393214 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.481484613
Short name	T726
Test name
Test status
Simulation time	27683261043 ps
CPU time	1149.69 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 01:08:14 PM PST 23
Peak memory	332980 kb
Host	smart-0eaaecc2-2631-4e27-863c-066e509e2605
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=481484613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.481484613 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.2773780155
Short name	T797
Test name
Test status
Simulation time	9860576240 ps
CPU time	739.11 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 01:01:33 PM PST 23
Peak memory	291728 kb
Host	smart-22c5fbc3-d3df-456a-9a71-877eaa09caec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2773780155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.2773780155 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.3685082583
Short name	T231
Test name
Test status
Simulation time	50888487101 ps
CPU time	4090.87 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 01:57:13 PM PST 23
Peak memory	652232 kb
Host	smart-b462ab88-039b-4ab4-8c84-13550ca92cd8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3685082583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3685082583 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.2355944250
Short name	T1024
Test name
Test status
Simulation time	43778687923 ps
CPU time	3421.51 seconds
Started	Dec 24 12:48:48 PM PST 23
Finished	Dec 24 01:45:51 PM PST 23
Peak memory	570572 kb
Host	smart-6e481245-1913-4d0b-8a34-5597f6f74513
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2355944250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2355944250 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_app.1362850817
Short name	T247
Test name
Test status
Simulation time	3605742472 ps
CPU time	74.99 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 12:50:34 PM PST 23
Peak memory	226004 kb
Host	smart-d91c2013-71db-4e5f-b864-4353c217335f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362850817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1362850817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.890227503
Short name	T163
Test name
Test status
Simulation time	14680682059 ps
CPU time	417.02 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 12:55:59 PM PST 23
Peak memory	228856 kb
Host	smart-5d6153d3-2853-45ff-8f47-602a58ff74ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890227503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.890227503 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.498980494
Short name	T866
Test name
Test status
Simulation time	694625997 ps
CPU time	6.32 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 12:49:29 PM PST 23
Peak memory	223436 kb
Host	smart-26edec1b-c77a-4cb3-b353-a4661771b035
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=498980494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.498980494 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.2575513207
Short name	T683
Test name
Test status
Simulation time	1613849417 ps
CPU time	17.58 seconds
Started	Dec 24 12:49:16 PM PST 23
Finished	Dec 24 12:49:35 PM PST 23
Peak memory	221368 kb
Host	smart-24ee7783-cd66-4c1a-b144-07f6c423de85
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2575513207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2575513207 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.3244414837
Short name	T583
Test name
Test status
Simulation time	32801186530 ps
CPU time	178.29 seconds
Started	Dec 24 12:49:09 PM PST 23
Finished	Dec 24 12:52:10 PM PST 23
Peak memory	236904 kb
Host	smart-94deb854-b56e-4084-86fc-01960d4c4835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244414837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3244414837 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.3197816687
Short name	T323
Test name
Test status
Simulation time	15869173991 ps
CPU time	312.32 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 12:54:37 PM PST 23
Peak memory	256664 kb
Host	smart-edbb1bbc-43b6-4af7-a51a-98d18da43a03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197816687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3197816687 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.1703659180
Short name	T36
Test name
Test status
Simulation time	6729355777 ps
CPU time	5.96 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 12:49:25 PM PST 23
Peak memory	207376 kb
Host	smart-f90fb586-a4b8-4483-8c64-7131f54c8714
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703659180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1703659180 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.3391802223
Short name	T433
Test name
Test status
Simulation time	107495206 ps
CPU time	1.35 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	216604 kb
Host	smart-49b6b01c-2366-46c6-91ce-c2f52691865f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391802223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3391802223 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.1914808834
Short name	T465
Test name
Test status
Simulation time	4486806540 ps
CPU time	113.4 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 12:51:14 PM PST 23
Peak memory	225588 kb
Host	smart-0646d765-114a-483a-8e5d-189528b490fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914808834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.1914808834 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.780577573
Short name	T375
Test name
Test status
Simulation time	24412271436 ps
CPU time	156.46 seconds
Started	Dec 24 12:49:16 PM PST 23
Finished	Dec 24 12:51:54 PM PST 23
Peak memory	234340 kb
Host	smart-ebb2559d-bb08-4e57-bfe5-f3b52e9c2680
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780577573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.780577573 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.1811842431
Short name	T582
Test name
Test status
Simulation time	5114538347 ps
CPU time	21.61 seconds
Started	Dec 24 12:49:04 PM PST 23
Finished	Dec 24 12:49:28 PM PST 23
Peak memory	223728 kb
Host	smart-154d6519-1d6c-41f0-95df-4491d835c84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811842431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1811842431 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.3772870432
Short name	T316
Test name
Test status
Simulation time	153301016673 ps
CPU time	1023.47 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 01:06:22 PM PST 23
Peak memory	338852 kb
Host	smart-71302a52-71da-49f7-90d7-538e46c0b65d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3772870432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3772870432 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.1377388903
Short name	T18
Test name
Test status
Simulation time	103322080 ps
CPU time	3.95 seconds
Started	Dec 24 12:49:23 PM PST 23
Finished	Dec 24 12:49:28 PM PST 23
Peak memory	215580 kb
Host	smart-469b3063-bcdd-41e4-b3b2-457d21c8600c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377388903 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.1377388903 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.51991188
Short name	T917
Test name
Test status
Simulation time	668569465 ps
CPU time	4.48 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 12:49:23 PM PST 23
Peak memory	215604 kb
Host	smart-0a0824b6-a47d-4a1c-bf8d-8d0af0bd30ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51991188 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.kmac_test_vectors_kmac_xof.51991188 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.4216114337
Short name	T932
Test name
Test status
Simulation time	18435201908 ps
CPU time	1524.33 seconds
Started	Dec 24 12:49:03 PM PST 23
Finished	Dec 24 01:14:30 PM PST 23
Peak memory	376716 kb
Host	smart-16a60d52-104f-4cd8-b04c-89f5c749e89c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4216114337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.4216114337 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.3393183421
Short name	T940
Test name
Test status
Simulation time	17915122442 ps
CPU time	1454.73 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 01:13:25 PM PST 23
Peak memory	373528 kb
Host	smart-f0bb45ea-2838-4daa-b79a-9f9e51d05d70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3393183421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3393183421 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.4125707953
Short name	T627
Test name
Test status
Simulation time	158838337115 ps
CPU time	1289.75 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 01:10:35 PM PST 23
Peak memory	332676 kb
Host	smart-060d9ff1-0629-4627-8799-7ff13cb71365
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4125707953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.4125707953 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.3583068527
Short name	T761
Test name
Test status
Simulation time	37607028534 ps
CPU time	813.19 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 01:02:38 PM PST 23
Peak memory	292436 kb
Host	smart-ae16b6a7-d425-40d6-8cfe-c1fca365bc34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3583068527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3583068527 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.1583518877
Short name	T598
Test name
Test status
Simulation time	194994171719 ps
CPU time	3951.27 seconds
Started	Dec 24 12:49:16 PM PST 23
Finished	Dec 24 01:55:10 PM PST 23
Peak memory	646892 kb
Host	smart-892aa24c-da07-4714-9aee-a28c4e1f8239
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1583518877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1583518877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.3694338337
Short name	T500
Test name
Test status
Simulation time	189595894217 ps
CPU time	3928.64 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 01:54:44 PM PST 23
Peak memory	550616 kb
Host	smart-fac7e144-66fd-401a-9a25-4d66061e3b19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3694338337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.3694338337 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.1521522431
Short name	T378
Test name
Test status
Simulation time	23488265 ps
CPU time	0.76 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 12:49:24 PM PST 23
Peak memory	205112 kb
Host	smart-7d227f68-51f5-4cf1-bdef-8852d25f6865
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521522431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1521522431 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.3428129673
Short name	T249
Test name
Test status
Simulation time	13705995828 ps
CPU time	93.95 seconds
Started	Dec 24 12:49:14 PM PST 23
Finished	Dec 24 12:50:50 PM PST 23
Peak memory	228224 kb
Host	smart-782a6180-8318-4b12-903f-93393973335c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428129673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3428129673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.561131711
Short name	T262
Test name
Test status
Simulation time	6879420269 ps
CPU time	542.88 seconds
Started	Dec 24 12:49:10 PM PST 23
Finished	Dec 24 12:58:15 PM PST 23
Peak memory	230440 kb
Host	smart-e46f248c-7cbe-4b76-b6e5-381aee536b74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561131711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.561131711 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.3102356739
Short name	T1144
Test name
Test status
Simulation time	589357025 ps
CPU time	12.21 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 12:49:29 PM PST 23
Peak memory	220416 kb
Host	smart-bf260330-e97e-4ad8-8263-c6362b996c75
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3102356739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3102356739 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.4220064942
Short name	T617
Test name
Test status
Simulation time	150763105 ps
CPU time	10.01 seconds
Started	Dec 24 12:49:25 PM PST 23
Finished	Dec 24 12:49:37 PM PST 23
Peak memory	223732 kb
Host	smart-c54e530e-40c4-4e6f-b22d-a73d07a3aa12
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4220064942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4220064942 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.3797925907
Short name	T512
Test name
Test status
Simulation time	55119202514 ps
CPU time	292.36 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 12:54:15 PM PST 23
Peak memory	243352 kb
Host	smart-0875cc78-5b8d-4ae0-b39b-7b54d19c598a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797925907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3797925907 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.2288993999
Short name	T418
Test name
Test status
Simulation time	34975869208 ps
CPU time	374.63 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 12:55:35 PM PST 23
Peak memory	256668 kb
Host	smart-b4e3411c-6877-4989-ba4b-9ea2502cda2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288993999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2288993999 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.1635633537
Short name	T791
Test name
Test status
Simulation time	80303909 ps
CPU time	1.34 seconds
Started	Dec 24 12:49:22 PM PST 23
Finished	Dec 24 12:49:25 PM PST 23
Peak memory	215644 kb
Host	smart-74218cf3-581d-4073-b096-e6f5f913e400
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635633537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1635633537 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.875623504
Short name	T636
Test name
Test status
Simulation time	119227342492 ps
CPU time	1047.55 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 01:06:50 PM PST 23
Peak memory	338804 kb
Host	smart-ed575152-8888-4c00-9512-cfee73f03759
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875623504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an d_output.875623504 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.301131207
Short name	T961
Test name
Test status
Simulation time	15357712089 ps
CPU time	78.56 seconds
Started	Dec 24 12:49:20 PM PST 23
Finished	Dec 24 12:50:40 PM PST 23
Peak memory	225244 kb
Host	smart-95c4d666-87ab-4be0-a511-6f6d8fa154ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301131207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.301131207 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.3699660872
Short name	T376
Test name
Test status
Simulation time	11985196865 ps
CPU time	38.83 seconds
Started	Dec 24 12:49:14 PM PST 23
Finished	Dec 24 12:49:55 PM PST 23
Peak memory	221580 kb
Host	smart-526bf70d-173b-42f1-9c58-e4bc1dc2860b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699660872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3699660872 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.3580048058
Short name	T76
Test name
Test status
Simulation time	58491190402 ps
CPU time	644.29 seconds
Started	Dec 24 12:49:22 PM PST 23
Finished	Dec 24 01:00:08 PM PST 23
Peak memory	313632 kb
Host	smart-22a4c7ef-f360-43eb-9874-06023cb55700
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3580048058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3580048058 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_stress_all_with_rand_reset.3865561856
Short name	T479
Test name
Test status
Simulation time	61918167438 ps
CPU time	825.94 seconds
Started	Dec 24 12:49:14 PM PST 23
Finished	Dec 24 01:03:02 PM PST 23
Peak memory	278032 kb
Host	smart-461a9e0e-4716-4e60-95d3-134aa9ad57c4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3865561856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.3865561856 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.1592959701
Short name	T308
Test name
Test status
Simulation time	351470151 ps
CPU time	4.51 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	215680 kb
Host	smart-3941d985-d9ac-49af-bcc2-51e69e4b07d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592959701 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.1592959701 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2845298839
Short name	T213
Test name
Test status
Simulation time	66853441 ps
CPU time	3.72 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	209060 kb
Host	smart-2918f70e-c368-4bd4-86f7-116b22dbc3a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845298839 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2845298839 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.2207148238
Short name	T688
Test name
Test status
Simulation time	268748530092 ps
CPU time	1818.94 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 01:19:38 PM PST 23
Peak memory	389504 kb
Host	smart-53bd4564-0bd5-41d5-8d4e-6cef17671e5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2207148238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2207148238 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.4198933847
Short name	T196
Test name
Test status
Simulation time	73536007296 ps
CPU time	1505.74 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 01:14:25 PM PST 23
Peak memory	372512 kb
Host	smart-617402c6-8814-4e0c-982f-14cf38d56d12
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4198933847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.4198933847 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.2327979754
Short name	T946
Test name
Test status
Simulation time	143129626934 ps
CPU time	1395.24 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 01:12:30 PM PST 23
Peak memory	333604 kb
Host	smart-f27e0b97-fd12-4737-bb7f-3c39fbca6ba7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2327979754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2327979754 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.1814819679
Short name	T993
Test name
Test status
Simulation time	40075042996 ps
CPU time	812.53 seconds
Started	Dec 24 12:49:19 PM PST 23
Finished	Dec 24 01:02:53 PM PST 23
Peak memory	296860 kb
Host	smart-93037dd8-48c0-40c0-9ad3-e63037b2ad81
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1814819679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1814819679 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.4121138119
Short name	T482
Test name
Test status
Simulation time	243622251393 ps
CPU time	4852.88 seconds
Started	Dec 24 12:49:20 PM PST 23
Finished	Dec 24 02:10:15 PM PST 23
Peak memory	656292 kb
Host	smart-ece67795-2d09-4286-9e83-21200cf5ee8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4121138119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.4121138119 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.1021780806
Short name	T715
Test name
Test status
Simulation time	546669696979 ps
CPU time	3621.31 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 01:49:40 PM PST 23
Peak memory	571064 kb
Host	smart-cb11569e-69af-4930-bf5b-005f854d41c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1021780806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1021780806 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.3615951572
Short name	T1117
Test name
Test status
Simulation time	73817434 ps
CPU time	0.77 seconds
Started	Dec 24 12:49:19 PM PST 23
Finished	Dec 24 12:49:22 PM PST 23
Peak memory	205104 kb
Host	smart-c4807647-d75e-428b-8cfc-fc62fbe6822a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615951572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3615951572 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.3635636770
Short name	T380
Test name
Test status
Simulation time	21773349125 ps
CPU time	292.85 seconds
Started	Dec 24 12:49:16 PM PST 23
Finished	Dec 24 12:54:11 PM PST 23
Peak memory	247128 kb
Host	smart-fdf4a119-a6a0-46f2-9fab-813c43b133a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635636770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3635636770 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.751288104
Short name	T1072
Test name
Test status
Simulation time	17522197479 ps
CPU time	490.95 seconds
Started	Dec 24 12:49:28 PM PST 23
Finished	Dec 24 12:57:40 PM PST 23
Peak memory	230204 kb
Host	smart-03882d25-ae46-4077-b198-c13a996a32a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751288104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.751288104 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.881790577
Short name	T1101
Test name
Test status
Simulation time	5660606620 ps
CPU time	36.83 seconds
Started	Dec 24 12:49:26 PM PST 23
Finished	Dec 24 12:50:04 PM PST 23
Peak memory	220048 kb
Host	smart-ab0e56c7-31bb-4e52-8e3a-f28b8e2d17ef
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=881790577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.881790577 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.3469457011
Short name	T802
Test name
Test status
Simulation time	2467357540 ps
CPU time	20.68 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 12:49:41 PM PST 23
Peak memory	223628 kb
Host	smart-94c31a21-1a8d-4708-a25e-85681e843c86
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3469457011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3469457011 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.837439205
Short name	T759
Test name
Test status
Simulation time	30590811616 ps
CPU time	264.21 seconds
Started	Dec 24 12:49:20 PM PST 23
Finished	Dec 24 12:53:46 PM PST 23
Peak memory	246076 kb
Host	smart-2916cd9e-7163-40f5-a1db-13b02e0ae915
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837439205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.837439205 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_key_error.1260647479
Short name	T934
Test name
Test status
Simulation time	1338677208 ps
CPU time	4.39 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 12:49:30 PM PST 23
Peak memory	207116 kb
Host	smart-ac51fe18-fd62-4031-8fea-93d09994d108
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260647479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1260647479 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.2921548963
Short name	T907
Test name
Test status
Simulation time	98783162 ps
CPU time	1.34 seconds
Started	Dec 24 12:49:31 PM PST 23
Finished	Dec 24 12:49:34 PM PST 23
Peak memory	215592 kb
Host	smart-f03494b4-c25d-437c-bb2a-fb9ca8b87b4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921548963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2921548963 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.3389050855
Short name	T1022
Test name
Test status
Simulation time	24025310088 ps
CPU time	1990.75 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 01:22:27 PM PST 23
Peak memory	443732 kb
Host	smart-1af073b6-063a-48e1-8688-e8fa28d50ba7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389050855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.3389050855 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.2361204727
Short name	T651
Test name
Test status
Simulation time	9689373090 ps
CPU time	236.97 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 12:53:13 PM PST 23
Peak memory	240692 kb
Host	smart-dedbef5d-c7f0-4691-aecb-aeadd598f11f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361204727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2361204727 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.3356673172
Short name	T303
Test name
Test status
Simulation time	4049538406 ps
CPU time	31.13 seconds
Started	Dec 24 12:49:23 PM PST 23
Finished	Dec 24 12:49:55 PM PST 23
Peak memory	222308 kb
Host	smart-1602b28d-2d9d-4820-a47e-1f1029e133fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356673172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3356673172 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all_with_rand_reset.3112955756
Short name	T758
Test name
Test status
Simulation time	29861830218 ps
CPU time	1303.99 seconds
Started	Dec 24 12:49:13 PM PST 23
Finished	Dec 24 01:10:59 PM PST 23
Peak memory	355324 kb
Host	smart-b91b4add-c8cb-4351-8c96-41e6d824bbbc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3112955756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.3112955756 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.108060081
Short name	T1138
Test name
Test status
Simulation time	121741534 ps
CPU time	3.81 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	215560 kb
Host	smart-124c84fb-5586-4278-a196-3dd9f43d8e29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108060081 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.kmac_test_vectors_kmac.108060081 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1107467557
Short name	T883
Test name
Test status
Simulation time	601654736 ps
CPU time	5.03 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 12:49:25 PM PST 23
Peak memory	215664 kb
Host	smart-3e153464-f109-482d-a5dd-afae27535368
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107467557 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1107467557 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.580165055
Short name	T1134
Test name
Test status
Simulation time	187897107912 ps
CPU time	1559.05 seconds
Started	Dec 24 12:49:17 PM PST 23
Finished	Dec 24 01:15:18 PM PST 23
Peak memory	391260 kb
Host	smart-8a91b210-d102-41b9-a2fe-e324435d94e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=580165055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.580165055 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.2660423995
Short name	T278
Test name
Test status
Simulation time	161987336944 ps
CPU time	1524.24 seconds
Started	Dec 24 12:49:32 PM PST 23
Finished	Dec 24 01:14:58 PM PST 23
Peak memory	376076 kb
Host	smart-026578a2-d4e1-4e49-8824-083a92eff67f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2660423995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2660423995 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.1567350810
Short name	T880
Test name
Test status
Simulation time	58983751442 ps
CPU time	1203.1 seconds
Started	Dec 24 12:49:26 PM PST 23
Finished	Dec 24 01:09:31 PM PST 23
Peak memory	345576 kb
Host	smart-7e481920-8cfb-437d-8577-fd738767596e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1567350810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.1567350810 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.2416700951
Short name	T1077
Test name
Test status
Simulation time	42710202153 ps
CPU time	933.22 seconds
Started	Dec 24 12:49:18 PM PST 23
Finished	Dec 24 01:04:53 PM PST 23
Peak memory	293892 kb
Host	smart-f02f50f5-2097-4a83-8523-7001d0793045
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2416700951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2416700951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.2558112555
Short name	T269
Test name
Test status
Simulation time	348028947842 ps
CPU time	4785.43 seconds
Started	Dec 24 12:49:15 PM PST 23
Finished	Dec 24 02:09:03 PM PST 23
Peak memory	642032 kb
Host	smart-812fa64f-5644-45c8-8cea-f8a3d0f8fbab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2558112555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2558112555 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.490271929
Short name	T357
Test name
Test status
Simulation time	13073082 ps
CPU time	0.77 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:49:59 PM PST 23
Peak memory	205188 kb
Host	smart-e1644ed2-b648-4fb6-9738-638014862851
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490271929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.490271929 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.1300612744
Short name	T775
Test name
Test status
Simulation time	3636748152 ps
CPU time	188.71 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 12:52:34 PM PST 23
Peak memory	238980 kb
Host	smart-0b281e57-790e-4743-bad8-0bcd60ae9e57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300612744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1300612744 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.3485962457
Short name	T385
Test name
Test status
Simulation time	9343363570 ps
CPU time	297.85 seconds
Started	Dec 24 12:49:25 PM PST 23
Finished	Dec 24 12:54:25 PM PST 23
Peak memory	227400 kb
Host	smart-7e8239d1-206a-4330-b69a-1b8c528f011f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485962457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3485962457 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.2264445594
Short name	T219
Test name
Test status
Simulation time	3148169078 ps
CPU time	19.29 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 12:49:45 PM PST 23
Peak memory	224000 kb
Host	smart-a7462e12-dc39-40e9-ab32-37e32ed3451f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2264445594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2264445594 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.2389642538
Short name	T403
Test name
Test status
Simulation time	4891121176 ps
CPU time	26.74 seconds
Started	Dec 24 12:49:26 PM PST 23
Finished	Dec 24 12:49:55 PM PST 23
Peak memory	223700 kb
Host	smart-53988465-2f57-4a25-ab6b-c2293f448a49
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2389642538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2389642538 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.3862879089
Short name	T513
Test name
Test status
Simulation time	7292984785 ps
CPU time	215.43 seconds
Started	Dec 24 12:49:23 PM PST 23
Finished	Dec 24 12:53:00 PM PST 23
Peak memory	241564 kb
Host	smart-03b8752a-fca0-4e23-8e25-68328dc17500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862879089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3862879089 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.601995964
Short name	T95
Test name
Test status
Simulation time	46649972669 ps
CPU time	330.85 seconds
Started	Dec 24 12:49:26 PM PST 23
Finished	Dec 24 12:54:59 PM PST 23
Peak memory	248536 kb
Host	smart-c3040fc5-bc2b-43f4-a1a6-6e942d332cce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601995964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.601995964 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.1575960597
Short name	T65
Test name
Test status
Simulation time	1341250150 ps
CPU time	2.44 seconds
Started	Dec 24 12:49:34 PM PST 23
Finished	Dec 24 12:49:38 PM PST 23
Peak memory	207072 kb
Host	smart-28e86fc0-b065-4de4-a8ed-09ae37313fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575960597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1575960597 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.3697030033
Short name	T558
Test name
Test status
Simulation time	504218787395 ps
CPU time	1811.33 seconds
Started	Dec 24 12:49:27 PM PST 23
Finished	Dec 24 01:19:40 PM PST 23
Peak memory	399184 kb
Host	smart-76508e2e-dc7d-48a0-a0e0-e62c1bd480d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697030033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.3697030033 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.475644934
Short name	T469
Test name
Test status
Simulation time	40783073466 ps
CPU time	188.73 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 12:52:34 PM PST 23
Peak memory	233440 kb
Host	smart-7474ad81-26c1-4640-85aa-9b6ff30dbd69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475644934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.475644934 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.2079944528
Short name	T811
Test name
Test status
Simulation time	30458139898 ps
CPU time	61.58 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 12:50:24 PM PST 23
Peak memory	215740 kb
Host	smart-d0192734-ffe3-4b47-b5a0-2bad640d1585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079944528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2079944528 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.1978935199
Short name	T519
Test name
Test status
Simulation time	459775556 ps
CPU time	4.78 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 12:50:12 PM PST 23
Peak memory	215736 kb
Host	smart-26ec99cc-5bdb-4d53-9969-46117b052594
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1978935199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1978935199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3778592250
Short name	T337
Test name
Test status
Simulation time	22502960864 ps
CPU time	469.04 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 12:57:40 PM PST 23
Peak memory	273372 kb
Host	smart-284a995a-7ed2-4205-9d73-44b6160e915c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3778592250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3778592250 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.38567720
Short name	T1040
Test name
Test status
Simulation time	233340705 ps
CPU time	4.16 seconds
Started	Dec 24 12:49:25 PM PST 23
Finished	Dec 24 12:49:31 PM PST 23
Peak memory	215692 kb
Host	smart-f5ac27d4-39fb-4d27-b1fa-11e8cb87a4d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567720 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.kmac_test_vectors_kmac.38567720 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.4201189199
Short name	T449
Test name
Test status
Simulation time	79246063 ps
CPU time	4.36 seconds
Started	Dec 24 12:49:42 PM PST 23
Finished	Dec 24 12:49:48 PM PST 23
Peak memory	209116 kb
Host	smart-eb0de17d-57a2-4dbb-a0b0-d16b0c8c9156
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201189199 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.4201189199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.941326706
Short name	T800
Test name
Test status
Simulation time	38457551245 ps
CPU time	1586.48 seconds
Started	Dec 24 12:49:20 PM PST 23
Finished	Dec 24 01:15:49 PM PST 23
Peak memory	391796 kb
Host	smart-bce53933-cb88-4aa5-927e-c0fc9568593e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=941326706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.941326706 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.923247050
Short name	T765
Test name
Test status
Simulation time	74700839822 ps
CPU time	1518.29 seconds
Started	Dec 24 12:49:25 PM PST 23
Finished	Dec 24 01:14:46 PM PST 23
Peak memory	377876 kb
Host	smart-6ee9ff2b-a0bc-4d3c-81b2-349ab5751b01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=923247050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.923247050 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.3085308638
Short name	T422
Test name
Test status
Simulation time	14348235218 ps
CPU time	1094.28 seconds
Started	Dec 24 12:49:21 PM PST 23
Finished	Dec 24 01:07:37 PM PST 23
Peak memory	340152 kb
Host	smart-2bff2b2a-d913-4461-b775-1bbd24b8acce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3085308638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3085308638 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.913321627
Short name	T461
Test name
Test status
Simulation time	9690372468 ps
CPU time	775.53 seconds
Started	Dec 24 12:49:24 PM PST 23
Finished	Dec 24 01:02:22 PM PST 23
Peak memory	292304 kb
Host	smart-68113686-ba67-448e-a824-ad8351b64487
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=913321627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.913321627 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.2087284759
Short name	T1030
Test name
Test status
Simulation time	115441314414 ps
CPU time	4119.86 seconds
Started	Dec 24 12:49:25 PM PST 23
Finished	Dec 24 01:58:07 PM PST 23
Peak memory	647760 kb
Host	smart-ea5eb518-8b0b-4adf-a28b-635c86faf1be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2087284759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2087284759 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.665968723
Short name	T628
Test name
Test status
Simulation time	585122025882 ps
CPU time	4113.36 seconds
Started	Dec 24 12:49:28 PM PST 23
Finished	Dec 24 01:58:03 PM PST 23
Peak memory	566644 kb
Host	smart-36981211-f839-416d-9264-0cbc56c0b8a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=665968723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.665968723 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.770630607
Short name	T573
Test name
Test status
Simulation time	18720054 ps
CPU time	0.81 seconds
Started	Dec 24 12:49:41 PM PST 23
Finished	Dec 24 12:49:43 PM PST 23
Peak memory	205188 kb
Host	smart-6da8746e-f560-4d48-b311-c810687d9d29
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770630607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.770630607 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.2062591022
Short name	T453
Test name
Test status
Simulation time	5152001217 ps
CPU time	58.13 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:50:53 PM PST 23
Peak memory	225548 kb
Host	smart-a539a83e-1dc7-4beb-9e4a-528517129617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062591022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2062591022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.4220981070
Short name	T771
Test name
Test status
Simulation time	52518181269 ps
CPU time	719.74 seconds
Started	Dec 24 12:49:51 PM PST 23
Finished	Dec 24 01:02:01 PM PST 23
Peak memory	232020 kb
Host	smart-3b04e06d-9e55-4fb2-bf2e-5735a482018a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220981070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.4220981070 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.2420749686
Short name	T361
Test name
Test status
Simulation time	47138394 ps
CPU time	3.75 seconds
Started	Dec 24 12:49:45 PM PST 23
Finished	Dec 24 12:49:51 PM PST 23
Peak memory	215496 kb
Host	smart-a87a17d7-028e-45cf-9a01-a9eb1f66bbfa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2420749686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2420749686 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.1787547718
Short name	T349
Test name
Test status
Simulation time	4354724134 ps
CPU time	30.54 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 12:50:22 PM PST 23
Peak memory	220276 kb
Host	smart-ab937e95-e328-4104-9eaa-c12781990b2a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1787547718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1787547718 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.1537730272
Short name	T150
Test name
Test status
Simulation time	10222085378 ps
CPU time	156.81 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:52:35 PM PST 23
Peak memory	234108 kb
Host	smart-f10901d9-58a4-4a88-a9aa-dfa3946894b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537730272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1537730272 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.2527229480
Short name	T746
Test name
Test status
Simulation time	18588058538 ps
CPU time	384.5 seconds
Started	Dec 24 12:49:45 PM PST 23
Finished	Dec 24 12:56:11 PM PST 23
Peak memory	256688 kb
Host	smart-b6ef51d1-8d62-42c0-b437-d69ce60ee075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527229480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2527229480 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.1989351143
Short name	T926
Test name
Test status
Simulation time	3361113629 ps
CPU time	4.68 seconds
Started	Dec 24 12:50:21 PM PST 23
Finished	Dec 24 12:50:28 PM PST 23
Peak memory	207288 kb
Host	smart-acee589b-8c5c-455e-b7bd-2950806affad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989351143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1989351143 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.3054454203
Short name	T668
Test name
Test status
Simulation time	59269237 ps
CPU time	1.13 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:49:53 PM PST 23
Peak memory	215692 kb
Host	smart-3e2e71fc-7ba2-45a0-a420-ef975223ed9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054454203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3054454203 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.891027220
Short name	T555
Test name
Test status
Simulation time	137874144012 ps
CPU time	2098.88 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 01:24:54 PM PST 23
Peak memory	420684 kb
Host	smart-a8dc18d6-7db1-4c80-8370-2e2a60054c72
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891027220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an d_output.891027220 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.196169467
Short name	T410
Test name
Test status
Simulation time	13806161688 ps
CPU time	224.5 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:53:48 PM PST 23
Peak memory	235668 kb
Host	smart-0e19c43d-c730-46ea-88ff-ebbe5801b859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196169467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.196169467 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.1241614708
Short name	T533
Test name
Test status
Simulation time	1927860270 ps
CPU time	25.32 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:50:24 PM PST 23
Peak memory	221572 kb
Host	smart-5533063f-5cec-4ba8-a5e5-dafa2572a8ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1241614708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1241614708 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.2225010163
Short name	T829
Test name
Test status
Simulation time	5820545925 ps
CPU time	370.51 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:56:09 PM PST 23
Peak memory	296284 kb
Host	smart-9d59fe7f-a6ca-4009-a11e-0f391259e5ec
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2225010163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2225010163 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.2284455652
Short name	T660
Test name
Test status
Simulation time	107613210092 ps
CPU time	1038.89 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:07:23 PM PST 23
Peak memory	316740 kb
Host	smart-51a8d742-fe2d-4c33-a804-53883fd8f08f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2284455652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.2284455652 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.1212760133
Short name	T1085
Test name
Test status
Simulation time	1052233494 ps
CPU time	4.62 seconds
Started	Dec 24 12:49:42 PM PST 23
Finished	Dec 24 12:49:47 PM PST 23
Peak memory	215596 kb
Host	smart-a3f9b98f-fd52-4e65-bdf3-cad5b1008c9c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212760133 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.1212760133 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3103704999
Short name	T878
Test name
Test status
Simulation time	1064268215 ps
CPU time	5.58 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	215576 kb
Host	smart-4e554c58-6004-4cb2-8b05-19677ba2e0f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103704999 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3103704999 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.1954774484
Short name	T844
Test name
Test status
Simulation time	341343480319 ps
CPU time	1894.76 seconds
Started	Dec 24 12:49:44 PM PST 23
Finished	Dec 24 01:21:21 PM PST 23
Peak memory	391876 kb
Host	smart-0758a3f1-3b1f-44c9-b548-1034522dcec6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1954774484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1954774484 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.640520194
Short name	T502
Test name
Test status
Simulation time	75396050243 ps
CPU time	1499.89 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 01:14:51 PM PST 23
Peak memory	388596 kb
Host	smart-56d37f50-f13b-4f11-a9b4-13530a644f9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=640520194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.640520194 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.3733934225
Short name	T1119
Test name
Test status
Simulation time	53861461312 ps
CPU time	1143.72 seconds
Started	Dec 24 12:49:55 PM PST 23
Finished	Dec 24 01:09:08 PM PST 23
Peak memory	331584 kb
Host	smart-ebc2d166-0dee-451f-a13f-c75844bc9522
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3733934225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.3733934225 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.3997399911
Short name	T427
Test name
Test status
Simulation time	195300111466 ps
CPU time	997.89 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:06:28 PM PST 23
Peak memory	294832 kb
Host	smart-cbf0a39d-4f12-4486-b8cd-b1f9a8474fc2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3997399911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.3997399911 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.1063956761
Short name	T1091
Test name
Test status
Simulation time	106406183688 ps
CPU time	3942.66 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:55:47 PM PST 23
Peak memory	655352 kb
Host	smart-97fff59d-1161-490b-b0e2-d4838ee02dfe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1063956761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1063956761 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.2299802815
Short name	T233
Test name
Test status
Simulation time	43332897112 ps
CPU time	3277.29 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:44:29 PM PST 23
Peak memory	553100 kb
Host	smart-bd3cfb59-ec1d-4496-bdc0-2872a3429116
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2299802815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2299802815 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.1104491996
Short name	T255
Test name
Test status
Simulation time	43517463 ps
CPU time	0.77 seconds
Started	Dec 24 12:49:44 PM PST 23
Finished	Dec 24 12:49:46 PM PST 23
Peak memory	205212 kb
Host	smart-e3aacd38-99a0-4af2-ba0a-8c07f93b4ce6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104491996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1104491996 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.2043661139
Short name	T501
Test name
Test status
Simulation time	35169964072 ps
CPU time	221.44 seconds
Started	Dec 24 12:49:43 PM PST 23
Finished	Dec 24 12:53:26 PM PST 23
Peak memory	240360 kb
Host	smart-29bf1337-443e-4c93-b00f-43d9b71b129a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043661139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2043661139 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.950112763
Short name	T694
Test name
Test status
Simulation time	36692315943 ps
CPU time	295.36 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 12:54:45 PM PST 23
Peak memory	226516 kb
Host	smart-4facb097-9f8f-4d9c-a7ee-db69b2787126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950112763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.950112763 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.464111737
Short name	T524
Test name
Test status
Simulation time	1954170419 ps
CPU time	37.78 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 12:50:47 PM PST 23
Peak memory	223684 kb
Host	smart-216e3062-1925-45cf-989b-acff73459f08
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=464111737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.464111737 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.2404541618
Short name	T572
Test name
Test status
Simulation time	6163497718 ps
CPU time	32.53 seconds
Started	Dec 24 12:49:37 PM PST 23
Finished	Dec 24 12:50:11 PM PST 23
Peak memory	223656 kb
Host	smart-5265b1e7-5629-438d-887c-7704cf2d9b1c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2404541618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2404541618 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.924610982
Short name	T729
Test name
Test status
Simulation time	9984104438 ps
CPU time	31.94 seconds
Started	Dec 24 12:49:55 PM PST 23
Finished	Dec 24 12:50:36 PM PST 23
Peak memory	221148 kb
Host	smart-f98bdc7c-3012-47fd-b5cb-9b535dd1ded9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924610982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.924610982 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.2395074474
Short name	T755
Test name
Test status
Simulation time	3886374692 ps
CPU time	286.67 seconds
Started	Dec 24 12:49:49 PM PST 23
Finished	Dec 24 12:54:44 PM PST 23
Peak memory	256612 kb
Host	smart-7a08dfa7-289d-4c6f-82b3-6b3b0bab005a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395074474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2395074474 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.3783584681
Short name	T478
Test name
Test status
Simulation time	17163951008 ps
CPU time	10.69 seconds
Started	Dec 24 12:49:40 PM PST 23
Finished	Dec 24 12:49:52 PM PST 23
Peak memory	207352 kb
Host	smart-ae53198e-b1bc-43eb-8d50-be5925402b1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783584681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3783584681 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.2961606815
Short name	T788
Test name
Test status
Simulation time	28030201 ps
CPU time	1.25 seconds
Started	Dec 24 12:49:42 PM PST 23
Finished	Dec 24 12:49:45 PM PST 23
Peak memory	217360 kb
Host	smart-172fe976-1784-4e6c-a692-9b4716f8b9de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961606815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2961606815 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.1289079576
Short name	T792
Test name
Test status
Simulation time	32111107139 ps
CPU time	348.92 seconds
Started	Dec 24 12:49:45 PM PST 23
Finished	Dec 24 12:55:36 PM PST 23
Peak memory	257616 kb
Host	smart-4c431dc5-3c55-4d2e-a0c7-892c703dc92e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289079576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.1289079576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.1647140435
Short name	T266
Test name
Test status
Simulation time	19262072172 ps
CPU time	86.8 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:51:18 PM PST 23
Peak memory	233764 kb
Host	smart-73d977f9-d29a-4bef-9071-086dea54b239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647140435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1647140435 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.4128105379
Short name	T718
Test name
Test status
Simulation time	6805428258 ps
CPU time	37.65 seconds
Started	Dec 24 12:49:45 PM PST 23
Finished	Dec 24 12:50:25 PM PST 23
Peak memory	215752 kb
Host	smart-bd2dcefe-f707-4cc4-b2bf-03d9fb2f417e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128105379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.4128105379 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.3955935506
Short name	T287
Test name
Test status
Simulation time	5914035851 ps
CPU time	153.34 seconds
Started	Dec 24 12:49:49 PM PST 23
Finished	Dec 24 12:52:29 PM PST 23
Peak memory	255396 kb
Host	smart-2907d3eb-ecef-4f00-8f03-28f1f8aa7b56
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3955935506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3955935506 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.229852368
Short name	T75
Test name
Test status
Simulation time	448270344 ps
CPU time	3.8 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	215676 kb
Host	smart-19fbcf95-60fc-443d-aefe-919342a2f9fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229852368 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.kmac_test_vectors_kmac.229852368 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2242039269
Short name	T1071
Test name
Test status
Simulation time	62937716 ps
CPU time	4.01 seconds
Started	Dec 24 12:50:07 PM PST 23
Finished	Dec 24 12:50:19 PM PST 23
Peak memory	215656 kb
Host	smart-9757e8e6-6b01-4ecf-9f83-9524af0bfdb5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242039269 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2242039269 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.2678026689
Short name	T510
Test name
Test status
Simulation time	581853355706 ps
CPU time	1864.96 seconds
Started	Dec 24 12:49:51 PM PST 23
Finished	Dec 24 01:21:05 PM PST 23
Peak memory	379052 kb
Host	smart-fb8d17f1-0e1d-49ec-a123-0389f0cf0f5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2678026689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2678026689 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.1062444445
Short name	T1050
Test name
Test status
Simulation time	185772831888 ps
CPU time	1763.56 seconds
Started	Dec 24 12:49:43 PM PST 23
Finished	Dec 24 01:19:08 PM PST 23
Peak memory	365168 kb
Host	smart-9a4bcc24-baa7-4ef0-ba6d-34c55463f5dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1062444445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1062444445 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.715782162
Short name	T625
Test name
Test status
Simulation time	471339191781 ps
CPU time	1340.38 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 01:12:10 PM PST 23
Peak memory	335968 kb
Host	smart-3a2a89a8-c2a9-48e1-8677-f9ddd7492295
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=715782162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.715782162 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.2464869214
Short name	T841
Test name
Test status
Simulation time	42526113388 ps
CPU time	883.52 seconds
Started	Dec 24 12:50:07 PM PST 23
Finished	Dec 24 01:04:59 PM PST 23
Peak memory	293380 kb
Host	smart-0f1667b4-c868-4b76-8678-fac97a319a5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2464869214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.2464869214 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.3074595781
Short name	T222
Test name
Test status
Simulation time	78347582413 ps
CPU time	3810.43 seconds
Started	Dec 24 12:49:42 PM PST 23
Finished	Dec 24 01:53:14 PM PST 23
Peak memory	634604 kb
Host	smart-b5306009-ea04-45cb-a901-81193de0114c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3074595781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.3074595781 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.4260506898
Short name	T526
Test name
Test status
Simulation time	44463867692 ps
CPU time	3536.64 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:48:48 PM PST 23
Peak memory	567144 kb
Host	smart-fa6573f4-d465-4f65-ac61-d5f6e81f176f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4260506898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.4260506898 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.1875578248
Short name	T241
Test name
Test status
Simulation time	59308271 ps
CPU time	0.78 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 12:50:12 PM PST 23
Peak memory	205196 kb
Host	smart-675e4c5b-d715-4c2e-8421-cb43d287833d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875578248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1875578248 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.1218061319
Short name	T494
Test name
Test status
Simulation time	41623446474 ps
CPU time	140.17 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:52:24 PM PST 23
Peak memory	234940 kb
Host	smart-d429ba89-e886-4df8-a274-fa36786d1b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218061319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1218061319 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.1347616303
Short name	T351
Test name
Test status
Simulation time	3302892957 ps
CPU time	99.08 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:51:37 PM PST 23
Peak memory	221752 kb
Host	smart-61526321-5068-400d-be11-5377bbc8bcdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347616303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1347616303 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.22525735
Short name	T921
Test name
Test status
Simulation time	984989460 ps
CPU time	21.14 seconds
Started	Dec 24 12:50:00 PM PST 23
Finished	Dec 24 12:50:33 PM PST 23
Peak memory	218612 kb
Host	smart-26929264-e61c-475a-bf59-fbabb79c6683
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=22525735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.22525735 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.1109823539
Short name	T937
Test name
Test status
Simulation time	1930340436 ps
CPU time	34.8 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:50:39 PM PST 23
Peak memory	223656 kb
Host	smart-765ec276-08af-46c4-8761-48605e42290e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1109823539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1109823539 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.509053716
Short name	T712
Test name
Test status
Simulation time	433226502 ps
CPU time	5.75 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:50:01 PM PST 23
Peak memory	216716 kb
Host	smart-cd561ba8-a853-45db-9015-92df155d35d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509053716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.509053716 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.2468934155
Short name	T593
Test name
Test status
Simulation time	1160196113 ps
CPU time	77.86 seconds
Started	Dec 24 12:49:49 PM PST 23
Finished	Dec 24 12:51:15 PM PST 23
Peak memory	240160 kb
Host	smart-0eac9eca-6769-49e6-88b4-e8ebd753c1b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468934155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2468934155 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.1878307851
Short name	T21
Test name
Test status
Simulation time	1257892219 ps
CPU time	2.19 seconds
Started	Dec 24 12:49:58 PM PST 23
Finished	Dec 24 12:50:12 PM PST 23
Peak memory	207352 kb
Host	smart-b0199741-42ae-43ec-8dbf-f023e791f097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878307851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1878307851 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.3048765286
Short name	T928
Test name
Test status
Simulation time	60242849 ps
CPU time	1.09 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:50:05 PM PST 23
Peak memory	215644 kb
Host	smart-db9cd871-b849-4234-9b7f-b5f85e1a2b6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048765286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3048765286 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.832536104
Short name	T534
Test name
Test status
Simulation time	45958489327 ps
CPU time	482.81 seconds
Started	Dec 24 12:50:01 PM PST 23
Finished	Dec 24 12:58:16 PM PST 23
Peak memory	264948 kb
Host	smart-8d32422a-2b13-4fa7-8e47-ce7d186fd1f4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832536104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an d_output.832536104 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.3097167821
Short name	T1001
Test name
Test status
Simulation time	1524132604 ps
CPU time	112.52 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 12:51:43 PM PST 23
Peak memory	229172 kb
Host	smart-445632e9-8ee4-48c2-90b0-62931dd3f2d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097167821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3097167821 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.995790717
Short name	T709
Test name
Test status
Simulation time	2921222989 ps
CPU time	21.96 seconds
Started	Dec 24 12:50:09 PM PST 23
Finished	Dec 24 12:50:38 PM PST 23
Peak memory	221508 kb
Host	smart-cba73e97-d29b-43d5-94c0-c4eaee0b4109
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995790717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.995790717 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.2305262835
Short name	T825
Test name
Test status
Simulation time	843726188 ps
CPU time	21.02 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 12:50:30 PM PST 23
Peak memory	224020 kb
Host	smart-d3ecebef-d465-4d36-8872-003ff2dd0eb5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2305262835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2305262835 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_stress_all_with_rand_reset.2727274559
Short name	T39
Test name
Test status
Simulation time	22777078586 ps
CPU time	380.2 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:56:19 PM PST 23
Peak memory	257076 kb
Host	smart-c78d3004-7da6-4c33-b5b2-fe1108c4ba3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2727274559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.2727274559 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.3618509928
Short name	T1036
Test name
Test status
Simulation time	1158581577 ps
CPU time	4.22 seconds
Started	Dec 24 12:50:16 PM PST 23
Finished	Dec 24 12:50:25 PM PST 23
Peak memory	215672 kb
Host	smart-ad2bcf4a-5d1f-4995-8e2c-90f20443c6d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618509928 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.3618509928 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1996259882
Short name	T70
Test name
Test status
Simulation time	289872612 ps
CPU time	3.8 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	215692 kb
Host	smart-4ab02085-d08a-4630-b56e-3057db4929b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996259882 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1996259882 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.3010681391
Short name	T197
Test name
Test status
Simulation time	18589375911 ps
CPU time	1456.81 seconds
Started	Dec 24 12:49:49 PM PST 23
Finished	Dec 24 01:14:13 PM PST 23
Peak memory	371584 kb
Host	smart-2b7fd8a8-cb9c-4381-b598-793964d20aa5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3010681391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3010681391 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.4214320519
Short name	T1007
Test name
Test status
Simulation time	393957565946 ps
CPU time	1826.42 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:20:17 PM PST 23
Peak memory	369908 kb
Host	smart-90a13b2d-9fa9-44a4-9ba1-8ebb1001af56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4214320519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.4214320519 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.2069108183
Short name	T437
Test name
Test status
Simulation time	72751357791 ps
CPU time	1344.58 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:12:27 PM PST 23
Peak memory	333160 kb
Host	smart-79965554-20bc-4baa-910b-9bc8966f9531
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2069108183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2069108183 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.579972036
Short name	T867
Test name
Test status
Simulation time	531931896392 ps
CPU time	5114.86 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 02:15:19 PM PST 23
Peak memory	644804 kb
Host	smart-115b4250-d8b3-4cb4-b93f-f58f341da22e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=579972036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.579972036 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.4067729950
Short name	T748
Test name
Test status
Simulation time	423984029671 ps
CPU time	3981.01 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:56:25 PM PST 23
Peak memory	554328 kb
Host	smart-4076b084-9e0d-4a2d-9dc0-024cc247168f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4067729950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.4067729950 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.1958704072
Short name	T306
Test name
Test status
Simulation time	16877382 ps
CPU time	0.75 seconds
Started	Dec 24 12:49:45 PM PST 23
Finished	Dec 24 12:49:48 PM PST 23
Peak memory	205208 kb
Host	smart-c557510d-66c6-4547-aa3c-75840c23ccda
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958704072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1958704072 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.2363633797
Short name	T149
Test name
Test status
Simulation time	9029924274 ps
CPU time	158.22 seconds
Started	Dec 24 12:49:48 PM PST 23
Finished	Dec 24 12:52:30 PM PST 23
Peak memory	234660 kb
Host	smart-8380f740-114c-4923-be9e-e29c20ab31b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363633797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2363633797 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.2869263450
Short name	T816
Test name
Test status
Simulation time	26448504390 ps
CPU time	801.58 seconds
Started	Dec 24 12:49:56 PM PST 23
Finished	Dec 24 01:03:28 PM PST 23
Peak memory	232512 kb
Host	smart-31056a9c-934c-4b08-938a-02e8d5ff65b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869263450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2869263450 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.4184711460
Short name	T967
Test name
Test status
Simulation time	6440184683 ps
CPU time	48.33 seconds
Started	Dec 24 12:50:02 PM PST 23
Finished	Dec 24 12:51:02 PM PST 23
Peak memory	223180 kb
Host	smart-835b16b4-b0aa-45a2-ae09-42511bd86289
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4184711460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4184711460 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.2295582587
Short name	T1105
Test name
Test status
Simulation time	437437390 ps
CPU time	30.27 seconds
Started	Dec 24 12:50:06 PM PST 23
Finished	Dec 24 12:50:45 PM PST 23
Peak memory	223756 kb
Host	smart-28982a6f-f0d7-474f-bc8b-b000ef305b57
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2295582587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2295582587 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.2422969335
Short name	T858
Test name
Test status
Simulation time	85347246663 ps
CPU time	293.55 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 12:54:57 PM PST 23
Peak memory	241388 kb
Host	smart-dd35fc3b-1b6d-4ef9-8844-bca77c86790f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422969335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2422969335 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_error.3785796299
Short name	T1012
Test name
Test status
Simulation time	22525630879 ps
CPU time	334.46 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 12:55:24 PM PST 23
Peak memory	256740 kb
Host	smart-467f4edf-d6ca-4100-b046-de82b9473e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785796299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3785796299 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.745601075
Short name	T585
Test name
Test status
Simulation time	79387643 ps
CPU time	1.25 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:50:01 PM PST 23
Peak memory	216552 kb
Host	smart-2b6a48f4-a6b2-4177-83b7-4947bfe51dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745601075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.745601075 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.1250919794
Short name	T240
Test name
Test status
Simulation time	595115763264 ps
CPU time	2906.49 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 01:38:33 PM PST 23
Peak memory	465864 kb
Host	smart-d25f74bc-4104-4f89-b17c-283a8d47fd95
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250919794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.1250919794 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.2401927454
Short name	T749
Test name
Test status
Simulation time	4321821787 ps
CPU time	84.05 seconds
Started	Dec 24 12:50:08 PM PST 23
Finished	Dec 24 12:51:39 PM PST 23
Peak memory	225960 kb
Host	smart-fe1f44dd-3208-41ba-88fb-a1d95ec030b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401927454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2401927454 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.2941519933
Short name	T528
Test name
Test status
Simulation time	2231395032 ps
CPU time	45.79 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:50:50 PM PST 23
Peak memory	215648 kb
Host	smart-d3d1d787-6d64-4b63-9d69-def8bc8b0284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941519933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2941519933 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.338759683
Short name	T885
Test name
Test status
Simulation time	9305547933 ps
CPU time	49.94 seconds
Started	Dec 24 12:50:01 PM PST 23
Finished	Dec 24 12:51:03 PM PST 23
Peak memory	223912 kb
Host	smart-019393e0-ca86-45c3-8ac1-a3c44887344b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=338759683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.338759683 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_stress_all_with_rand_reset.479340370
Short name	T1108
Test name
Test status
Simulation time	149064266058 ps
CPU time	695.23 seconds
Started	Dec 24 12:50:07 PM PST 23
Finished	Dec 24 01:01:50 PM PST 23
Peak memory	260784 kb
Host	smart-fcb935e5-ae2c-4580-8bab-a171f47d09ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=479340370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.479340370 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.2589724003
Short name	T13
Test name
Test status
Simulation time	1046537438 ps
CPU time	4.19 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	215688 kb
Host	smart-5064eb90-9aa9-4c7d-9008-e6610fa2348f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589724003 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.2589724003 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.1610906052
Short name	T413
Test name
Test status
Simulation time	1316121993 ps
CPU time	4.53 seconds
Started	Dec 24 12:50:06 PM PST 23
Finished	Dec 24 12:50:20 PM PST 23
Peak memory	215636 kb
Host	smart-8007a00b-97c1-49db-938e-c5d2968f9fcb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610906052 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.1610906052 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.3450768759
Short name	T408
Test name
Test status
Simulation time	75968919957 ps
CPU time	1397.83 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 01:13:08 PM PST 23
Peak memory	372096 kb
Host	smart-58e21c79-842b-4bda-b21d-d758357ed64c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3450768759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3450768759 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.448167015
Short name	T553
Test name
Test status
Simulation time	200872171830 ps
CPU time	1869.08 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 01:21:13 PM PST 23
Peak memory	377008 kb
Host	smart-224a8237-dd06-49a6-af8f-b1803b351fd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=448167015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.448167015 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.3526700047
Short name	T679
Test name
Test status
Simulation time	14187759070 ps
CPU time	1138.61 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 01:09:03 PM PST 23
Peak memory	334000 kb
Host	smart-3df06601-9d5c-420d-8fdf-7418ee233b54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3526700047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3526700047 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.1603136754
Short name	T485
Test name
Test status
Simulation time	40345251183 ps
CPU time	829.21 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:03:53 PM PST 23
Peak memory	298696 kb
Host	smart-ef55cff7-5792-4514-993a-5faa3f6b1685
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1603136754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1603136754 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.1868900562
Short name	T391
Test name
Test status
Simulation time	206348546099 ps
CPU time	3803.8 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:53:15 PM PST 23
Peak memory	622564 kb
Host	smart-5cd10aaa-bfc2-4290-9cb8-0d0424f2e87b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1868900562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1868900562 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.1563159451
Short name	T411
Test name
Test status
Simulation time	160351960356 ps
CPU time	3381.38 seconds
Started	Dec 24 12:49:46 PM PST 23
Finished	Dec 24 01:46:11 PM PST 23
Peak memory	561748 kb
Host	smart-e319aa02-6e6b-4cf7-9494-79c2d62588d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1563159451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1563159451 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.3135381655
Short name	T486
Test name
Test status
Simulation time	55958704 ps
CPU time	0.81 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 12:50:12 PM PST 23
Peak memory	205140 kb
Host	smart-0d88a543-bf13-4d56-a071-34b134108be6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135381655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3135381655 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.2789381891
Short name	T692
Test name
Test status
Simulation time	2038225316 ps
CPU time	39.55 seconds
Started	Dec 24 12:49:58 PM PST 23
Finished	Dec 24 12:50:49 PM PST 23
Peak memory	223800 kb
Host	smart-68c7d6b2-0521-4c62-a53c-4a2254bd8b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789381891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2789381891 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.3880355392
Short name	T161
Test name
Test status
Simulation time	26097321882 ps
CPU time	361.99 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 12:56:08 PM PST 23
Peak memory	228576 kb
Host	smart-8f0f5a85-d6e0-4964-9d1f-5d55be8ceb51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880355392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3880355392 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.2301744949
Short name	T676
Test name
Test status
Simulation time	2086266712 ps
CPU time	38.12 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:50:42 PM PST 23
Peak memory	221356 kb
Host	smart-a58f54f7-939e-47b8-835f-c2339bbd0879
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2301744949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2301744949 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.3747364648
Short name	T342
Test name
Test status
Simulation time	1911865589 ps
CPU time	12.48 seconds
Started	Dec 24 12:50:02 PM PST 23
Finished	Dec 24 12:50:26 PM PST 23
Peak memory	218688 kb
Host	smart-706e1450-0734-493d-907d-45afc2016e26
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3747364648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3747364648 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.2923173439
Short name	T704
Test name
Test status
Simulation time	147197467 ps
CPU time	3.37 seconds
Started	Dec 24 12:50:03 PM PST 23
Finished	Dec 24 12:50:17 PM PST 23
Peak memory	216732 kb
Host	smart-5e86cc1e-3234-407e-942e-235789a0c9f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923173439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2923173439 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.2858676379
Short name	T853
Test name
Test status
Simulation time	85339917871 ps
CPU time	390.22 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:56:29 PM PST 23
Peak memory	256704 kb
Host	smart-213fb5e9-c7b2-4c20-aeba-2b4b1c0dc430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858676379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2858676379 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.2354675319
Short name	T1147
Test name
Test status
Simulation time	70327996 ps
CPU time	0.89 seconds
Started	Dec 24 12:49:50 PM PST 23
Finished	Dec 24 12:50:00 PM PST 23
Peak memory	205692 kb
Host	smart-a8e58f08-a6de-4785-b9bf-a6657f3c9941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354675319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2354675319 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.3686736172
Short name	T9
Test name
Test status
Simulation time	140423631 ps
CPU time	1.08 seconds
Started	Dec 24 12:50:15 PM PST 23
Finished	Dec 24 12:50:22 PM PST 23
Peak memory	215524 kb
Host	smart-943f9efa-5e0e-4fed-bd13-d47c8adb1cce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686736172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3686736172 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.453774495
Short name	T399
Test name
Test status
Simulation time	108743837372 ps
CPU time	685.91 seconds
Started	Dec 24 12:49:57 PM PST 23
Finished	Dec 24 01:01:35 PM PST 23
Peak memory	275404 kb
Host	smart-9cd56269-3184-41de-b693-0cc723082d11
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453774495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_an d_output.453774495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.2701569964
Short name	T1000
Test name
Test status
Simulation time	4182593688 ps
CPU time	149.03 seconds
Started	Dec 24 12:49:56 PM PST 23
Finished	Dec 24 12:52:35 PM PST 23
Peak memory	235368 kb
Host	smart-77f0e6e3-9f6e-4aba-8514-db4a0028afd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701569964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2701569964 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.3012508634
Short name	T701
Test name
Test status
Simulation time	2354194330 ps
CPU time	48.66 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:50:53 PM PST 23
Peak memory	219264 kb
Host	smart-197ee49b-a025-4015-b0ef-711d63630cee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012508634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3012508634 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.3451147818
Short name	T446
Test name
Test status
Simulation time	30225638233 ps
CPU time	538.67 seconds
Started	Dec 24 12:50:08 PM PST 23
Finished	Dec 24 12:59:14 PM PST 23
Peak memory	291252 kb
Host	smart-b02cb80a-fa03-48fc-9a65-7cd5ffd7f7bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3451147818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3451147818 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.3174118333
Short name	T814
Test name
Test status
Simulation time	8491353852 ps
CPU time	528.65 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:58:53 PM PST 23
Peak memory	288536 kb
Host	smart-07c94dd8-8f7f-4879-ad03-5e73991b1f2b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3174118333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.3174118333 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.2507095938
Short name	T842
Test name
Test status
Simulation time	258591201 ps
CPU time	5.05 seconds
Started	Dec 24 12:50:01 PM PST 23
Finished	Dec 24 12:50:18 PM PST 23
Peak memory	215688 kb
Host	smart-559a2a32-6fba-4627-a307-a72145382174
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507095938 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.2507095938 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.11024119
Short name	T430
Test name
Test status
Simulation time	1523275599 ps
CPU time	4.87 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 12:50:16 PM PST 23
Peak memory	215708 kb
Host	smart-4b4ec7b1-3f31-4681-9964-53db206e966b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11024119 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.kmac_test_vectors_kmac_xof.11024119 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.3767530867
Short name	T1059
Test name
Test status
Simulation time	83207912655 ps
CPU time	1762.31 seconds
Started	Dec 24 12:50:20 PM PST 23
Finished	Dec 24 01:19:46 PM PST 23
Peak memory	386860 kb
Host	smart-f836b333-70df-4aa6-bb87-704f0acb9e24
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3767530867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3767530867 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.848575112
Short name	T720
Test name
Test status
Simulation time	185194804917 ps
CPU time	1900.38 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:21:44 PM PST 23
Peak memory	370452 kb
Host	smart-c65db8e4-adf3-4707-8ad1-2694be70da45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=848575112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.848575112 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.448254995
Short name	T777
Test name
Test status
Simulation time	54463807146 ps
CPU time	1147.06 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 01:09:11 PM PST 23
Peak memory	334700 kb
Host	smart-0c63f6f3-1a78-441d-8a33-c5c514b35be0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=448254995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.448254995 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.1262328774
Short name	T212
Test name
Test status
Simulation time	9979407156 ps
CPU time	752.68 seconds
Started	Dec 24 12:50:00 PM PST 23
Finished	Dec 24 01:02:45 PM PST 23
Peak memory	293452 kb
Host	smart-987910ad-c04a-4478-a9a9-1bf6d0f607d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1262328774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1262328774 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.3502322689
Short name	T986
Test name
Test status
Simulation time	52123878496 ps
CPU time	4157.93 seconds
Started	Dec 24 12:49:47 PM PST 23
Finished	Dec 24 01:59:09 PM PST 23
Peak memory	654664 kb
Host	smart-0ed8eae7-b56c-4bd9-a071-0e6936017aa3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3502322689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3502322689 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.963826727
Short name	T849
Test name
Test status
Simulation time	626939751213 ps
CPU time	3891.27 seconds
Started	Dec 24 12:49:51 PM PST 23
Finished	Dec 24 01:54:52 PM PST 23
Peak memory	556352 kb
Host	smart-e91771d7-becb-406d-b725-f218da1d1f0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=963826727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.963826727 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.3280238190
Short name	T1016
Test name
Test status
Simulation time	28387893 ps
CPU time	0.77 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:48:36 PM PST 23
Peak memory	205192 kb
Host	smart-9d4b05a4-e28a-4477-8ce7-b3e7e90febdc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280238190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3280238190 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.2305250020
Short name	T935
Test name
Test status
Simulation time	10874440655 ps
CPU time	213.61 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 12:51:59 PM PST 23
Peak memory	239036 kb
Host	smart-139cd202-0a89-4d25-8bae-e23dda87cb46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305250020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2305250020 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.1724780778
Short name	T873
Test name
Test status
Simulation time	1153001729 ps
CPU time	5.33 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:48:40 PM PST 23
Peak memory	215688 kb
Host	smart-255aa15c-2d37-43ee-a840-0f2efc537365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724780778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1724780778 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.3103653108
Short name	T1020
Test name
Test status
Simulation time	1037903597 ps
CPU time	39.47 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	219184 kb
Host	smart-c130a942-bdda-4d65-b3da-56758ef2b391
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103653108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3103653108 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.1490970692
Short name	T195
Test name
Test status
Simulation time	4499072967 ps
CPU time	22.89 seconds
Started	Dec 24 12:48:28 PM PST 23
Finished	Dec 24 12:48:53 PM PST 23
Peak memory	220384 kb
Host	smart-a63afd4a-1cee-4630-8a5e-283827c78593
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1490970692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1490970692 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.3969046994
Short name	T1111
Test name
Test status
Simulation time	1440364374 ps
CPU time	22.83 seconds
Started	Dec 24 12:48:30 PM PST 23
Finished	Dec 24 12:48:54 PM PST 23
Peak memory	223728 kb
Host	smart-71c1be0c-4a7f-4ef4-b226-8a1b85e1249b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3969046994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3969046994 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3390079622
Short name	T298
Test name
Test status
Simulation time	12641322560 ps
CPU time	61.23 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:50:00 PM PST 23
Peak memory	216604 kb
Host	smart-a1012904-a095-4f68-b1c5-22410c4b3275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390079622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3390079622 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.3891854174
Short name	T731
Test name
Test status
Simulation time	64673974367 ps
CPU time	263.37 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 12:53:04 PM PST 23
Peak memory	243580 kb
Host	smart-28dca34a-8247-4f5f-9fdc-2d337f59774a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891854174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3891854174 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.449841261
Short name	T336
Test name
Test status
Simulation time	7445771975 ps
CPU time	45.41 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 12:49:29 PM PST 23
Peak memory	239340 kb
Host	smart-82fd7bc8-9675-4d59-83cb-e27dce0c2b9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449841261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.449841261 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.242925920
Short name	T547
Test name
Test status
Simulation time	109814153 ps
CPU time	1.12 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 12:48:42 PM PST 23
Peak memory	205408 kb
Host	smart-ad4ce094-90c8-4553-88f3-fcef666ff06a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242925920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.242925920 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.3063256310
Short name	T951
Test name
Test status
Simulation time	48147083 ps
CPU time	1.42 seconds
Started	Dec 24 12:48:43 PM PST 23
Finished	Dec 24 12:48:46 PM PST 23
Peak memory	217472 kb
Host	smart-399f9825-295b-4409-929c-df7c030a348b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063256310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3063256310 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.477102468
Short name	T454
Test name
Test status
Simulation time	21241372716 ps
CPU time	217.8 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:52:14 PM PST 23
Peak memory	238644 kb
Host	smart-70769d5b-67bc-4b0d-86c3-4885ef5daa21
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477102468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and _output.477102468 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.3295822875
Short name	T292
Test name
Test status
Simulation time	2376139279 ps
CPU time	41.46 seconds
Started	Dec 24 12:48:25 PM PST 23
Finished	Dec 24 12:49:08 PM PST 23
Peak memory	221888 kb
Host	smart-30e217e7-ab9c-4780-9e9e-160c3c3df0d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295822875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3295822875 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.2253341069
Short name	T68
Test name
Test status
Simulation time	3153834383 ps
CPU time	27.76 seconds
Started	Dec 24 12:48:36 PM PST 23
Finished	Dec 24 12:49:06 PM PST 23
Peak memory	246484 kb
Host	smart-6aab269b-d3ff-4a39-999d-2d80aec13ce2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253341069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2253341069 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.4268236436
Short name	T319
Test name
Test status
Simulation time	952861005 ps
CPU time	25.32 seconds
Started	Dec 24 12:49:04 PM PST 23
Finished	Dec 24 12:49:32 PM PST 23
Peak memory	223816 kb
Host	smart-d3b6ee7c-c228-48a1-914e-80275841829b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268236436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.4268236436 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.845682492
Short name	T180
Test name
Test status
Simulation time	674462985 ps
CPU time	14.23 seconds
Started	Dec 24 12:48:16 PM PST 23
Finished	Dec 24 12:48:32 PM PST 23
Peak memory	219124 kb
Host	smart-69017089-0dbe-4be4-a4c2-7385c9401561
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845682492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.845682492 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.2930572380
Short name	T1130
Test name
Test status
Simulation time	35397688387 ps
CPU time	1096.04 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 01:06:53 PM PST 23
Peak memory	404324 kb
Host	smart-7d52cb3c-130c-41f8-b052-6f2a13f532b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2930572380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2930572380 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.3018940635
Short name	T499
Test name
Test status
Simulation time	263068359 ps
CPU time	5.02 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:49:01 PM PST 23
Peak memory	215696 kb
Host	smart-35c8eb09-e624-4db9-9e9e-3c73689abba3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018940635 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.3018940635 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2516054968
Short name	T343
Test name
Test status
Simulation time	128857972 ps
CPU time	4.08 seconds
Started	Dec 24 12:48:48 PM PST 23
Finished	Dec 24 12:48:53 PM PST 23
Peak memory	208532 kb
Host	smart-697f14fe-ef20-4f34-8fa9-b1ebb61083bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516054968 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2516054968 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.2713618199
Short name	T371
Test name
Test status
Simulation time	202780839318 ps
CPU time	2001.84 seconds
Started	Dec 24 12:48:44 PM PST 23
Finished	Dec 24 01:22:07 PM PST 23
Peak memory	392808 kb
Host	smart-7a1581be-4ebb-47cc-9fa4-284650f3ed9a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2713618199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2713618199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.1713321024
Short name	T388
Test name
Test status
Simulation time	62203922444 ps
CPU time	1853.12 seconds
Started	Dec 24 12:48:45 PM PST 23
Finished	Dec 24 01:19:39 PM PST 23
Peak memory	387332 kb
Host	smart-4f09b2c9-c862-42ad-89cd-43887eafd224
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1713321024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1713321024 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.1579675092
Short name	T1084
Test name
Test status
Simulation time	178873624281 ps
CPU time	1356.43 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 01:11:13 PM PST 23
Peak memory	333048 kb
Host	smart-89236302-0f60-4b4c-b02a-695d89e3faa7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1579675092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1579675092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.61480012
Short name	T1115
Test name
Test status
Simulation time	9932998194 ps
CPU time	782.85 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 01:01:38 PM PST 23
Peak memory	295592 kb
Host	smart-4753760f-0042-4bb1-9e54-9aee297bbebe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=61480012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.61480012 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.3548297117
Short name	T743
Test name
Test status
Simulation time	179312857246 ps
CPU time	4871.54 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 02:10:12 PM PST 23
Peak memory	640256 kb
Host	smart-de2482fb-7a9b-4d2e-a3ce-02a3d69b5e10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3548297117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3548297117 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.171579658
Short name	T764
Test name
Test status
Simulation time	86977705357 ps
CPU time	3449.28 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 01:46:06 PM PST 23
Peak memory	565168 kb
Host	smart-82da6bf1-5e7f-492f-837f-928d1b347d0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=171579658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.171579658 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.1621236967
Short name	T671
Test name
Test status
Simulation time	16624247 ps
CPU time	0.77 seconds
Started	Dec 24 12:50:08 PM PST 23
Finished	Dec 24 12:50:16 PM PST 23
Peak memory	205180 kb
Host	smart-a886a899-3ee3-4a33-9030-de8dc7d1aa2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621236967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1621236967 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.576179535
Short name	T393
Test name
Test status
Simulation time	7999015494 ps
CPU time	137.9 seconds
Started	Dec 24 12:49:56 PM PST 23
Finished	Dec 24 12:52:24 PM PST 23
Peak memory	232280 kb
Host	smart-6cf58fe0-f893-45e5-870a-f79740ab4946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576179535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.576179535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.3846501916
Short name	T1127
Test name
Test status
Simulation time	40564577203 ps
CPU time	214.03 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:53:38 PM PST 23
Peak memory	239464 kb
Host	smart-cac87b23-dca2-48c4-a6fd-7299d03cbfee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846501916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3846501916 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_error.1571761905
Short name	T686
Test name
Test status
Simulation time	12402575049 ps
CPU time	137.86 seconds
Started	Dec 24 12:50:19 PM PST 23
Finished	Dec 24 12:52:54 PM PST 23
Peak memory	248452 kb
Host	smart-0adfb500-e032-4287-a8b1-8376d5dcab3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571761905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1571761905 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/20.kmac_key_error.1243942437
Short name	T987
Test name
Test status
Simulation time	474794743 ps
CPU time	2.82 seconds
Started	Dec 24 12:50:02 PM PST 23
Finished	Dec 24 12:50:17 PM PST 23
Peak memory	207256 kb
Host	smart-3ff32a2b-00d7-453a-845f-acca3f3d26e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243942437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1243942437 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.1392836153
Short name	T586
Test name
Test status
Simulation time	127983138 ps
CPU time	1.33 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 12:50:12 PM PST 23
Peak memory	215532 kb
Host	smart-e02102f2-0938-4d81-822d-64150e28e758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392836153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1392836153 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.739853751
Short name	T186
Test name
Test status
Simulation time	25281268232 ps
CPU time	713.29 seconds
Started	Dec 24 12:50:04 PM PST 23
Finished	Dec 24 01:02:08 PM PST 23
Peak memory	288452 kb
Host	smart-2e68fb6d-1a44-4e71-a771-bd28f9d261e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739853751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an d_output.739853751 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.246119129
Short name	T386
Test name
Test status
Simulation time	63239744234 ps
CPU time	245.72 seconds
Started	Dec 24 12:49:55 PM PST 23
Finished	Dec 24 12:54:10 PM PST 23
Peak memory	240824 kb
Host	smart-2df658c8-943d-4c5a-b369-efff6ec12d43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246119129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.246119129 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.577779006
Short name	T901
Test name
Test status
Simulation time	7818194682 ps
CPU time	60.43 seconds
Started	Dec 24 12:49:53 PM PST 23
Finished	Dec 24 12:51:04 PM PST 23
Peak memory	216548 kb
Host	smart-87aff38f-bcc3-48e3-9c1b-ee1f80f2a2b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577779006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.577779006 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.1803870804
Short name	T826
Test name
Test status
Simulation time	692019496 ps
CPU time	11.64 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 12:50:23 PM PST 23
Peak memory	217868 kb
Host	smart-04aa8d13-f644-4c84-95e3-f1ba62e08e39
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1803870804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1803870804 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.3392309066
Short name	T890
Test name
Test status
Simulation time	91309541 ps
CPU time	3.82 seconds
Started	Dec 24 12:49:55 PM PST 23
Finished	Dec 24 12:50:10 PM PST 23
Peak memory	215764 kb
Host	smart-435ca16f-698f-4f59-81f5-17a737a4d1fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392309066 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.kmac_test_vectors_kmac.3392309066 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2006016947
Short name	T209
Test name
Test status
Simulation time	968480516 ps
CPU time	5.4 seconds
Started	Dec 24 12:50:24 PM PST 23
Finished	Dec 24 12:50:32 PM PST 23
Peak memory	215664 kb
Host	smart-4367f350-1e5f-4289-9619-f70a52019779
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006016947 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2006016947 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.1317556023
Short name	T143
Test name
Test status
Simulation time	101359085032 ps
CPU time	2027.63 seconds
Started	Dec 24 12:50:00 PM PST 23
Finished	Dec 24 01:24:00 PM PST 23
Peak memory	400444 kb
Host	smart-5970db65-d3ca-407f-8974-35711d873cda
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1317556023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1317556023 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.4230987911
Short name	T496
Test name
Test status
Simulation time	239932777114 ps
CPU time	1739.22 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:19:03 PM PST 23
Peak memory	367456 kb
Host	smart-461610ed-4b2e-4f40-8cba-7d5f4f75bdc2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4230987911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.4230987911 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.2896250508
Short name	T902
Test name
Test status
Simulation time	13942226417 ps
CPU time	1059.23 seconds
Started	Dec 24 12:49:56 PM PST 23
Finished	Dec 24 01:07:45 PM PST 23
Peak memory	329504 kb
Host	smart-adc8896b-898d-4515-8112-3de7a1dd6afd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2896250508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2896250508 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.3957541355
Short name	T689
Test name
Test status
Simulation time	49999493319 ps
CPU time	1023.94 seconds
Started	Dec 24 12:50:03 PM PST 23
Finished	Dec 24 01:07:18 PM PST 23
Peak memory	295392 kb
Host	smart-5a1cb497-ac71-4b10-98de-029408553e3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3957541355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3957541355 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.4137549926
Short name	T1133
Test name
Test status
Simulation time	1426852479832 ps
CPU time	4896.27 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 02:11:48 PM PST 23
Peak memory	646276 kb
Host	smart-cb1f13cf-5c0a-4622-a717-bb853555e7f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4137549926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.4137549926 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.3051326884
Short name	T568
Test name
Test status
Simulation time	731746623737 ps
CPU time	4336.85 seconds
Started	Dec 24 12:50:17 PM PST 23
Finished	Dec 24 02:02:39 PM PST 23
Peak memory	566732 kb
Host	smart-e8d1f307-9b2f-454a-b2b5-70587d03260e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3051326884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3051326884 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.1086701850
Short name	T733
Test name
Test status
Simulation time	18914333 ps
CPU time	0.81 seconds
Started	Dec 24 12:50:13 PM PST 23
Finished	Dec 24 12:50:20 PM PST 23
Peak memory	205200 kb
Host	smart-a7bb46a2-a0ad-4057-ad28-c9a5ce1e743c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086701850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1086701850 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.1354208345
Short name	T1033
Test name
Test status
Simulation time	6032836795 ps
CPU time	162.5 seconds
Started	Dec 24 12:49:58 PM PST 23
Finished	Dec 24 12:52:53 PM PST 23
Peak memory	237728 kb
Host	smart-21ef8ada-7bd6-4a1b-8ea9-a70a6405f8f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354208345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1354208345 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.1099138727
Short name	T1122
Test name
Test status
Simulation time	32901238217 ps
CPU time	713.51 seconds
Started	Dec 24 12:49:56 PM PST 23
Finished	Dec 24 01:02:00 PM PST 23
Peak memory	232540 kb
Host	smart-9844ec9e-98fd-41b2-a1df-15702a94a7d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099138727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1099138727 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.2517965196
Short name	T608
Test name
Test status
Simulation time	2571499827 ps
CPU time	13.13 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 12:50:20 PM PST 23
Peak memory	223868 kb
Host	smart-d9015281-f89e-4511-9aac-28b40f4996cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517965196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2517965196 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_error.403731629
Short name	T511
Test name
Test status
Simulation time	71733205726 ps
CPU time	245.02 seconds
Started	Dec 24 12:50:01 PM PST 23
Finished	Dec 24 12:54:18 PM PST 23
Peak memory	248556 kb
Host	smart-df51ead2-5e5f-43c6-a09e-4151f0962d97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403731629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.403731629 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.1302624981
Short name	T64
Test name
Test status
Simulation time	603583175 ps
CPU time	2.93 seconds
Started	Dec 24 12:50:13 PM PST 23
Finished	Dec 24 12:50:22 PM PST 23
Peak memory	207048 kb
Host	smart-aaa3e86b-3062-4c3e-bb48-805e8cd599d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302624981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1302624981 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.1237495381
Short name	T597
Test name
Test status
Simulation time	27289226 ps
CPU time	1.19 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 12:50:39 PM PST 23
Peak memory	216764 kb
Host	smart-c6bd4027-5a9e-4f46-8450-08a6e1618160
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237495381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1237495381 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.1671973426
Short name	T601
Test name
Test status
Simulation time	5689063786 ps
CPU time	119.4 seconds
Started	Dec 24 12:50:04 PM PST 23
Finished	Dec 24 12:52:14 PM PST 23
Peak memory	224420 kb
Host	smart-ba56ca2c-9eca-4d30-839e-3adde355c384
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671973426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.1671973426 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.4020192966
Short name	T695
Test name
Test status
Simulation time	74040841001 ps
CPU time	408.48 seconds
Started	Dec 24 12:50:03 PM PST 23
Finished	Dec 24 12:57:03 PM PST 23
Peak memory	250008 kb
Host	smart-50c83fc6-5904-4a4c-90a6-3359623538e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020192966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4020192966 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.2487725477
Short name	T15
Test name
Test status
Simulation time	3025328838 ps
CPU time	32.94 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 12:50:45 PM PST 23
Peak memory	219360 kb
Host	smart-af1bc8d3-30c0-42b6-b32b-4eb87c0520d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487725477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2487725477 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.124422250
Short name	T838
Test name
Test status
Simulation time	40007144195 ps
CPU time	588.48 seconds
Started	Dec 24 12:50:01 PM PST 23
Finished	Dec 24 01:00:02 PM PST 23
Peak memory	303844 kb
Host	smart-69018abe-463d-4d65-8a27-0589297342f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=124422250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.124422250 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_stress_all_with_rand_reset.3626168568
Short name	T669
Test name
Test status
Simulation time	21285851066 ps
CPU time	225.05 seconds
Started	Dec 24 12:50:06 PM PST 23
Finished	Dec 24 12:54:00 PM PST 23
Peak memory	240348 kb
Host	smart-6bf1d2b6-c66a-479a-a96f-69445c8656bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3626168568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.3626168568 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.324640635
Short name	T322
Test name
Test status
Simulation time	71152883 ps
CPU time	3.96 seconds
Started	Dec 24 12:49:54 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	209064 kb
Host	smart-7155f253-246c-4571-af37-365a37324c83
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324640635 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.kmac_test_vectors_kmac.324640635 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3865331612
Short name	T184
Test name
Test status
Simulation time	525350072 ps
CPU time	4.86 seconds
Started	Dec 24 12:50:04 PM PST 23
Finished	Dec 24 12:50:19 PM PST 23
Peak memory	208780 kb
Host	smart-24348d2b-59b1-4c81-9747-f26e6ffbf799
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865331612 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3865331612 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.1669710492
Short name	T790
Test name
Test status
Simulation time	969839710844 ps
CPU time	1915.82 seconds
Started	Dec 24 12:50:00 PM PST 23
Finished	Dec 24 01:22:08 PM PST 23
Peak memory	391028 kb
Host	smart-847d3682-f755-47b2-b722-95e0a93d2e0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1669710492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1669710492 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.3912435323
Short name	T927
Test name
Test status
Simulation time	210676231479 ps
CPU time	1689.21 seconds
Started	Dec 24 12:49:59 PM PST 23
Finished	Dec 24 01:18:21 PM PST 23
Peak memory	370440 kb
Host	smart-5d8b56b4-6114-49ff-99a4-0cca40df658d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3912435323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3912435323 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.4078700815
Short name	T370
Test name
Test status
Simulation time	467811385516 ps
CPU time	1503.72 seconds
Started	Dec 24 12:50:08 PM PST 23
Finished	Dec 24 01:15:19 PM PST 23
Peak memory	334212 kb
Host	smart-c72ffe91-f936-4989-a10f-20b8010e7363
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4078700815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.4078700815 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.7726448
Short name	T1026
Test name
Test status
Simulation time	10063701894 ps
CPU time	800.1 seconds
Started	Dec 24 12:50:07 PM PST 23
Finished	Dec 24 01:03:35 PM PST 23
Peak memory	298032 kb
Host	smart-83e376b2-0359-4a1f-b2dc-21d119eea360
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=7726448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.7726448 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.2501667412
Short name	T274
Test name
Test status
Simulation time	231009279426 ps
CPU time	4223 seconds
Started	Dec 24 12:50:13 PM PST 23
Finished	Dec 24 02:00:43 PM PST 23
Peak memory	650200 kb
Host	smart-a1464480-f03b-403f-b022-4a00434a8571
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2501667412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2501667412 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.3402556980
Short name	T861
Test name
Test status
Simulation time	863034491969 ps
CPU time	4102 seconds
Started	Dec 24 12:50:03 PM PST 23
Finished	Dec 24 01:58:37 PM PST 23
Peak memory	568428 kb
Host	smart-35f1209c-2d15-4412-bc3c-077f66abdda0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3402556980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3402556980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.4128877386
Short name	T239
Test name
Test status
Simulation time	14100546 ps
CPU time	0.77 seconds
Started	Dec 24 12:50:35 PM PST 23
Finished	Dec 24 12:50:41 PM PST 23
Peak memory	205096 kb
Host	smart-420078bf-3f90-4ee0-8b27-01581f2bd662
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128877386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.4128877386 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.2075583366
Short name	T916
Test name
Test status
Simulation time	21332137489 ps
CPU time	145.55 seconds
Started	Dec 24 12:50:49 PM PST 23
Finished	Dec 24 12:53:16 PM PST 23
Peak memory	235060 kb
Host	smart-b7ff7db2-1c46-4c5e-8145-ac4053603dc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075583366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2075583366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.3742512349
Short name	T72
Test name
Test status
Simulation time	104700152437 ps
CPU time	630.28 seconds
Started	Dec 24 12:50:05 PM PST 23
Finished	Dec 24 01:00:45 PM PST 23
Peak memory	230752 kb
Host	smart-08585c9f-52b0-4c98-b5a3-94e99fbe0382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742512349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3742512349 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.2454425143
Short name	T889
Test name
Test status
Simulation time	20699761614 ps
CPU time	87.19 seconds
Started	Dec 24 12:50:25 PM PST 23
Finished	Dec 24 12:51:55 PM PST 23
Peak memory	227008 kb
Host	smart-d34618ec-4113-4b4a-9ffc-a052877df115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454425143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2454425143 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.3931877680
Short name	T559
Test name
Test status
Simulation time	2232854286 ps
CPU time	152.33 seconds
Started	Dec 24 12:50:32 PM PST 23
Finished	Dec 24 12:53:10 PM PST 23
Peak memory	255500 kb
Host	smart-66ec8a40-510c-4554-a26e-5def193c820d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3931877680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3931877680 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.3477503333
Short name	T443
Test name
Test status
Simulation time	3363368786 ps
CPU time	3.42 seconds
Started	Dec 24 12:50:35 PM PST 23
Finished	Dec 24 12:50:44 PM PST 23
Peak memory	207364 kb
Host	smart-33fd32b5-4089-46b0-be81-e16304793194
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477503333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3477503333 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.714995550
Short name	T834
Test name
Test status
Simulation time	24378403 ps
CPU time	1.21 seconds
Started	Dec 24 12:50:26 PM PST 23
Finished	Dec 24 12:50:30 PM PST 23
Peak memory	215592 kb
Host	smart-8a63ab78-9ba3-4a33-b6f8-c02a2a4da772
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714995550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.714995550 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.2632108827
Short name	T218
Test name
Test status
Simulation time	169693656273 ps
CPU time	2375.58 seconds
Started	Dec 24 12:49:52 PM PST 23
Finished	Dec 24 01:29:40 PM PST 23
Peak memory	458436 kb
Host	smart-82b24c09-f35c-48e1-b589-f59082fc01a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632108827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.2632108827 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.1017776474
Short name	T473
Test name
Test status
Simulation time	52032987674 ps
CPU time	301.36 seconds
Started	Dec 24 12:50:08 PM PST 23
Finished	Dec 24 12:55:17 PM PST 23
Peak memory	244340 kb
Host	smart-a3e57177-d99d-4bce-ae68-94362dc2dae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017776474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1017776474 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.996697736
Short name	T656
Test name
Test status
Simulation time	3485567150 ps
CPU time	44.89 seconds
Started	Dec 24 12:50:12 PM PST 23
Finished	Dec 24 12:51:03 PM PST 23
Peak memory	219232 kb
Host	smart-501c88eb-ccc2-4374-b35e-b594d285f717
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996697736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.996697736 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.2702738120
Short name	T862
Test name
Test status
Simulation time	23704354754 ps
CPU time	109.48 seconds
Started	Dec 24 12:50:30 PM PST 23
Finished	Dec 24 12:52:27 PM PST 23
Peak memory	255968 kb
Host	smart-330ec506-a83a-481a-a3dc-3769fcb2b550
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2702738120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2702738120 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.1379377231
Short name	T1064
Test name
Test status
Simulation time	239693257 ps
CPU time	4.3 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 12:50:43 PM PST 23
Peak memory	215680 kb
Host	smart-eb0ecd5e-b9a1-4da4-87c2-f91c268aea71
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379377231 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.1379377231 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3214682799
Short name	T283
Test name
Test status
Simulation time	69735936 ps
CPU time	3.82 seconds
Started	Dec 24 12:50:36 PM PST 23
Finished	Dec 24 12:50:46 PM PST 23
Peak memory	215708 kb
Host	smart-28868e7a-00db-4b90-991a-06a34b3e9be9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214682799 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3214682799 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.2412509327
Short name	T318
Test name
Test status
Simulation time	74183582058 ps
CPU time	1443.29 seconds
Started	Dec 24 12:50:29 PM PST 23
Finished	Dec 24 01:14:40 PM PST 23
Peak memory	378604 kb
Host	smart-2d28db08-bfd5-4abe-ba3d-fe1eab4e890f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2412509327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2412509327 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.1229886897
Short name	T362
Test name
Test status
Simulation time	64571001854 ps
CPU time	1685.73 seconds
Started	Dec 24 12:50:43 PM PST 23
Finished	Dec 24 01:18:51 PM PST 23
Peak memory	378072 kb
Host	smart-c02004af-ff97-4319-88c5-fa9e8d0b80dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1229886897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1229886897 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.1380501904
Short name	T919
Test name
Test status
Simulation time	50466587179 ps
CPU time	1069.09 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 01:08:28 PM PST 23
Peak memory	333824 kb
Host	smart-c3fa1772-4619-4618-8ee4-9e5fc5e2b696
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1380501904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1380501904 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.755031145
Short name	T851
Test name
Test status
Simulation time	9492148604 ps
CPU time	802.89 seconds
Started	Dec 24 12:50:31 PM PST 23
Finished	Dec 24 01:04:01 PM PST 23
Peak memory	294084 kb
Host	smart-08c1b0ef-8ef0-4213-aa5e-aa80a81e4d17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=755031145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.755031145 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.3459138539
Short name	T1088
Test name
Test status
Simulation time	721255205713 ps
CPU time	4787.2 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 02:10:17 PM PST 23
Peak memory	656580 kb
Host	smart-5795f06f-8a67-49bc-9b5d-d673c8d3d75c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3459138539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.3459138539 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.1278981798
Short name	T664
Test name
Test status
Simulation time	179800813482 ps
CPU time	3410.58 seconds
Started	Dec 24 12:50:30 PM PST 23
Finished	Dec 24 01:47:29 PM PST 23
Peak memory	558988 kb
Host	smart-70f0ac48-d70a-4c8e-965b-523f3a004cfe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1278981798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1278981798 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.2884712845
Short name	T49
Test name
Test status
Simulation time	235330435 ps
CPU time	0.92 seconds
Started	Dec 24 12:50:29 PM PST 23
Finished	Dec 24 12:50:37 PM PST 23
Peak memory	205208 kb
Host	smart-05028112-db57-4a7d-954c-a3dbe0be8461
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884712845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2884712845 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.2979024280
Short name	T835
Test name
Test status
Simulation time	6134069069 ps
CPU time	33.73 seconds
Started	Dec 24 12:50:30 PM PST 23
Finished	Dec 24 12:51:11 PM PST 23
Peak memory	220404 kb
Host	smart-f7fe80a0-23c5-4f7a-bf3d-70e651f6cdce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979024280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2979024280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.1627914793
Short name	T1136
Test name
Test status
Simulation time	550800729 ps
CPU time	16.98 seconds
Started	Dec 24 12:50:28 PM PST 23
Finished	Dec 24 12:50:52 PM PST 23
Peak memory	218876 kb
Host	smart-eec54dd1-562e-41a6-9e01-ee79e0bffaf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627914793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1627914793 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.3667359818
Short name	T621
Test name
Test status
Simulation time	3150771562 ps
CPU time	24.43 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 12:51:03 PM PST 23
Peak memory	223848 kb
Host	smart-c7e2f21e-ab81-4c53-a3e7-0a04eb993c8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667359818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3667359818 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.736876206
Short name	T810
Test name
Test status
Simulation time	4663999174 ps
CPU time	97.68 seconds
Started	Dec 24 12:50:23 PM PST 23
Finished	Dec 24 12:52:03 PM PST 23
Peak memory	240156 kb
Host	smart-baf30ef8-2708-4f83-ad6f-f7fdc067ee46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736876206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.736876206 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_key_error.4093723535
Short name	T900
Test name
Test status
Simulation time	2006545135 ps
CPU time	5.53 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 12:50:35 PM PST 23
Peak memory	207204 kb
Host	smart-bb8c89d0-7527-48c9-91a5-9f9d8507c58a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093723535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.4093723535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.2271983658
Short name	T459
Test name
Test status
Simulation time	2131833467 ps
CPU time	24.23 seconds
Started	Dec 24 12:50:32 PM PST 23
Finished	Dec 24 12:51:02 PM PST 23
Peak memory	228768 kb
Host	smart-a40b1f4b-9fb8-43af-824d-3a688716ac0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271983658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2271983658 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.716812714
Short name	T991
Test name
Test status
Simulation time	23441352576 ps
CPU time	2089.5 seconds
Started	Dec 24 12:50:38 PM PST 23
Finished	Dec 24 01:25:33 PM PST 23
Peak memory	441608 kb
Host	smart-ad151222-1cbc-42d9-b7e8-e9755dda9846
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716812714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_an d_output.716812714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.3200275024
Short name	T776
Test name
Test status
Simulation time	32501640024 ps
CPU time	290.37 seconds
Started	Dec 24 12:50:29 PM PST 23
Finished	Dec 24 12:55:26 PM PST 23
Peak memory	242740 kb
Host	smart-4d4165c6-206d-4d56-9d76-67b0ed14edd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200275024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3200275024 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.3935621609
Short name	T615
Test name
Test status
Simulation time	751272996 ps
CPU time	3.81 seconds
Started	Dec 24 12:50:50 PM PST 23
Finished	Dec 24 12:50:56 PM PST 23
Peak memory	221356 kb
Host	smart-bef26df5-dc6e-4444-af3e-6ca545804c7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935621609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3935621609 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.2760166765
Short name	T1079
Test name
Test status
Simulation time	42142855590 ps
CPU time	541.17 seconds
Started	Dec 24 12:50:38 PM PST 23
Finished	Dec 24 12:59:44 PM PST 23
Peak memory	301828 kb
Host	smart-03d5428a-5b26-4f99-b2ca-450a9a243bb5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2760166765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2760166765 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_stress_all_with_rand_reset.3953902094
Short name	T584
Test name
Test status
Simulation time	410323028616 ps
CPU time	2155.78 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 01:26:34 PM PST 23
Peak memory	334024 kb
Host	smart-b20c5310-15ca-499b-b54e-4916dd944c8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3953902094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.3953902094 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.3254084192
Short name	T574
Test name
Test status
Simulation time	176338294 ps
CPU time	5.08 seconds
Started	Dec 24 12:50:40 PM PST 23
Finished	Dec 24 12:50:49 PM PST 23
Peak memory	208592 kb
Host	smart-178e291e-1845-4334-bdb2-547a09cbee7c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254084192 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.3254084192 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.32341102
Short name	T450
Test name
Test status
Simulation time	835938172 ps
CPU time	4.93 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 12:50:35 PM PST 23
Peak memory	208796 kb
Host	smart-014f095d-b858-4b5d-9748-c57ccce55bee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341102 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.kmac_test_vectors_kmac_xof.32341102 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.1827382219
Short name	T977
Test name
Test status
Simulation time	142904811292 ps
CPU time	1937.94 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 01:22:48 PM PST 23
Peak memory	373984 kb
Host	smart-311202f9-87c9-4194-9f33-cc782530afa4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1827382219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1827382219 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.2256649232
Short name	T795
Test name
Test status
Simulation time	37376610276 ps
CPU time	1536.91 seconds
Started	Dec 24 12:50:31 PM PST 23
Finished	Dec 24 01:16:15 PM PST 23
Peak memory	377780 kb
Host	smart-fbc2dd57-734e-4a7c-aaae-264bc0c075a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2256649232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2256649232 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.2255629747
Short name	T675
Test name
Test status
Simulation time	47810676432 ps
CPU time	1270.09 seconds
Started	Dec 24 12:50:28 PM PST 23
Finished	Dec 24 01:11:46 PM PST 23
Peak memory	339176 kb
Host	smart-e0897ed1-23de-4692-afbc-6db8a36723fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2255629747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2255629747 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.568013843
Short name	T985
Test name
Test status
Simulation time	39812403038 ps
CPU time	791.2 seconds
Started	Dec 24 12:50:39 PM PST 23
Finished	Dec 24 01:03:55 PM PST 23
Peak memory	295340 kb
Host	smart-f80a6a16-b1a4-4720-a541-4aa69b59fafe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=568013843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.568013843 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.2858578905
Short name	T1014
Test name
Test status
Simulation time	3463282481171 ps
CPU time	5845.13 seconds
Started	Dec 24 12:50:30 PM PST 23
Finished	Dec 24 02:28:03 PM PST 23
Peak memory	657216 kb
Host	smart-e5e83064-420f-404e-9f06-2d36f1d46762
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2858578905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2858578905 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.2703865178
Short name	T947
Test name
Test status
Simulation time	606695779061 ps
CPU time	3906.9 seconds
Started	Dec 24 12:50:28 PM PST 23
Finished	Dec 24 01:55:42 PM PST 23
Peak memory	562788 kb
Host	smart-e0c9bc41-24e0-4b12-b30b-4875466d73cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2703865178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.2703865178 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.3864645441
Short name	T767
Test name
Test status
Simulation time	18501164 ps
CPU time	0.82 seconds
Started	Dec 24 12:50:35 PM PST 23
Finished	Dec 24 12:50:41 PM PST 23
Peak memory	205092 kb
Host	smart-43688d8f-c621-4c30-a8e7-729d29467996
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864645441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3864645441 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.1922206439
Short name	T110
Test name
Test status
Simulation time	8720523841 ps
CPU time	209.94 seconds
Started	Dec 24 12:50:36 PM PST 23
Finished	Dec 24 12:54:11 PM PST 23
Peak memory	242468 kb
Host	smart-1e040f57-3b76-41ba-a5de-8c3d64571e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922206439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1922206439 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.3181221987
Short name	T537
Test name
Test status
Simulation time	2737434695 ps
CPU time	58.32 seconds
Started	Dec 24 12:50:41 PM PST 23
Finished	Dec 24 12:51:42 PM PST 23
Peak memory	227556 kb
Host	smart-75182e42-bef4-4bc0-9b83-2928df5d5afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181221987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3181221987 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.3469226164
Short name	T458
Test name
Test status
Simulation time	404365562 ps
CPU time	1.23 seconds
Started	Dec 24 12:50:44 PM PST 23
Finished	Dec 24 12:50:48 PM PST 23
Peak memory	207224 kb
Host	smart-ac84b65b-2ac8-46ee-a126-4ed193664acf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469226164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3469226164 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.2194689969
Short name	T489
Test name
Test status
Simulation time	818076980 ps
CPU time	62.76 seconds
Started	Dec 24 12:50:36 PM PST 23
Finished	Dec 24 12:51:44 PM PST 23
Peak memory	233040 kb
Host	smart-7d94afeb-df1f-4b0f-ac79-850a34f3b1fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194689969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2194689969 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.2215830943
Short name	T708
Test name
Test status
Simulation time	1440028691 ps
CPU time	4.07 seconds
Started	Dec 24 12:50:44 PM PST 23
Finished	Dec 24 12:50:50 PM PST 23
Peak memory	207096 kb
Host	smart-0ab43ceb-b9e2-4aea-8fd8-f7ac50299165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215830943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2215830943 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.4184549909
Short name	T1053
Test name
Test status
Simulation time	32875506 ps
CPU time	1.3 seconds
Started	Dec 24 12:50:38 PM PST 23
Finished	Dec 24 12:50:44 PM PST 23
Peak memory	217368 kb
Host	smart-5600a582-6dfb-4f89-871c-28b7304febe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184549909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.4184549909 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.686107558
Short name	T644
Test name
Test status
Simulation time	86470594594 ps
CPU time	628.24 seconds
Started	Dec 24 12:50:39 PM PST 23
Finished	Dec 24 01:01:12 PM PST 23
Peak memory	280848 kb
Host	smart-d06d6e05-633f-47d8-881f-32f476212473
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686107558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an d_output.686107558 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.1387727804
Short name	T990
Test name
Test status
Simulation time	4879311647 ps
CPU time	93.3 seconds
Started	Dec 24 12:50:28 PM PST 23
Finished	Dec 24 12:52:08 PM PST 23
Peak memory	227756 kb
Host	smart-2ea6a0eb-067f-4502-9f50-8686f9986de9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387727804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1387727804 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.82603016
Short name	T684
Test name
Test status
Simulation time	6887394429 ps
CPU time	61.32 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 12:51:31 PM PST 23
Peak memory	218964 kb
Host	smart-a718d118-c17b-4f75-87bb-b7013b960a9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82603016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.82603016 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.2850418858
Short name	T960
Test name
Test status
Simulation time	13620724553 ps
CPU time	196.22 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 12:53:54 PM PST 23
Peak memory	235092 kb
Host	smart-769466dd-232e-4b89-a39e-356726df0c3e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2850418858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2850418858 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.4158129652
Short name	T476
Test name
Test status
Simulation time	263365970 ps
CPU time	4.15 seconds
Started	Dec 24 12:50:31 PM PST 23
Finished	Dec 24 12:50:42 PM PST 23
Peak memory	215716 kb
Host	smart-3df04630-1aef-436d-88ee-ba9a533a6acc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158129652 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.4158129652 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1720798225
Short name	T1104
Test name
Test status
Simulation time	596585427 ps
CPU time	4.53 seconds
Started	Dec 24 12:50:39 PM PST 23
Finished	Dec 24 12:50:48 PM PST 23
Peak memory	215788 kb
Host	smart-02c1696f-9fbe-417e-b023-7cb1f2eecd3c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720798225 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1720798225 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.2684895305
Short name	T820
Test name
Test status
Simulation time	198792487655 ps
CPU time	1913.22 seconds
Started	Dec 24 12:50:29 PM PST 23
Finished	Dec 24 01:22:29 PM PST 23
Peak memory	392612 kb
Host	smart-0a3febda-0c8d-4f14-b7f8-150012af2c14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2684895305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2684895305 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.1118938620
Short name	T1018
Test name
Test status
Simulation time	136189789799 ps
CPU time	1807.42 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 01:20:46 PM PST 23
Peak memory	377932 kb
Host	smart-c50db2d0-3969-4937-841d-326c09237d15
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1118938620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.1118938620 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.3893480272
Short name	T1083
Test name
Test status
Simulation time	140637737793 ps
CPU time	1414.22 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 01:14:13 PM PST 23
Peak memory	329968 kb
Host	smart-48e5646b-1d4f-4e9f-ac83-32d2837b23d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3893480272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3893480272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.3710258798
Short name	T1146
Test name
Test status
Simulation time	32621725100 ps
CPU time	899.52 seconds
Started	Dec 24 12:50:29 PM PST 23
Finished	Dec 24 01:05:36 PM PST 23
Peak memory	290064 kb
Host	smart-e428eb1d-a61a-4d21-a8a9-659d44059814
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3710258798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3710258798 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.3576886975
Short name	T271
Test name
Test status
Simulation time	1311505358703 ps
CPU time	5469.77 seconds
Started	Dec 24 12:50:24 PM PST 23
Finished	Dec 24 02:21:37 PM PST 23
Peak memory	650304 kb
Host	smart-3c9913a3-fac2-4985-b050-d3f24919495c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3576886975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3576886975 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.660700198
Short name	T854
Test name
Test status
Simulation time	43515447812 ps
CPU time	3386.8 seconds
Started	Dec 24 12:50:31 PM PST 23
Finished	Dec 24 01:47:05 PM PST 23
Peak memory	567288 kb
Host	smart-d81ec3a5-4133-4275-aac7-2ca97bb58e6f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=660700198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.660700198 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.985560370
Short name	T881
Test name
Test status
Simulation time	36175898 ps
CPU time	0.77 seconds
Started	Dec 24 12:51:01 PM PST 23
Finished	Dec 24 12:51:12 PM PST 23
Peak memory	205072 kb
Host	smart-90649779-be27-47bf-9961-d5bd55c053c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985560370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.985560370 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.1206574954
Short name	T487
Test name
Test status
Simulation time	3849126718 ps
CPU time	80.9 seconds
Started	Dec 24 12:50:44 PM PST 23
Finished	Dec 24 12:52:07 PM PST 23
Peak memory	227424 kb
Host	smart-99171edd-2aac-4e8c-b0be-bc0f0de7d11c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206574954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1206574954 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.2511748839
Short name	T836
Test name
Test status
Simulation time	2915957827 ps
CPU time	58.14 seconds
Started	Dec 24 12:50:27 PM PST 23
Finished	Dec 24 12:51:28 PM PST 23
Peak memory	223876 kb
Host	smart-d137128a-4ba7-472a-8d53-6b08841d8638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511748839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2511748839 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.4165610730
Short name	T674
Test name
Test status
Simulation time	72609335327 ps
CPU time	326.13 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 12:56:05 PM PST 23
Peak memory	244728 kb
Host	smart-1265e318-d76d-4062-ba9d-0ba48c5dab94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165610730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4165610730 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.1471820512
Short name	T552
Test name
Test status
Simulation time	28139950482 ps
CPU time	278.49 seconds
Started	Dec 24 12:50:30 PM PST 23
Finished	Dec 24 12:55:15 PM PST 23
Peak memory	253996 kb
Host	smart-6e07b135-005a-42a5-a711-c685c2c01380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471820512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1471820512 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.4136946109
Short name	T1121
Test name
Test status
Simulation time	456736538 ps
CPU time	3.08 seconds
Started	Dec 24 12:50:32 PM PST 23
Finished	Dec 24 12:50:41 PM PST 23
Peak memory	207216 kb
Host	smart-9134fc73-16ec-4a17-9628-e52d6ec2e8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136946109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.4136946109 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.2811870452
Short name	T949
Test name
Test status
Simulation time	118860484 ps
CPU time	1.32 seconds
Started	Dec 24 12:50:35 PM PST 23
Finished	Dec 24 12:50:41 PM PST 23
Peak memory	217900 kb
Host	smart-6f379fe2-46a6-4e10-b657-5f199fd91a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811870452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2811870452 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.2757486396
Short name	T7
Test name
Test status
Simulation time	21598116191 ps
CPU time	1794.88 seconds
Started	Dec 24 12:50:38 PM PST 23
Finished	Dec 24 01:20:38 PM PST 23
Peak memory	421684 kb
Host	smart-723bdb20-cd3f-4b6b-a9d3-b3d7974f5c11
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757486396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a nd_output.2757486396 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.605023377
Short name	T468
Test name
Test status
Simulation time	60876915646 ps
CPU time	320.34 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 12:55:59 PM PST 23
Peak memory	245256 kb
Host	smart-054febb9-613c-446f-a5bd-a399c8b3466e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605023377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.605023377 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.3663104344
Short name	T648
Test name
Test status
Simulation time	1159918487 ps
CPU time	15.09 seconds
Started	Dec 24 12:50:24 PM PST 23
Finished	Dec 24 12:50:41 PM PST 23
Peak memory	223788 kb
Host	smart-02537fcf-57b6-43eb-bf26-b8429548004c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663104344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3663104344 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all.1820011207
Short name	T40
Test name
Test status
Simulation time	72965561151 ps
CPU time	825.42 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 01:04:55 PM PST 23
Peak memory	303876 kb
Host	smart-281236fc-28ce-4868-b156-45351260aadf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1820011207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1820011207 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/25.kmac_stress_all_with_rand_reset.759356607
Short name	T1137
Test name
Test status
Simulation time	247054014997 ps
CPU time	1262.24 seconds
Started	Dec 24 12:50:57 PM PST 23
Finished	Dec 24 01:12:03 PM PST 23
Peak memory	306256 kb
Host	smart-cff0dd73-8ad6-4289-ab8f-dae55f1de51c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=759356607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.759356607 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.4130943505
Short name	T600
Test name
Test status
Simulation time	1021409360 ps
CPU time	4.14 seconds
Started	Dec 24 12:50:28 PM PST 23
Finished	Dec 24 12:50:39 PM PST 23
Peak memory	215680 kb
Host	smart-6c0c0daa-8548-41d5-a4c1-83fdc551493a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130943505 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.4130943505 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.932939951
Short name	T1107
Test name
Test status
Simulation time	71018412 ps
CPU time	3.54 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 12:50:42 PM PST 23
Peak memory	215716 kb
Host	smart-fa59bab7-1478-4f8d-b31a-5c45653f8a39
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932939951 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 25.kmac_test_vectors_kmac_xof.932939951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.3659753463
Short name	T404
Test name
Test status
Simulation time	67302943663 ps
CPU time	1565.65 seconds
Started	Dec 24 12:50:32 PM PST 23
Finished	Dec 24 01:16:44 PM PST 23
Peak memory	392252 kb
Host	smart-a848365c-cceb-4a73-a30b-4aa02c5ccfae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3659753463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3659753463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.657398244
Short name	T455
Test name
Test status
Simulation time	387455065745 ps
CPU time	1761.15 seconds
Started	Dec 24 12:50:35 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	364860 kb
Host	smart-ce5255dc-5f2a-4750-b8b7-1088fcb4a9c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=657398244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.657398244 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.3951786195
Short name	T769
Test name
Test status
Simulation time	28796001363 ps
CPU time	1156.65 seconds
Started	Dec 24 12:50:47 PM PST 23
Finished	Dec 24 01:10:05 PM PST 23
Peak memory	339336 kb
Host	smart-a8e3e8b1-e5fe-4842-b6c9-3d526b181bd1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3951786195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3951786195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.650299488
Short name	T860
Test name
Test status
Simulation time	232267360858 ps
CPU time	1058.8 seconds
Started	Dec 24 12:50:33 PM PST 23
Finished	Dec 24 01:08:17 PM PST 23
Peak memory	294876 kb
Host	smart-3c7043b2-cd81-46da-8fff-c8703b9151a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=650299488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.650299488 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.2296698268
Short name	T923
Test name
Test status
Simulation time	180411516509 ps
CPU time	4622.71 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 02:07:42 PM PST 23
Peak memory	645892 kb
Host	smart-1720fef0-1ab5-464a-9348-c4b13b406bc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2296698268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2296698268 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.4285046289
Short name	T599
Test name
Test status
Simulation time	43176886179 ps
CPU time	3358.45 seconds
Started	Dec 24 12:50:34 PM PST 23
Finished	Dec 24 01:46:37 PM PST 23
Peak memory	560660 kb
Host	smart-a7ee5e3c-d57f-4991-82b4-f8c1e44cd533
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4285046289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.4285046289 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.1473056311
Short name	T722
Test name
Test status
Simulation time	18807751 ps
CPU time	0.9 seconds
Started	Dec 24 12:51:08 PM PST 23
Finished	Dec 24 12:51:17 PM PST 23
Peak memory	205088 kb
Host	smart-f508ac38-1354-42f3-b631-fdb5a2149223
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473056311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1473056311 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.1394213904
Short name	T1076
Test name
Test status
Simulation time	37858115038 ps
CPU time	229.31 seconds
Started	Dec 24 12:51:01 PM PST 23
Finished	Dec 24 12:55:01 PM PST 23
Peak memory	242732 kb
Host	smart-8168e1b1-7526-4566-81fa-8b735e4ad735
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394213904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1394213904 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.36371324
Short name	T610
Test name
Test status
Simulation time	32869752234 ps
CPU time	411.9 seconds
Started	Dec 24 12:50:53 PM PST 23
Finished	Dec 24 12:57:47 PM PST 23
Peak memory	228404 kb
Host	smart-92c587ef-ac90-4fb9-9ab1-c6c3eb3c5e32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36371324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.36371324 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.38865889
Short name	T442
Test name
Test status
Simulation time	36089051693 ps
CPU time	289.05 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 12:55:54 PM PST 23
Peak memory	246336 kb
Host	smart-38170813-9ab8-4523-9eac-b3433763af4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38865889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.38865889 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.4139437918
Short name	T463
Test name
Test status
Simulation time	63445557534 ps
CPU time	306.47 seconds
Started	Dec 24 12:50:54 PM PST 23
Finished	Dec 24 12:56:03 PM PST 23
Peak memory	254492 kb
Host	smart-7f81c5c0-449a-4a93-a9c8-3a9160a10df7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139437918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.4139437918 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.927811136
Short name	T477
Test name
Test status
Simulation time	2173025818 ps
CPU time	3.2 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:51:14 PM PST 23
Peak memory	207292 kb
Host	smart-bf46a1cc-4b37-4f0a-9319-2e222ed52773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927811136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.927811136 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.2580711784
Short name	T665
Test name
Test status
Simulation time	54564198 ps
CPU time	1.19 seconds
Started	Dec 24 12:51:03 PM PST 23
Finished	Dec 24 12:51:15 PM PST 23
Peak memory	216280 kb
Host	smart-83f276fc-8b70-4405-afae-313219cf2b29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580711784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2580711784 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.148269328
Short name	T894
Test name
Test status
Simulation time	37752624263 ps
CPU time	844.98 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 01:05:02 PM PST 23
Peak memory	296144 kb
Host	smart-3e772ac7-3a83-4ab0-a626-4fccc1dcbc4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148269328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an d_output.148269328 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.1611363997
Short name	T332
Test name
Test status
Simulation time	4024286565 ps
CPU time	75.37 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 12:52:20 PM PST 23
Peak memory	224260 kb
Host	smart-c1ef89f0-2b38-4d67-b691-8538a520fffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611363997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1611363997 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.2969939205
Short name	T416
Test name
Test status
Simulation time	10002917664 ps
CPU time	20.29 seconds
Started	Dec 24 12:50:53 PM PST 23
Finished	Dec 24 12:51:15 PM PST 23
Peak memory	219600 kb
Host	smart-8fe9f395-8010-46d8-b922-cd5c043a175c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969939205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2969939205 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.557954475
Short name	T618
Test name
Test status
Simulation time	211103621077 ps
CPU time	1518.64 seconds
Started	Dec 24 12:50:53 PM PST 23
Finished	Dec 24 01:16:13 PM PST 23
Peak memory	392960 kb
Host	smart-c8fd46b1-c850-4eb6-a718-97dfb2ce8a24
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=557954475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.557954475 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.2349527236
Short name	T508
Test name
Test status
Simulation time	43377703296 ps
CPU time	595.49 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 01:01:00 PM PST 23
Peak memory	257180 kb
Host	smart-751e7ebc-1820-424c-a852-6b9ec5074cf4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2349527236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.2349527236 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.3534702937
Short name	T432
Test name
Test status
Simulation time	780667948 ps
CPU time	5.26 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 12:51:03 PM PST 23
Peak memory	215796 kb
Host	smart-d0873758-eeca-476c-a7a3-a76c90fd217c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534702937 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.3534702937 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1113325604
Short name	T201
Test name
Test status
Simulation time	680889636 ps
CPU time	4.65 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 12:51:02 PM PST 23
Peak memory	208992 kb
Host	smart-d0d8ecec-a22c-466c-86b7-59919bc94c41
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113325604 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1113325604 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.1636281872
Short name	T822
Test name
Test status
Simulation time	105520379751 ps
CPU time	1589.7 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 01:17:27 PM PST 23
Peak memory	394260 kb
Host	smart-dcfc2a26-af12-402e-b8dc-142fecbc2e23
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1636281872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.1636281872 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.704747207
Short name	T409
Test name
Test status
Simulation time	240953622927 ps
CPU time	1672.2 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 01:18:49 PM PST 23
Peak memory	368616 kb
Host	smart-0f46f7b4-1008-47fb-ac83-993eafd9dcf3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=704747207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.704747207 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.2262180322
Short name	T1116
Test name
Test status
Simulation time	234363555598 ps
CPU time	1324.73 seconds
Started	Dec 24 12:50:57 PM PST 23
Finished	Dec 24 01:13:06 PM PST 23
Peak memory	334916 kb
Host	smart-0fccff4e-a0f4-47cc-9c5f-6ee2ebfacc6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2262180322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.2262180322 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.1308012832
Short name	T1118
Test name
Test status
Simulation time	9968656406 ps
CPU time	808.19 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 01:04:30 PM PST 23
Peak memory	295976 kb
Host	smart-5bc86cf7-aa1d-425d-8209-e6bf6b23c261
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1308012832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1308012832 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.1638838094
Short name	T957
Test name
Test status
Simulation time	1064590133977 ps
CPU time	5637.56 seconds
Started	Dec 24 12:51:07 PM PST 23
Finished	Dec 24 02:25:14 PM PST 23
Peak memory	646180 kb
Host	smart-b591984e-adce-4fbb-8b07-d6afbd22c81a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1638838094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1638838094 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.3479507132
Short name	T250
Test name
Test status
Simulation time	44827523691 ps
CPU time	3478.67 seconds
Started	Dec 24 12:50:57 PM PST 23
Finished	Dec 24 01:49:01 PM PST 23
Peak memory	556656 kb
Host	smart-bbb61f98-47d7-4d77-b22f-5942c943009b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3479507132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3479507132 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.2613119569
Short name	T43
Test name
Test status
Simulation time	21215554 ps
CPU time	0.77 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 12:51:03 PM PST 23
Peak memory	205056 kb
Host	smart-83f30d25-24af-4d4a-84e1-5fb905d8a07e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613119569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2613119569 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.226170883
Short name	T492
Test name
Test status
Simulation time	4137169754 ps
CPU time	275.17 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:55:45 PM PST 23
Peak memory	248192 kb
Host	smart-22b293cf-18be-4745-99aa-275698e68aea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226170883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.226170883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.112124285
Short name	T796
Test name
Test status
Simulation time	96605347573 ps
CPU time	428.55 seconds
Started	Dec 24 12:50:56 PM PST 23
Finished	Dec 24 12:58:08 PM PST 23
Peak memory	226688 kb
Host	smart-a6214dc9-7cb8-4363-b738-f44008190e7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112124285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.112124285 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.4133696850
Short name	T818
Test name
Test status
Simulation time	33954714852 ps
CPU time	141.24 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:53:32 PM PST 23
Peak memory	233876 kb
Host	smart-39cf1e99-37f2-479b-ac14-371dc3e3b88a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133696850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4133696850 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.3109860863
Short name	T33
Test name
Test status
Simulation time	12448717147 ps
CPU time	319.13 seconds
Started	Dec 24 12:50:56 PM PST 23
Finished	Dec 24 12:56:18 PM PST 23
Peak memory	256476 kb
Host	smart-64825048-910a-4af1-89f6-b20643efc4ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109860863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3109860863 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.1838853939
Short name	T25
Test name
Test status
Simulation time	2130397188 ps
CPU time	5.14 seconds
Started	Dec 24 12:50:52 PM PST 23
Finished	Dec 24 12:50:59 PM PST 23
Peak memory	207232 kb
Host	smart-f982b6dd-348c-4175-9644-1bb8d10a7dd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838853939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1838853939 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.798810286
Short name	T10
Test name
Test status
Simulation time	37286501 ps
CPU time	1.29 seconds
Started	Dec 24 12:50:57 PM PST 23
Finished	Dec 24 12:51:02 PM PST 23
Peak memory	216644 kb
Host	smart-65865791-8c9e-4db7-a82f-6a146b3e1e44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798810286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.798810286 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.2178592562
Short name	T204
Test name
Test status
Simulation time	73315356806 ps
CPU time	2186.86 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 01:27:29 PM PST 23
Peak memory	428192 kb
Host	smart-54eddae0-35a0-4404-bb39-c3019f27c149
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178592562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.2178592562 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.200554812
Short name	T503
Test name
Test status
Simulation time	10412485286 ps
CPU time	212.89 seconds
Started	Dec 24 12:51:03 PM PST 23
Finished	Dec 24 12:54:47 PM PST 23
Peak memory	235356 kb
Host	smart-55dbaf14-1acf-493c-944a-e94df4769566
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200554812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.200554812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.1179687463
Short name	T700
Test name
Test status
Simulation time	4379910576 ps
CPU time	67.9 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 12:52:11 PM PST 23
Peak memory	216832 kb
Host	smart-c0280c2c-b827-45a4-890d-289ef6facc01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179687463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1179687463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all.1762926983
Short name	T520
Test name
Test status
Simulation time	8957444888 ps
CPU time	661.76 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 01:01:58 PM PST 23
Peak memory	318836 kb
Host	smart-74bd5cef-fb18-4388-b4c9-8306cc3bf874
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1762926983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1762926983 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.3377771186
Short name	T1029
Test name
Test status
Simulation time	1096447805 ps
CPU time	4.74 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 12:51:08 PM PST 23
Peak memory	215680 kb
Host	smart-4aa24085-f7df-4409-b31b-39e2bb8ae43c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377771186 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.3377771186 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2485374050
Short name	T752
Test name
Test status
Simulation time	67128718 ps
CPU time	3.92 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 12:51:08 PM PST 23
Peak memory	215588 kb
Host	smart-11ffde3d-3146-49f2-a5f0-632cad6a5a82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485374050 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2485374050 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.56924211
Short name	T609
Test name
Test status
Simulation time	259141255697 ps
CPU time	1833.14 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 01:21:36 PM PST 23
Peak memory	391160 kb
Host	smart-db9e944b-1866-4b1c-a689-837db136ec34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=56924211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.56924211 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.1768379002
Short name	T490
Test name
Test status
Simulation time	614430583800 ps
CPU time	1676.76 seconds
Started	Dec 24 12:50:58 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	375720 kb
Host	smart-b357a558-7997-4355-8863-af9a657119ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1768379002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1768379002 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.372009175
Short name	T517
Test name
Test status
Simulation time	133130645547 ps
CPU time	1251.06 seconds
Started	Dec 24 12:50:56 PM PST 23
Finished	Dec 24 01:11:50 PM PST 23
Peak memory	332604 kb
Host	smart-14e5d716-5091-480d-8cc1-ee4021311cee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=372009175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.372009175 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.2248105084
Short name	T387
Test name
Test status
Simulation time	33215163098 ps
CPU time	926.01 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 01:06:32 PM PST 23
Peak memory	295700 kb
Host	smart-d182afe9-08e1-4799-a265-af77fbac3424
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2248105084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2248105084 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.3264790856
Short name	T782
Test name
Test status
Simulation time	1038253463400 ps
CPU time	5539.09 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 02:23:25 PM PST 23
Peak memory	661464 kb
Host	smart-5f948327-a6c2-4c3e-861d-7c1029ca34ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3264790856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3264790856 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.3811710642
Short name	T975
Test name
Test status
Simulation time	1032350240736 ps
CPU time	4167.9 seconds
Started	Dec 24 12:50:57 PM PST 23
Finished	Dec 24 02:00:29 PM PST 23
Peak memory	555952 kb
Host	smart-86849ebb-0884-4e73-b7b1-641171a7a514
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3811710642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3811710642 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.732312015
Short name	T328
Test name
Test status
Simulation time	15719510 ps
CPU time	0.78 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 12:51:28 PM PST 23
Peak memory	205144 kb
Host	smart-6c5c9618-5616-4aec-952d-844e3c6bfe4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732312015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.732312015 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.493787140
Short name	T382
Test name
Test status
Simulation time	7546477370 ps
CPU time	182.91 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 12:54:08 PM PST 23
Peak memory	237844 kb
Host	smart-7a337bcf-a975-4118-b80e-0cd7df8d728f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493787140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.493787140 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.1126747631
Short name	T970
Test name
Test status
Simulation time	6188117808 ps
CPU time	87.07 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:52:37 PM PST 23
Peak memory	221092 kb
Host	smart-c90735bb-d1d7-4955-bd9f-af57ad1042c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126747631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1126747631 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.216834844
Short name	T260
Test name
Test status
Simulation time	52309809646 ps
CPU time	210.92 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:54:42 PM PST 23
Peak memory	237404 kb
Host	smart-e3215399-f79d-4962-8e3b-32cf94b5ef8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216834844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.216834844 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_error.3567807164
Short name	T899
Test name
Test status
Simulation time	152921390479 ps
CPU time	313.28 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 12:56:39 PM PST 23
Peak memory	256592 kb
Host	smart-82faa73d-577b-4e2f-895c-fe9a42cb88fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567807164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3567807164 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.3507328448
Short name	T892
Test name
Test status
Simulation time	2326473021 ps
CPU time	3.81 seconds
Started	Dec 24 12:51:14 PM PST 23
Finished	Dec 24 12:51:25 PM PST 23
Peak memory	207540 kb
Host	smart-a7777350-2cf8-42c6-a0d0-ac7c0e6dbb7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507328448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3507328448 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.4044903838
Short name	T944
Test name
Test status
Simulation time	114399877 ps
CPU time	1.26 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:51:24 PM PST 23
Peak memory	215732 kb
Host	smart-d36d4701-1e98-4e82-86d6-cfdffe23e835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044903838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4044903838 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.855555409
Short name	T670
Test name
Test status
Simulation time	37400564065 ps
CPU time	1146.14 seconds
Started	Dec 24 12:51:01 PM PST 23
Finished	Dec 24 01:10:18 PM PST 23
Peak memory	326620 kb
Host	smart-f4b2d376-22a8-42c4-86eb-56885c37a1b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855555409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an d_output.855555409 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.2115053222
Short name	T821
Test name
Test status
Simulation time	1072491827 ps
CPU time	82.7 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 12:52:21 PM PST 23
Peak memory	224324 kb
Host	smart-4cb941d1-9875-4fd7-ab8c-31b712211c41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115053222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2115053222 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.1730408079
Short name	T716
Test name
Test status
Simulation time	3149489878 ps
CPU time	50.94 seconds
Started	Dec 24 12:51:01 PM PST 23
Finished	Dec 24 12:52:03 PM PST 23
Peak memory	219804 kb
Host	smart-fa7bbc86-033f-47dc-9f9c-e4b97f6db3a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730408079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1730408079 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.2135419030
Short name	T42
Test name
Test status
Simulation time	904515137066 ps
CPU time	1483.32 seconds
Started	Dec 24 12:51:25 PM PST 23
Finished	Dec 24 01:16:12 PM PST 23
Peak memory	400952 kb
Host	smart-db9661aa-dc65-4427-a0c4-c2042e6bf124
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2135419030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2135419030 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_stress_all_with_rand_reset.166623355
Short name	T964
Test name
Test status
Simulation time	32564497126 ps
CPU time	837.43 seconds
Started	Dec 24 12:51:14 PM PST 23
Finished	Dec 24 01:05:19 PM PST 23
Peak memory	305004 kb
Host	smart-cbf5fe72-0fd7-459e-8422-7282977fea4f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=166623355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all_with_rand_reset.166623355 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.2775223568
Short name	T377
Test name
Test status
Simulation time	1048299811 ps
CPU time	5.2 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 12:51:15 PM PST 23
Peak memory	215652 kb
Host	smart-0f799c49-820d-42aa-9ceb-050b49637d47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775223568 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.2775223568 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.848824500
Short name	T190
Test name
Test status
Simulation time	995818405 ps
CPU time	4.51 seconds
Started	Dec 24 12:51:03 PM PST 23
Finished	Dec 24 12:51:18 PM PST 23
Peak memory	215496 kb
Host	smart-9bb95aee-c14a-4d41-863a-d6c66f1ca20a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848824500 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 28.kmac_test_vectors_kmac_xof.848824500 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.1252662621
Short name	T192
Test name
Test status
Simulation time	328441246673 ps
CPU time	1809.59 seconds
Started	Dec 24 12:50:56 PM PST 23
Finished	Dec 24 01:21:08 PM PST 23
Peak memory	375376 kb
Host	smart-c1f36c49-6382-4de9-8500-be8a4a1f8351
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1252662621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1252662621 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.3420711737
Short name	T998
Test name
Test status
Simulation time	385601431043 ps
CPU time	1936.67 seconds
Started	Dec 24 12:51:00 PM PST 23
Finished	Dec 24 01:23:28 PM PST 23
Peak memory	377152 kb
Host	smart-3e171671-893b-4e0b-af25-066439993a33
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3420711737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3420711737 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.431696194
Short name	T929
Test name
Test status
Simulation time	98120672469 ps
CPU time	1182.13 seconds
Started	Dec 24 12:50:55 PM PST 23
Finished	Dec 24 01:10:39 PM PST 23
Peak memory	336692 kb
Host	smart-42ace560-0bde-4352-823c-d38af0e94d06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=431696194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.431696194 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.1559064688
Short name	T884
Test name
Test status
Simulation time	219891673504 ps
CPU time	994.35 seconds
Started	Dec 24 12:50:59 PM PST 23
Finished	Dec 24 01:07:39 PM PST 23
Peak memory	293152 kb
Host	smart-2574fd42-87f3-486a-a56d-5dc955922a7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1559064688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1559064688 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.3309422318
Short name	T518
Test name
Test status
Simulation time	179467101287 ps
CPU time	4737.38 seconds
Started	Dec 24 12:51:06 PM PST 23
Finished	Dec 24 02:10:14 PM PST 23
Peak memory	643016 kb
Host	smart-95464f12-ccba-4779-885d-8838d0eef158
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3309422318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3309422318 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.3847298535
Short name	T1057
Test name
Test status
Simulation time	481641646747 ps
CPU time	4485.65 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 02:06:10 PM PST 23
Peak memory	561080 kb
Host	smart-a958842b-68ec-4271-b299-73df66065fca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3847298535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3847298535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.3212555256
Short name	T421
Test name
Test status
Simulation time	28154934 ps
CPU time	0.79 seconds
Started	Dec 24 12:51:23 PM PST 23
Finished	Dec 24 12:51:29 PM PST 23
Peak memory	205212 kb
Host	smart-7f1cdf1f-9d71-463a-9ad0-69c343071c18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212555256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3212555256 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.4130320389
Short name	T893
Test name
Test status
Simulation time	42445671898 ps
CPU time	237.44 seconds
Started	Dec 24 12:51:12 PM PST 23
Finished	Dec 24 12:55:15 PM PST 23
Peak memory	239716 kb
Host	smart-7c2a07b9-855f-4e3a-b1da-4941e1ed9814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130320389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.4130320389 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.2254260178
Short name	T1094
Test name
Test status
Simulation time	43803710941 ps
CPU time	364.08 seconds
Started	Dec 24 12:51:20 PM PST 23
Finished	Dec 24 12:57:30 PM PST 23
Peak memory	227236 kb
Host	smart-eeb1d01e-a06c-460b-bda8-94f40d578933
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254260178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2254260178 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.4262514665
Short name	T1089
Test name
Test status
Simulation time	949507257 ps
CPU time	22.39 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:51:45 PM PST 23
Peak memory	219212 kb
Host	smart-cb58126b-c120-4abd-abfa-710cebf703bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262514665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.4262514665 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.533975833
Short name	T379
Test name
Test status
Simulation time	10931002129 ps
CPU time	285.17 seconds
Started	Dec 24 12:51:24 PM PST 23
Finished	Dec 24 12:56:14 PM PST 23
Peak memory	256680 kb
Host	smart-3915fcab-8b82-44d9-b06a-1fdda8571e96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533975833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.533975833 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.4011028443
Short name	T912
Test name
Test status
Simulation time	1373341099 ps
CPU time	6.35 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 12:51:33 PM PST 23
Peak memory	207292 kb
Host	smart-813fe6df-0dc6-4eef-9ba7-bbc2157a6082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011028443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.4011028443 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.33402425
Short name	T1132
Test name
Test status
Simulation time	149634868 ps
CPU time	1.3 seconds
Started	Dec 24 12:51:14 PM PST 23
Finished	Dec 24 12:51:22 PM PST 23
Peak memory	215624 kb
Host	smart-2a791430-b9b1-4c75-9c70-70fa0c546e20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33402425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.33402425 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.1850386449
Short name	T738
Test name
Test status
Simulation time	20628479943 ps
CPU time	569 seconds
Started	Dec 24 12:51:12 PM PST 23
Finished	Dec 24 01:00:46 PM PST 23
Peak memory	273776 kb
Host	smart-274a0b5a-13e8-4447-b862-b5bc4f81b749
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850386449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.1850386449 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.1770843869
Short name	T384
Test name
Test status
Simulation time	139595365323 ps
CPU time	182.18 seconds
Started	Dec 24 12:51:22 PM PST 23
Finished	Dec 24 12:54:30 PM PST 23
Peak memory	229600 kb
Host	smart-3d5073ed-7734-452f-90fe-d63cf0e8e043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770843869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1770843869 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.187734001
Short name	T412
Test name
Test status
Simulation time	3127591165 ps
CPU time	14.35 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 12:51:39 PM PST 23
Peak memory	219164 kb
Host	smart-bb9f2ec7-0f92-4bd6-82f3-a42c4e1cb6e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187734001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.187734001 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.2633680545
Short name	T855
Test name
Test status
Simulation time	30370422591 ps
CPU time	600.68 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 01:01:26 PM PST 23
Peak memory	317760 kb
Host	smart-03d2d937-a243-40b5-bd31-3b7db45675b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2633680545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2633680545 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.2929672358
Short name	T624
Test name
Test status
Simulation time	545394453 ps
CPU time	4.41 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:51:27 PM PST 23
Peak memory	215600 kb
Host	smart-3ea1ec78-41da-431b-8c0d-8b129f785280
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929672358 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.2929672358 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.1703555817
Short name	T307
Test name
Test status
Simulation time	176118223 ps
CPU time	4.5 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 12:51:28 PM PST 23
Peak memory	215704 kb
Host	smart-95c4fdc9-777e-4a94-8406-92db831b8ccc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703555817 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.1703555817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.3677853977
Short name	T876
Test name
Test status
Simulation time	18463652248 ps
CPU time	1576.25 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 01:17:39 PM PST 23
Peak memory	376832 kb
Host	smart-956b97e9-7fe6-43ec-8c75-7d17787d07f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3677853977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3677853977 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.3895720306
Short name	T73
Test name
Test status
Simulation time	18057201171 ps
CPU time	1474.37 seconds
Started	Dec 24 12:51:13 PM PST 23
Finished	Dec 24 01:15:54 PM PST 23
Peak memory	375932 kb
Host	smart-5513cb3a-777e-4116-b419-85f0abfccf59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3895720306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3895720306 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.2986604805
Short name	T875
Test name
Test status
Simulation time	51219759636 ps
CPU time	1136.56 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 01:10:24 PM PST 23
Peak memory	326732 kb
Host	smart-3c4346e4-4912-4ac2-98d4-9eb677520e0d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2986604805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2986604805 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.2989737406
Short name	T827
Test name
Test status
Simulation time	168822153975 ps
CPU time	927.11 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 01:06:53 PM PST 23
Peak memory	294376 kb
Host	smart-95a2b644-5232-47f9-a59d-d15550e13286
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2989737406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2989737406 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.3070851624
Short name	T705
Test name
Test status
Simulation time	100919491625 ps
CPU time	4064.14 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 01:59:10 PM PST 23
Peak memory	642112 kb
Host	smart-145db2d8-91a0-46f9-ad60-db08b3da5afe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3070851624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3070851624 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.3507486552
Short name	T605
Test name
Test status
Simulation time	84076329261 ps
CPU time	3355.48 seconds
Started	Dec 24 12:51:15 PM PST 23
Finished	Dec 24 01:47:18 PM PST 23
Peak memory	569748 kb
Host	smart-b371a757-c226-49c8-8d91-e6ff7f98efdb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3507486552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3507486552 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.1600524486
Short name	T281
Test name
Test status
Simulation time	17010695 ps
CPU time	0.8 seconds
Started	Dec 24 12:48:40 PM PST 23
Finished	Dec 24 12:48:42 PM PST 23
Peak memory	205048 kb
Host	smart-67338f6e-e80b-4d2b-8946-4bc0bb33a948
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600524486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1600524486 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.4150019446
Short name	T806
Test name
Test status
Simulation time	542084158 ps
CPU time	10.04 seconds
Started	Dec 24 12:48:27 PM PST 23
Finished	Dec 24 12:48:39 PM PST 23
Peak memory	221116 kb
Host	smart-07f983f6-cb4a-412d-aaf5-44e56a334243
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150019446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.4150019446 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.1114380252
Short name	T974
Test name
Test status
Simulation time	10004846607 ps
CPU time	173.79 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 12:51:26 PM PST 23
Peak memory	236996 kb
Host	smart-e511debd-ed38-48df-a93e-e41b9b324346
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114380252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1114380252 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.1066202107
Short name	T460
Test name
Test status
Simulation time	102010414791 ps
CPU time	331.38 seconds
Started	Dec 24 12:48:38 PM PST 23
Finished	Dec 24 12:54:11 PM PST 23
Peak memory	225268 kb
Host	smart-98bd265f-e01c-414b-bfbb-2196958de921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066202107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1066202107 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.3325447164
Short name	T922
Test name
Test status
Simulation time	1399893717 ps
CPU time	25.86 seconds
Started	Dec 24 12:48:52 PM PST 23
Finished	Dec 24 12:49:20 PM PST 23
Peak memory	223592 kb
Host	smart-7b9e73e1-68fd-468b-bd13-eab43f369686
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3325447164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3325447164 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.293153742
Short name	T739
Test name
Test status
Simulation time	161548584 ps
CPU time	5.66 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:48:43 PM PST 23
Peak memory	223592 kb
Host	smart-1b3c7087-cbe5-43c3-8468-728015cefd47
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=293153742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.293153742 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.3673657774
Short name	T736
Test name
Test status
Simulation time	40281030303 ps
CPU time	43.34 seconds
Started	Dec 24 12:48:47 PM PST 23
Finished	Dec 24 12:49:31 PM PST 23
Peak memory	216888 kb
Host	smart-0f8bb231-01cb-4bb3-8922-f6ba3aa2b115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673657774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3673657774 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.1817252253
Short name	T999
Test name
Test status
Simulation time	17251072849 ps
CPU time	273.11 seconds
Started	Dec 24 12:48:37 PM PST 23
Finished	Dec 24 12:53:12 PM PST 23
Peak memory	245836 kb
Host	smart-6e67bedb-37bd-4213-a11c-fccccea31652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817252253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1817252253 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.2635941511
Short name	T812
Test name
Test status
Simulation time	13913207597 ps
CPU time	367.85 seconds
Started	Dec 24 12:48:25 PM PST 23
Finished	Dec 24 12:54:34 PM PST 23
Peak memory	253020 kb
Host	smart-47388540-c2d6-4846-a7cd-73900d038502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635941511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2635941511 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.2840372356
Short name	T982
Test name
Test status
Simulation time	1266479763 ps
CPU time	2.24 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 12:48:38 PM PST 23
Peak memory	207088 kb
Host	smart-93568477-b1ed-4a15-8176-dd520725182f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840372356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2840372356 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.3694101268
Short name	T943
Test name
Test status
Simulation time	291471937 ps
CPU time	2.06 seconds
Started	Dec 24 12:48:53 PM PST 23
Finished	Dec 24 12:48:57 PM PST 23
Peak memory	219128 kb
Host	smart-63aecb9f-58be-493d-8d36-7e8ce535c90f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694101268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3694101268 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.1640063991
Short name	T207
Test name
Test status
Simulation time	11568927062 ps
CPU time	184.04 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 12:51:30 PM PST 23
Peak memory	236944 kb
Host	smart-b27f239e-ab6e-4e33-9ece-deece8369062
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640063991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.1640063991 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.3280657750
Short name	T1027
Test name
Test status
Simulation time	7402209206 ps
CPU time	176.52 seconds
Started	Dec 24 12:48:26 PM PST 23
Finished	Dec 24 12:51:24 PM PST 23
Peak memory	237196 kb
Host	smart-06fb7c3d-6aa5-49ed-b6f2-f8ed7042fae5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280657750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3280657750 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.2863903869
Short name	T11
Test name
Test status
Simulation time	32169487887 ps
CPU time	60.09 seconds
Started	Dec 24 12:48:32 PM PST 23
Finished	Dec 24 12:49:34 PM PST 23
Peak memory	257160 kb
Host	smart-2aa453e1-da40-40d8-9dc7-092e4ac2d6de
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863903869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2863903869 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.1686935614
Short name	T46
Test name
Test status
Simulation time	4166526341 ps
CPU time	320.06 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 12:54:01 PM PST 23
Peak memory	246476 kb
Host	smart-03da6f0b-3dc8-4b59-bbf8-5f640deb9ae0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686935614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1686935614 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.2049796816
Short name	T570
Test name
Test status
Simulation time	11156319881 ps
CPU time	61.75 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:49:57 PM PST 23
Peak memory	220444 kb
Host	smart-983aa7ad-d953-4e12-86a6-0c02519807ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049796816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2049796816 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.3635369957
Short name	T939
Test name
Test status
Simulation time	28120992648 ps
CPU time	1527.01 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 01:14:04 PM PST 23
Peak memory	436860 kb
Host	smart-d285e0d7-1167-4056-9aef-d3df1b56aecc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3635369957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3635369957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.2062825578
Short name	T707
Test name
Test status
Simulation time	141501513286 ps
CPU time	793.8 seconds
Started	Dec 24 12:48:26 PM PST 23
Finished	Dec 24 01:01:42 PM PST 23
Peak memory	265052 kb
Host	smart-2c5d03f4-49e5-4ebc-91df-dd5294b2f2a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2062825578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.2062825578 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.1479055973
Short name	T955
Test name
Test status
Simulation time	243840774 ps
CPU time	4.84 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:48:42 PM PST 23
Peak memory	215604 kb
Host	smart-355d2d44-e144-4c63-8e46-0e64a74e35f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479055973 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.1479055973 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2674918495
Short name	T832
Test name
Test status
Simulation time	184680034 ps
CPU time	4.84 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 12:48:47 PM PST 23
Peak memory	215680 kb
Host	smart-05c21c5b-f041-40c7-ad2a-4277ef5edddb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674918495 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2674918495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.4277520067
Short name	T678
Test name
Test status
Simulation time	334553199085 ps
CPU time	1844.61 seconds
Started	Dec 24 12:48:25 PM PST 23
Finished	Dec 24 01:19:11 PM PST 23
Peak memory	388984 kb
Host	smart-6873f77f-a1e0-4bdc-9527-6fa37793214c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4277520067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.4277520067 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.1878612299
Short name	T530
Test name
Test status
Simulation time	259023805961 ps
CPU time	1754.96 seconds
Started	Dec 24 12:48:50 PM PST 23
Finished	Dec 24 01:18:06 PM PST 23
Peak memory	387632 kb
Host	smart-81779ec0-c821-4f93-abcb-d51c7a1ba559
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1878612299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1878612299 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.2764203614
Short name	T187
Test name
Test status
Simulation time	273653318467 ps
CPU time	1337.11 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 01:10:57 PM PST 23
Peak memory	331796 kb
Host	smart-12510333-ad1e-4557-b9b8-9990355663fc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2764203614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2764203614 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.2561644908
Short name	T435
Test name
Test status
Simulation time	40538081997 ps
CPU time	762.14 seconds
Started	Dec 24 12:48:32 PM PST 23
Finished	Dec 24 01:01:15 PM PST 23
Peak memory	291532 kb
Host	smart-ad8ab79b-7267-4079-ad1e-976f10fcbe1f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2561644908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2561644908 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.262888081
Short name	T525
Test name
Test status
Simulation time	869171322198 ps
CPU time	4934.87 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 02:10:41 PM PST 23
Peak memory	660716 kb
Host	smart-4a11775b-1a26-4dde-adbc-a26a93ab673d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=262888081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.262888081 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.2346795921
Short name	T45
Test name
Test status
Simulation time	288143173048 ps
CPU time	3847.8 seconds
Started	Dec 24 12:48:24 PM PST 23
Finished	Dec 24 01:52:34 PM PST 23
Peak memory	553432 kb
Host	smart-db61b1d7-cc8a-45a6-a3d2-7d8db8c54c47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2346795921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2346795921 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.293027630
Short name	T1106
Test name
Test status
Simulation time	27360730 ps
CPU time	0.81 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 12:51:26 PM PST 23
Peak memory	205052 kb
Host	smart-026a8073-5015-4d72-882e-dc66a258bc29
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293027630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.293027630 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.1302165580
Short name	T603
Test name
Test status
Simulation time	9694147307 ps
CPU time	183.69 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:54:27 PM PST 23
Peak memory	234396 kb
Host	smart-7ce66315-8c55-4523-b61b-8be326f15ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302165580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1302165580 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.3433118694
Short name	T687
Test name
Test status
Simulation time	43412366486 ps
CPU time	696.77 seconds
Started	Dec 24 12:51:15 PM PST 23
Finished	Dec 24 01:02:59 PM PST 23
Peak memory	231520 kb
Host	smart-0530cfdb-f747-4e62-9156-8cea2c4f059f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433118694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3433118694 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.1189179537
Short name	T234
Test name
Test status
Simulation time	50882876474 ps
CPU time	225.17 seconds
Started	Dec 24 12:51:12 PM PST 23
Finished	Dec 24 12:55:03 PM PST 23
Peak memory	240988 kb
Host	smart-8891770f-c97e-4d5a-97fd-882d63573ca8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189179537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1189179537 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.897217113
Short name	T268
Test name
Test status
Simulation time	12286812282 ps
CPU time	320.43 seconds
Started	Dec 24 12:51:23 PM PST 23
Finished	Dec 24 12:56:49 PM PST 23
Peak memory	256648 kb
Host	smart-39cc79cf-3d20-4581-aa80-0f08592966cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897217113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.897217113 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.2131091994
Short name	T877
Test name
Test status
Simulation time	1495748674 ps
CPU time	4.56 seconds
Started	Dec 24 12:51:15 PM PST 23
Finished	Dec 24 12:51:27 PM PST 23
Peak memory	207272 kb
Host	smart-f557dabe-baf6-4fdc-a13e-ca206320eeca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131091994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2131091994 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.87996055
Short name	T620
Test name
Test status
Simulation time	117491440 ps
CPU time	1.27 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 12:51:25 PM PST 23
Peak memory	220660 kb
Host	smart-e11edf49-ef10-4b71-9f7a-5965e7140754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87996055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.87996055 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.351997195
Short name	T640
Test name
Test status
Simulation time	36047606731 ps
CPU time	847.92 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 01:05:31 PM PST 23
Peak memory	312240 kb
Host	smart-dd89ed48-2df0-4a14-9f17-e839a7ffd899
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351997195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an d_output.351997195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.3272382756
Short name	T407
Test name
Test status
Simulation time	3308538937 ps
CPU time	255.53 seconds
Started	Dec 24 12:51:13 PM PST 23
Finished	Dec 24 12:55:34 PM PST 23
Peak memory	244136 kb
Host	smart-96d9e61c-8c9f-4e17-b44c-43561815a5fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272382756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3272382756 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.363226833
Short name	T723
Test name
Test status
Simulation time	1035880052 ps
CPU time	49.89 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 12:52:17 PM PST 23
Peak memory	221592 kb
Host	smart-1a254366-037c-489b-a1cc-995649920c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363226833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.363226833 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.1216537012
Short name	T725
Test name
Test status
Simulation time	2814708888 ps
CPU time	199.69 seconds
Started	Dec 24 12:51:15 PM PST 23
Finished	Dec 24 12:54:42 PM PST 23
Peak memory	256628 kb
Host	smart-e9f50a32-d527-4b6f-a220-c26a2a46914e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1216537012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1216537012 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_stress_all_with_rand_reset.3790377008
Short name	T223
Test name
Test status
Simulation time	155942767850 ps
CPU time	909.01 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 01:06:35 PM PST 23
Peak memory	272944 kb
Host	smart-8fb5680a-7f2a-4396-a528-b3f703e3daf9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3790377008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.3790377008 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.1215747372
Short name	T1145
Test name
Test status
Simulation time	165129379 ps
CPU time	4.2 seconds
Started	Dec 24 12:51:14 PM PST 23
Finished	Dec 24 12:51:24 PM PST 23
Peak memory	215644 kb
Host	smart-67a63e13-490e-49c4-9c17-9fbd95e29ede
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215747372 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.1215747372 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2470673920
Short name	T414
Test name
Test status
Simulation time	244683143 ps
CPU time	4.42 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:51:27 PM PST 23
Peak memory	208212 kb
Host	smart-19f80fef-4c6f-48fb-864c-f873d7be34da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470673920 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2470673920 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.1972777629
Short name	T523
Test name
Test status
Simulation time	19427368043 ps
CPU time	1586.23 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 01:17:49 PM PST 23
Peak memory	396056 kb
Host	smart-1b5707da-efed-4698-a1dc-1857e924f315
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1972777629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.1972777629 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.2032758409
Short name	T335
Test name
Test status
Simulation time	35939484710 ps
CPU time	1445.85 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 01:15:31 PM PST 23
Peak memory	371520 kb
Host	smart-6878b4a2-4abb-4704-866e-2cb3584b08a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2032758409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2032758409 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.2996285516
Short name	T575
Test name
Test status
Simulation time	264239247519 ps
CPU time	1385.24 seconds
Started	Dec 24 12:51:14 PM PST 23
Finished	Dec 24 01:14:26 PM PST 23
Peak memory	327672 kb
Host	smart-39e27761-5ccc-440a-bb0c-53fef6eee7e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2996285516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2996285516 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.951781205
Short name	T904
Test name
Test status
Simulation time	54961357727 ps
CPU time	957.16 seconds
Started	Dec 24 12:51:13 PM PST 23
Finished	Dec 24 01:07:17 PM PST 23
Peak memory	294876 kb
Host	smart-3eef09ff-82f0-4e80-bfd8-e8c197ae3052
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=951781205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.951781205 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.2259226995
Short name	T284
Test name
Test status
Simulation time	459369099687 ps
CPU time	4795.03 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 02:11:21 PM PST 23
Peak memory	639992 kb
Host	smart-cfe2af53-e33a-4a58-a9be-324e95a7066d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2259226995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2259226995 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.3778711363
Short name	T984
Test name
Test status
Simulation time	864550656906 ps
CPU time	4133.05 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 02:00:17 PM PST 23
Peak memory	559228 kb
Host	smart-5e8eef53-3ea8-439a-820e-48a5ba63c257
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3778711363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3778711363 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.710081272
Short name	T737
Test name
Test status
Simulation time	14251119 ps
CPU time	0.74 seconds
Started	Dec 24 12:51:24 PM PST 23
Finished	Dec 24 12:51:30 PM PST 23
Peak memory	205168 kb
Host	smart-14839af8-782a-4c04-8768-e857edcf4b87
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710081272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.710081272 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.1450731942
Short name	T474
Test name
Test status
Simulation time	6486471038 ps
CPU time	59.02 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 12:52:25 PM PST 23
Peak memory	224372 kb
Host	smart-0656afde-3dcb-4088-bf77-adcc9a95e92a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450731942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1450731942 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.2127170836
Short name	T727
Test name
Test status
Simulation time	11840353240 ps
CPU time	226.45 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 12:55:10 PM PST 23
Peak memory	226072 kb
Host	smart-fe983b65-aa13-4cd0-a1e5-f794d7aee6c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127170836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2127170836 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.490095418
Short name	T258
Test name
Test status
Simulation time	821306959 ps
CPU time	13.81 seconds
Started	Dec 24 12:51:20 PM PST 23
Finished	Dec 24 12:51:40 PM PST 23
Peak memory	220540 kb
Host	smart-a889f223-cb5e-4e1d-82e5-e2a47e0bdc01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490095418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.490095418 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.4240566807
Short name	T864
Test name
Test status
Simulation time	61914653999 ps
CPU time	304.39 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 12:56:32 PM PST 23
Peak memory	255140 kb
Host	smart-3e49c1b9-6a82-4fea-b504-9ba81eeebd0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240566807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4240566807 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.2478610501
Short name	T787
Test name
Test status
Simulation time	88806747 ps
CPU time	1.06 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 12:51:34 PM PST 23
Peak memory	205592 kb
Host	smart-12a0a45f-a583-4b6e-9ea6-30a9bcfb1dd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478610501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2478610501 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.2617405946
Short name	T595
Test name
Test status
Simulation time	29253185 ps
CPU time	1.21 seconds
Started	Dec 24 12:51:26 PM PST 23
Finished	Dec 24 12:51:31 PM PST 23
Peak memory	215564 kb
Host	smart-e4588c27-5482-4879-aff9-1c7d21a1f1f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617405946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2617405946 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.582462189
Short name	T611
Test name
Test status
Simulation time	311123190127 ps
CPU time	2378.69 seconds
Started	Dec 24 12:51:23 PM PST 23
Finished	Dec 24 01:31:07 PM PST 23
Peak memory	446388 kb
Host	smart-8699cd0e-5ec0-4f52-abec-005ebd79fe86
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582462189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an d_output.582462189 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.3104259414
Short name	T1140
Test name
Test status
Simulation time	33168705719 ps
CPU time	192.16 seconds
Started	Dec 24 12:51:13 PM PST 23
Finished	Dec 24 12:54:32 PM PST 23
Peak memory	236912 kb
Host	smart-d5bbed0a-8d41-4bda-9d08-8e999e3679ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104259414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3104259414 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.3638435831
Short name	T521
Test name
Test status
Simulation time	11294799113 ps
CPU time	55.66 seconds
Started	Dec 24 12:51:17 PM PST 23
Finished	Dec 24 12:52:20 PM PST 23
Peak memory	221624 kb
Host	smart-413638c0-351d-4143-b2d8-e8ec57925bd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638435831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3638435831 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.746611784
Short name	T588
Test name
Test status
Simulation time	1158622908 ps
CPU time	67.42 seconds
Started	Dec 24 12:51:24 PM PST 23
Finished	Dec 24 12:52:36 PM PST 23
Peak memory	240592 kb
Host	smart-8456e798-70ee-48c9-a7a3-89b84627fa36
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=746611784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.746611784 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.1181804593
Short name	T182
Test name
Test status
Simulation time	278489132 ps
CPU time	4.07 seconds
Started	Dec 24 12:51:19 PM PST 23
Finished	Dec 24 12:51:30 PM PST 23
Peak memory	215696 kb
Host	smart-1a721429-7d57-4c91-92d4-37cd7064b10c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181804593 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.1181804593 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.4176982416
Short name	T471
Test name
Test status
Simulation time	254860889 ps
CPU time	4.76 seconds
Started	Dec 24 12:51:16 PM PST 23
Finished	Dec 24 12:51:28 PM PST 23
Peak memory	215672 kb
Host	smart-1b13885b-293e-49ef-91dc-769fec807baf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176982416 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.4176982416 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.3972537964
Short name	T532
Test name
Test status
Simulation time	19665419636 ps
CPU time	1556.38 seconds
Started	Dec 24 12:51:30 PM PST 23
Finished	Dec 24 01:17:28 PM PST 23
Peak memory	393056 kb
Host	smart-80b5328b-0800-4924-9ac3-55819db86a01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3972537964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3972537964 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.3729871791
Short name	T188
Test name
Test status
Simulation time	93929150830 ps
CPU time	1814.44 seconds
Started	Dec 24 12:51:21 PM PST 23
Finished	Dec 24 01:21:41 PM PST 23
Peak memory	371928 kb
Host	smart-ffdc9404-3008-45a5-81e7-2bcaabafe9c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3729871791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3729871791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.270877607
Short name	T950
Test name
Test status
Simulation time	125047675459 ps
CPU time	1334.67 seconds
Started	Dec 24 12:51:15 PM PST 23
Finished	Dec 24 01:13:37 PM PST 23
Peak memory	336000 kb
Host	smart-17ce4518-b2bb-49d5-95fc-dc925c41c1b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=270877607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.270877607 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.1811580537
Short name	T857
Test name
Test status
Simulation time	39275911425 ps
CPU time	776.98 seconds
Started	Dec 24 12:51:24 PM PST 23
Finished	Dec 24 01:04:26 PM PST 23
Peak memory	292724 kb
Host	smart-71f5b86d-7aff-4962-bf3c-1ca8bf5ec127
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1811580537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1811580537 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.700677063
Short name	T1139
Test name
Test status
Simulation time	179602757827 ps
CPU time	4830.81 seconds
Started	Dec 24 12:51:20 PM PST 23
Finished	Dec 24 02:11:58 PM PST 23
Peak memory	652100 kb
Host	smart-fafe5ee1-162a-498b-ae49-fb86135b9141
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=700677063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.700677063 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.155102842
Short name	T256
Test name
Test status
Simulation time	228074886499 ps
CPU time	4282.04 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 02:02:48 PM PST 23
Peak memory	551824 kb
Host	smart-3d46d5c7-3fa8-40d7-9b7e-4a8ca38ca73d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=155102842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.155102842 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.92941740
Short name	T557
Test name
Test status
Simulation time	75954752 ps
CPU time	0.8 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 12:51:35 PM PST 23
Peak memory	205188 kb
Host	smart-5268bfe3-e3f1-407f-a584-c52618cf3d6f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92941740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.92941740 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.1860613347
Short name	T302
Test name
Test status
Simulation time	3175612290 ps
CPU time	17.85 seconds
Started	Dec 24 12:51:33 PM PST 23
Finished	Dec 24 12:51:53 PM PST 23
Peak memory	218076 kb
Host	smart-e32fd1f7-14b9-4e9e-bc9c-75c231b4fa81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860613347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1860613347 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.1200038591
Short name	T415
Test name
Test status
Simulation time	17526881583 ps
CPU time	355.93 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 12:57:35 PM PST 23
Peak memory	229052 kb
Host	smart-804faa5b-d69e-4622-813f-c53bf0d9496a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200038591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1200038591 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.3126204250
Short name	T989
Test name
Test status
Simulation time	14566652738 ps
CPU time	255.82 seconds
Started	Dec 24 12:51:39 PM PST 23
Finished	Dec 24 12:55:58 PM PST 23
Peak memory	246404 kb
Host	smart-12c93fc8-bbcf-4ee1-82bf-382b6ec7f2cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126204250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3126204250 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.2173186662
Short name	T968
Test name
Test status
Simulation time	4693847413 ps
CPU time	337.5 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:57:20 PM PST 23
Peak memory	256748 kb
Host	smart-efa6538d-5523-4cd1-8d8b-c04e7ff690e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173186662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2173186662 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_key_error.2242501710
Short name	T996
Test name
Test status
Simulation time	3582855784 ps
CPU time	4.9 seconds
Started	Dec 24 12:51:35 PM PST 23
Finished	Dec 24 12:51:41 PM PST 23
Peak memory	207320 kb
Host	smart-b32b7261-0f0b-4cea-8649-89d5963a7ffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242501710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2242501710 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.880331117
Short name	T401
Test name
Test status
Simulation time	107485192 ps
CPU time	1.2 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 12:51:40 PM PST 23
Peak memory	215900 kb
Host	smart-e94e0d34-98d0-48b4-94af-6ff6b1b8a8b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880331117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.880331117 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.1477663272
Short name	T200
Test name
Test status
Simulation time	386538040105 ps
CPU time	1831.93 seconds
Started	Dec 24 12:51:18 PM PST 23
Finished	Dec 24 01:21:58 PM PST 23
Peak memory	388692 kb
Host	smart-4e339725-1bd2-4c5c-a205-de31d33b27c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477663272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.1477663272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.3545753039
Short name	T562
Test name
Test status
Simulation time	4254771431 ps
CPU time	83.45 seconds
Started	Dec 24 12:51:35 PM PST 23
Finished	Dec 24 12:53:00 PM PST 23
Peak memory	227028 kb
Host	smart-c7587f4c-ba0e-4367-9cdc-9278dde4101f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545753039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3545753039 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.2522550064
Short name	T1082
Test name
Test status
Simulation time	8229500414 ps
CPU time	34.8 seconds
Started	Dec 24 12:51:44 PM PST 23
Finished	Dec 24 12:52:20 PM PST 23
Peak memory	216796 kb
Host	smart-553dc061-93ef-4655-a937-b7a4d4ea8401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522550064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2522550064 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.2680299425
Short name	T509
Test name
Test status
Simulation time	45541481574 ps
CPU time	984.09 seconds
Started	Dec 24 12:51:52 PM PST 23
Finished	Dec 24 01:08:18 PM PST 23
Peak memory	356288 kb
Host	smart-7efae551-5147-40d5-9340-725029e6d216
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2680299425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2680299425 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_stress_all_with_rand_reset.1627809522
Short name	T420
Test name
Test status
Simulation time	191472890428 ps
CPU time	644.9 seconds
Started	Dec 24 12:51:35 PM PST 23
Finished	Dec 24 01:02:22 PM PST 23
Peak memory	257024 kb
Host	smart-fbed8df7-56b0-4d0f-b383-606be844e1e9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1627809522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all_with_rand_reset.1627809522 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.132449971
Short name	T830
Test name
Test status
Simulation time	655127462 ps
CPU time	4.32 seconds
Started	Dec 24 12:51:46 PM PST 23
Finished	Dec 24 12:51:52 PM PST 23
Peak memory	215732 kb
Host	smart-98893901-5890-4c57-9591-63bd5ad343c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132449971 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.kmac_test_vectors_kmac.132449971 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2054677426
Short name	T1148
Test name
Test status
Simulation time	194212950 ps
CPU time	3.98 seconds
Started	Dec 24 12:51:35 PM PST 23
Finished	Dec 24 12:51:40 PM PST 23
Peak memory	215700 kb
Host	smart-8ff97801-8293-457e-8746-d2328eddf3ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054677426 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2054677426 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.3686281070
Short name	T216
Test name
Test status
Simulation time	406305304080 ps
CPU time	2010.25 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 01:25:10 PM PST 23
Peak memory	393292 kb
Host	smart-ea0d3e31-6c62-4826-ad22-e97081a145a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3686281070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3686281070 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.1365186085
Short name	T887
Test name
Test status
Simulation time	71532850886 ps
CPU time	1398.2 seconds
Started	Dec 24 12:51:31 PM PST 23
Finished	Dec 24 01:14:51 PM PST 23
Peak memory	362452 kb
Host	smart-957e502b-55ce-4a03-92cc-de6b4aa469c2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1365186085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1365186085 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.3949359703
Short name	T594
Test name
Test status
Simulation time	98240466678 ps
CPU time	1303.07 seconds
Started	Dec 24 12:51:33 PM PST 23
Finished	Dec 24 01:13:18 PM PST 23
Peak memory	336092 kb
Host	smart-b97700a4-3e1b-4e98-931a-6a5f1305ce2d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3949359703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3949359703 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.788346067
Short name	T1039
Test name
Test status
Simulation time	33965122864 ps
CPU time	876.14 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 01:06:16 PM PST 23
Peak memory	294576 kb
Host	smart-dbc8b7f0-c9e9-4501-9f63-239bbfc7eba2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=788346067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.788346067 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.1840652399
Short name	T879
Test name
Test status
Simulation time	52517526394 ps
CPU time	4176.82 seconds
Started	Dec 24 12:51:34 PM PST 23
Finished	Dec 24 02:01:13 PM PST 23
Peak memory	641460 kb
Host	smart-cfea62c1-f845-44df-a15a-8a9de4641ca3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1840652399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.1840652399 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.2828934237
Short name	T202
Test name
Test status
Simulation time	44652892610 ps
CPU time	3387.31 seconds
Started	Dec 24 12:51:37 PM PST 23
Finished	Dec 24 01:48:06 PM PST 23
Peak memory	569748 kb
Host	smart-2f9d6c28-c584-4481-b82f-6bf319e8488a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2828934237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2828934237 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.68588639
Short name	T1073
Test name
Test status
Simulation time	113518478 ps
CPU time	0.98 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:51:43 PM PST 23
Peak memory	205192 kb
Host	smart-f476d570-0539-440b-9e18-87fd5be262d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68588639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.68588639 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.3535506045
Short name	T263
Test name
Test status
Simulation time	4761891479 ps
CPU time	279.21 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:56:22 PM PST 23
Peak memory	245784 kb
Host	smart-0a6f99fc-9117-4fb4-aada-da4e05eb476c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535506045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3535506045 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.3054385852
Short name	T1054
Test name
Test status
Simulation time	19636442416 ps
CPU time	440.88 seconds
Started	Dec 24 12:51:49 PM PST 23
Finished	Dec 24 12:59:11 PM PST 23
Peak memory	227988 kb
Host	smart-95d3a68e-d878-4176-ad85-708d39e2107b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054385852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3054385852 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.1737930728
Short name	T77
Test name
Test status
Simulation time	6368187068 ps
CPU time	34.03 seconds
Started	Dec 24 12:51:51 PM PST 23
Finished	Dec 24 12:52:27 PM PST 23
Peak memory	223936 kb
Host	smart-a8730086-1234-4c1a-bb8f-7a48c0e49b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737930728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1737930728 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.3294588781
Short name	T31
Test name
Test status
Simulation time	12128158991 ps
CPU time	128.75 seconds
Started	Dec 24 12:51:45 PM PST 23
Finished	Dec 24 12:53:56 PM PST 23
Peak memory	248616 kb
Host	smart-b63c7c87-8dcc-44bb-94ac-1f1fc447dc07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294588781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3294588781 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.1403892831
Short name	T988
Test name
Test status
Simulation time	8724376179 ps
CPU time	7.77 seconds
Started	Dec 24 12:51:39 PM PST 23
Finished	Dec 24 12:51:48 PM PST 23
Peak memory	207352 kb
Host	smart-93e8da74-6dae-4df8-8001-bdcc7bb2eb53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403892831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1403892831 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.3971387663
Short name	T345
Test name
Test status
Simulation time	161934235 ps
CPU time	1.41 seconds
Started	Dec 24 12:51:31 PM PST 23
Finished	Dec 24 12:51:34 PM PST 23
Peak memory	215620 kb
Host	smart-b94455be-b44c-45c1-97bd-a0571232b673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971387663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3971387663 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.2719236629
Short name	T958
Test name
Test status
Simulation time	31950369612 ps
CPU time	721.43 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 01:03:35 PM PST 23
Peak memory	289480 kb
Host	smart-c900ebac-3171-47e9-a370-63dec8de9361
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719236629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.2719236629 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.4191066799
Short name	T1058
Test name
Test status
Simulation time	6252911550 ps
CPU time	168.96 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:54:31 PM PST 23
Peak memory	233876 kb
Host	smart-fed1464c-d49e-4d5a-8f76-de41238f5d26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191066799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.4191066799 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.2520098369
Short name	T1075
Test name
Test status
Simulation time	989163650 ps
CPU time	22.12 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	223928 kb
Host	smart-5a952123-0482-4ac5-8619-365aaf70da61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520098369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2520098369 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.2489684314
Short name	T457
Test name
Test status
Simulation time	18195848168 ps
CPU time	298.27 seconds
Started	Dec 24 12:51:53 PM PST 23
Finished	Dec 24 12:56:53 PM PST 23
Peak memory	288860 kb
Host	smart-7bfba6ef-9a19-47db-94cd-4f843d65d8e9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2489684314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2489684314 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_stress_all_with_rand_reset.907685253
Short name	T1043
Test name
Test status
Simulation time	13813418494 ps
CPU time	588.48 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 01:01:22 PM PST 23
Peak memory	289276 kb
Host	smart-7e2b607e-1b80-45ab-acb2-0762f577cf1a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=907685253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.907685253 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.1454866396
Short name	T546
Test name
Test status
Simulation time	186242010 ps
CPU time	4.74 seconds
Started	Dec 24 12:51:35 PM PST 23
Finished	Dec 24 12:51:41 PM PST 23
Peak memory	215720 kb
Host	smart-b10a1a3e-8358-446f-871a-5de99f7fe319
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454866396 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.1454866396 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1546789492
Short name	T997
Test name
Test status
Simulation time	1041502779 ps
CPU time	5.28 seconds
Started	Dec 24 12:51:40 PM PST 23
Finished	Dec 24 12:51:48 PM PST 23
Peak memory	215792 kb
Host	smart-0c0088f5-6246-41ba-bf06-82f671fefc95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546789492 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1546789492 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.1410548260
Short name	T590
Test name
Test status
Simulation time	39183769486 ps
CPU time	1518.53 seconds
Started	Dec 24 12:51:34 PM PST 23
Finished	Dec 24 01:16:54 PM PST 23
Peak memory	390952 kb
Host	smart-4a5e8567-a64b-43cc-89e5-f24c7cdf1751
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1410548260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1410548260 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.2088208667
Short name	T942
Test name
Test status
Simulation time	92263021309 ps
CPU time	1688.79 seconds
Started	Dec 24 12:51:37 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	365576 kb
Host	smart-01afce8c-9c04-4538-a2e3-aa43e433546b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2088208667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2088208667 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.2626912704
Short name	T205
Test name
Test status
Simulation time	28315814328 ps
CPU time	1152.91 seconds
Started	Dec 24 12:51:36 PM PST 23
Finished	Dec 24 01:10:50 PM PST 23
Peak memory	333764 kb
Host	smart-f294fcd4-f923-4037-82d9-995e95deb0d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2626912704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2626912704 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.3598529740
Short name	T1129
Test name
Test status
Simulation time	19118180739 ps
CPU time	787.07 seconds
Started	Dec 24 12:51:29 PM PST 23
Finished	Dec 24 01:04:38 PM PST 23
Peak memory	296300 kb
Host	smart-e8801b6a-98ba-4076-b58f-e416fbc3ea76
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3598529740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3598529740 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.2228471899
Short name	T191
Test name
Test status
Simulation time	724900432331 ps
CPU time	4965.13 seconds
Started	Dec 24 12:51:34 PM PST 23
Finished	Dec 24 02:14:21 PM PST 23
Peak memory	661560 kb
Host	smart-1468afed-a0b2-4799-9062-47bc3691e32a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2228471899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2228471899 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.4051169917
Short name	T483
Test name
Test status
Simulation time	501599167392 ps
CPU time	3931.56 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 01:57:10 PM PST 23
Peak memory	561564 kb
Host	smart-6526d3d5-fb7f-4f74-b4c2-cde4e14b3f87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4051169917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.4051169917 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.883835021
Short name	T488
Test name
Test status
Simulation time	37243753 ps
CPU time	0.75 seconds
Started	Dec 24 12:51:44 PM PST 23
Finished	Dec 24 12:51:46 PM PST 23
Peak memory	205088 kb
Host	smart-63e5ae5f-e79d-4110-8acf-2f641796599e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883835021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.883835021 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.2688116220
Short name	T226
Test name
Test status
Simulation time	44651310981 ps
CPU time	276.81 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 12:56:17 PM PST 23
Peak memory	241888 kb
Host	smart-b598c8db-e3d3-455b-9e9d-91b46ff7ae80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688116220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2688116220 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.3457991261
Short name	T1063
Test name
Test status
Simulation time	1311655659 ps
CPU time	19.49 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 12:51:53 PM PST 23
Peak memory	223232 kb
Host	smart-372818d5-c4d4-4fd7-90d2-aee508bccb52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457991261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3457991261 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.2117589701
Short name	T1035
Test name
Test status
Simulation time	19453523669 ps
CPU time	109.68 seconds
Started	Dec 24 12:51:50 PM PST 23
Finished	Dec 24 12:53:41 PM PST 23
Peak memory	229116 kb
Host	smart-c3a61041-6eba-410f-b450-35d35e844e83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117589701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2117589701 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.2363665254
Short name	T34
Test name
Test status
Simulation time	68396381670 ps
CPU time	343.38 seconds
Started	Dec 24 12:51:43 PM PST 23
Finished	Dec 24 12:57:28 PM PST 23
Peak memory	266044 kb
Host	smart-a91ffb55-dc5d-401a-ae67-41a688ef711a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363665254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2363665254 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.952512909
Short name	T529
Test name
Test status
Simulation time	1754009114 ps
CPU time	5.06 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 12:51:39 PM PST 23
Peak memory	207116 kb
Host	smart-3049ecb7-914b-4479-b1c1-2356d193d065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952512909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.952512909 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.1912830249
Short name	T774
Test name
Test status
Simulation time	205541113 ps
CPU time	1.38 seconds
Started	Dec 24 12:51:30 PM PST 23
Finished	Dec 24 12:51:33 PM PST 23
Peak memory	215588 kb
Host	smart-01cd6f55-cc36-442c-847d-e8ca05f9fbdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912830249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1912830249 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.264102212
Short name	T680
Test name
Test status
Simulation time	2457802809 ps
CPU time	202.37 seconds
Started	Dec 24 12:51:44 PM PST 23
Finished	Dec 24 12:55:08 PM PST 23
Peak memory	238652 kb
Host	smart-f11b4538-ae26-4a35-a518-33e2c58ccb73
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264102212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an d_output.264102212 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.461054576
Short name	T804
Test name
Test status
Simulation time	12369817674 ps
CPU time	224.33 seconds
Started	Dec 24 12:51:38 PM PST 23
Finished	Dec 24 12:55:24 PM PST 23
Peak memory	240704 kb
Host	smart-9be838c0-9340-4812-bad2-4ca8347ab2ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461054576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.461054576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.4188491248
Short name	T754
Test name
Test status
Simulation time	1714005925 ps
CPU time	29.03 seconds
Started	Dec 24 12:51:33 PM PST 23
Finished	Dec 24 12:52:04 PM PST 23
Peak memory	216768 kb
Host	smart-eca8171f-a97d-4aca-88fc-d016e2ea9711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188491248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4188491248 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.2158409991
Short name	T1002
Test name
Test status
Simulation time	128385658345 ps
CPU time	904.38 seconds
Started	Dec 24 12:51:39 PM PST 23
Finished	Dec 24 01:06:45 PM PST 23
Peak memory	341792 kb
Host	smart-60617596-cadf-4e31-8f7c-85ed54a23d6f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2158409991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2158409991 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_stress_all_with_rand_reset.3136619591
Short name	T1068
Test name
Test status
Simulation time	152652945899 ps
CPU time	836.22 seconds
Started	Dec 24 12:51:39 PM PST 23
Finished	Dec 24 01:05:38 PM PST 23
Peak memory	304492 kb
Host	smart-907f8c15-570e-451b-b9af-d0ff429d9157
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3136619591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.3136619591 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.1008482997
Short name	T545
Test name
Test status
Simulation time	517201413 ps
CPU time	4.52 seconds
Started	Dec 24 12:51:45 PM PST 23
Finished	Dec 24 12:51:51 PM PST 23
Peak memory	215608 kb
Host	smart-c0a4c0d1-e4f9-40ca-a864-0f4521511d4b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008482997 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.1008482997 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.2386930858
Short name	T906
Test name
Test status
Simulation time	66569539 ps
CPU time	3.98 seconds
Started	Dec 24 12:51:39 PM PST 23
Finished	Dec 24 12:51:46 PM PST 23
Peak memory	215712 kb
Host	smart-58e89d1f-1c36-49f1-82f2-0dc409c84775
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386930858 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.2386930858 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.3395638883
Short name	T667
Test name
Test status
Simulation time	19652351106 ps
CPU time	1562.45 seconds
Started	Dec 24 12:51:32 PM PST 23
Finished	Dec 24 01:17:36 PM PST 23
Peak memory	399980 kb
Host	smart-6463b355-af27-4cd8-adfb-1b6c2bba9787
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3395638883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3395638883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.906084832
Short name	T400
Test name
Test status
Simulation time	124594718866 ps
CPU time	1750.09 seconds
Started	Dec 24 12:51:43 PM PST 23
Finished	Dec 24 01:20:55 PM PST 23
Peak memory	373788 kb
Host	smart-4f99664b-92da-4ca6-8845-3605ebc274a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=906084832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.906084832 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.2602002212
Short name	T208
Test name
Test status
Simulation time	59860105484 ps
CPU time	1291.54 seconds
Started	Dec 24 12:51:41 PM PST 23
Finished	Dec 24 01:13:15 PM PST 23
Peak memory	329560 kb
Host	smart-17ead969-b076-4b96-a319-e5bc0c420612
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2602002212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.2602002212 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.1836598051
Short name	T536
Test name
Test status
Simulation time	97264424516 ps
CPU time	966.44 seconds
Started	Dec 24 12:51:37 PM PST 23
Finished	Dec 24 01:07:45 PM PST 23
Peak memory	293920 kb
Host	smart-207ccafa-1968-4275-8494-3ef415d478f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1836598051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1836598051 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.725509732
Short name	T614
Test name
Test status
Simulation time	51310926883 ps
CPU time	4126.21 seconds
Started	Dec 24 12:51:37 PM PST 23
Finished	Dec 24 02:00:24 PM PST 23
Peak memory	638036 kb
Host	smart-e4adf6a3-d76d-449f-b75a-192cf6984296
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=725509732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.725509732 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.739223926
Short name	T392
Test name
Test status
Simulation time	179575320674 ps
CPU time	3448.31 seconds
Started	Dec 24 12:51:33 PM PST 23
Finished	Dec 24 01:49:04 PM PST 23
Peak memory	558164 kb
Host	smart-1c05b507-1d14-4333-b4f4-146c55d862fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=739223926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.739223926 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.824859594
Short name	T429
Test name
Test status
Simulation time	52059064 ps
CPU time	0.78 seconds
Started	Dec 24 12:52:06 PM PST 23
Finished	Dec 24 12:52:08 PM PST 23
Peak memory	205164 kb
Host	smart-ced3fe2e-17f5-428d-b989-b710dcb5c5df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824859594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.824859594 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.2939363214
Short name	T506
Test name
Test status
Simulation time	1081702889 ps
CPU time	23.96 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 12:52:29 PM PST 23
Peak memory	223840 kb
Host	smart-40ce7789-e41e-42e3-92cb-f24b2307ce4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939363214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2939363214 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.2397035367
Short name	T952
Test name
Test status
Simulation time	8614783466 ps
CPU time	690.26 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 01:03:36 PM PST 23
Peak memory	231260 kb
Host	smart-cc5aa8cc-acc3-4c2b-ad06-760040af1062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397035367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.2397035367 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.2619048618
Short name	T994
Test name
Test status
Simulation time	23246133980 ps
CPU time	243.4 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 12:56:09 PM PST 23
Peak memory	240856 kb
Host	smart-5acd6ade-6499-4772-b936-6d466d2c6627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619048618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2619048618 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.569817342
Short name	T905
Test name
Test status
Simulation time	7312851834 ps
CPU time	73.15 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 12:53:18 PM PST 23
Peak memory	233184 kb
Host	smart-53dd046e-ec00-4f34-92b2-f930d97360d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569817342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.569817342 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.1407891003
Short name	T66
Test name
Test status
Simulation time	1882759801 ps
CPU time	3.58 seconds
Started	Dec 24 12:51:58 PM PST 23
Finished	Dec 24 12:52:03 PM PST 23
Peak memory	207088 kb
Host	smart-9a64ebd4-8056-44a0-a51e-553b8e0a317a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407891003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1407891003 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.4166200384
Short name	T360
Test name
Test status
Simulation time	104266034 ps
CPU time	1.22 seconds
Started	Dec 24 12:52:01 PM PST 23
Finished	Dec 24 12:52:04 PM PST 23
Peak memory	219612 kb
Host	smart-57a6958f-cf87-429f-a921-1987ee22a0aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166200384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4166200384 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.189326513
Short name	T635
Test name
Test status
Simulation time	538210561861 ps
CPU time	2236.43 seconds
Started	Dec 24 12:51:55 PM PST 23
Finished	Dec 24 01:29:13 PM PST 23
Peak memory	437744 kb
Host	smart-08ba95c6-0507-4095-bb98-149eb14c1618
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189326513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an d_output.189326513 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.3485099006
Short name	T203
Test name
Test status
Simulation time	524509157 ps
CPU time	40.63 seconds
Started	Dec 24 12:51:57 PM PST 23
Finished	Dec 24 12:52:39 PM PST 23
Peak memory	223772 kb
Host	smart-e74f0ad6-bda2-4451-9a79-092b190f5608
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485099006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3485099006 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.2041892423
Short name	T365
Test name
Test status
Simulation time	3275013594 ps
CPU time	51.3 seconds
Started	Dec 24 12:51:58 PM PST 23
Finished	Dec 24 12:52:51 PM PST 23
Peak memory	215900 kb
Host	smart-1b2ef14d-e397-406d-9872-bbddfdc80d80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041892423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2041892423 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.121709482
Short name	T27
Test name
Test status
Simulation time	204938030569 ps
CPU time	1098.85 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 01:10:25 PM PST 23
Peak memory	355216 kb
Host	smart-699614a3-5927-4214-bc48-d605e4f51857
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=121709482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.121709482 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.623807412
Short name	T434
Test name
Test status
Simulation time	4824279005 ps
CPU time	5.33 seconds
Started	Dec 24 12:51:58 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	215748 kb
Host	smart-d11b7f6a-09f3-4dd0-b74b-19cca2330239
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623807412 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 35.kmac_test_vectors_kmac.623807412 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.4031554370
Short name	T179
Test name
Test status
Simulation time	295318139 ps
CPU time	4.09 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 12:52:06 PM PST 23
Peak memory	215560 kb
Host	smart-e8c259db-4909-4869-bf88-710d5279d800
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031554370 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.4031554370 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.2467213249
Short name	T5
Test name
Test status
Simulation time	421221854007 ps
CPU time	1989.78 seconds
Started	Dec 24 12:51:56 PM PST 23
Finished	Dec 24 01:25:07 PM PST 23
Peak memory	390796 kb
Host	smart-fd530a2a-3086-4504-afe7-f7eb0b50ee74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2467213249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2467213249 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.2193624818
Short name	T431
Test name
Test status
Simulation time	368726901656 ps
CPU time	1770.04 seconds
Started	Dec 24 12:51:54 PM PST 23
Finished	Dec 24 01:21:26 PM PST 23
Peak memory	388408 kb
Host	smart-77b7dcc7-8106-4598-91dd-3e9a5b82fb68
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2193624818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2193624818 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.3719017853
Short name	T925
Test name
Test status
Simulation time	46109458853 ps
CPU time	1299.24 seconds
Started	Dec 24 12:51:56 PM PST 23
Finished	Dec 24 01:13:37 PM PST 23
Peak memory	329776 kb
Host	smart-3a88ee6c-8f90-418e-bc4c-db211b969e2c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3719017853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3719017853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.1611201227
Short name	T785
Test name
Test status
Simulation time	160416014910 ps
CPU time	751.35 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 01:04:36 PM PST 23
Peak memory	296692 kb
Host	smart-c68c42f0-22f8-4a63-b85a-0c2013b387f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1611201227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1611201227 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.1446635778
Short name	T768
Test name
Test status
Simulation time	1946584534488 ps
CPU time	5499.67 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 02:23:46 PM PST 23
Peak memory	668184 kb
Host	smart-6e2c7b5b-ed71-4b94-8f75-1c3f83139900
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1446635778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1446635778 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.3307844642
Short name	T634
Test name
Test status
Simulation time	197537735022 ps
CPU time	3766.64 seconds
Started	Dec 24 12:51:56 PM PST 23
Finished	Dec 24 01:54:45 PM PST 23
Peak memory	565660 kb
Host	smart-7529d0a4-5e0c-4285-b22f-32359e25d404
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3307844642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3307844642 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.1623482833
Short name	T730
Test name
Test status
Simulation time	19092364 ps
CPU time	0.83 seconds
Started	Dec 24 12:51:58 PM PST 23
Finished	Dec 24 12:52:01 PM PST 23
Peak memory	205088 kb
Host	smart-5ec41479-66f7-4496-963e-7f3795df1441
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623482833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1623482833 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.4023763089
Short name	T327
Test name
Test status
Simulation time	15054590090 ps
CPU time	198.54 seconds
Started	Dec 24 12:51:58 PM PST 23
Finished	Dec 24 12:55:18 PM PST 23
Peak memory	240180 kb
Host	smart-942ee885-a44c-44fb-bee0-1a432d2caa3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023763089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.4023763089 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.4059427463
Short name	T691
Test name
Test status
Simulation time	3864050477 ps
CPU time	323.38 seconds
Started	Dec 24 12:52:05 PM PST 23
Finished	Dec 24 12:57:30 PM PST 23
Peak memory	228008 kb
Host	smart-9c093531-731d-4aeb-81a9-4214b42a9912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059427463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.4059427463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.326252219
Short name	T1006
Test name
Test status
Simulation time	1307464972 ps
CPU time	6.86 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 12:52:13 PM PST 23
Peak memory	222312 kb
Host	smart-22b80c89-171b-4fad-9d2a-9a81894efb9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326252219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.326252219 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.3050320464
Short name	T447
Test name
Test status
Simulation time	1302155613 ps
CPU time	40.04 seconds
Started	Dec 24 12:52:08 PM PST 23
Finished	Dec 24 12:52:51 PM PST 23
Peak memory	240264 kb
Host	smart-86faadd5-86da-478e-8ac3-e20871e447d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050320464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3050320464 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.351642940
Short name	T305
Test name
Test status
Simulation time	500177973 ps
CPU time	2.6 seconds
Started	Dec 24 12:51:54 PM PST 23
Finished	Dec 24 12:51:58 PM PST 23
Peak memory	207036 kb
Host	smart-a64943c1-a5dd-44b4-bd33-78ac4ea3f0cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351642940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.351642940 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.2887295948
Short name	T333
Test name
Test status
Simulation time	59395814 ps
CPU time	1.44 seconds
Started	Dec 24 12:51:54 PM PST 23
Finished	Dec 24 12:51:57 PM PST 23
Peak memory	216560 kb
Host	smart-35a8bd5c-e29a-4e10-922b-9ba507c2c5ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887295948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2887295948 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.3838607725
Short name	T965
Test name
Test status
Simulation time	230287205947 ps
CPU time	2411.52 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 01:32:17 PM PST 23
Peak memory	439956 kb
Host	smart-d336fdd0-a31a-4f13-817b-dbab5ab77dcc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838607725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.3838607725 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.316625970
Short name	T1095
Test name
Test status
Simulation time	15490034238 ps
CPU time	203.94 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 12:55:26 PM PST 23
Peak memory	236376 kb
Host	smart-ebac5f30-a33b-478f-8e8e-2a80c6388375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316625970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.316625970 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.3285368631
Short name	T1120
Test name
Test status
Simulation time	3477685616 ps
CPU time	57.2 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 12:53:01 PM PST 23
Peak memory	217840 kb
Host	smart-bd7632f1-6247-4d4d-96a7-9dda026cc230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285368631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3285368631 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.1371509124
Short name	T741
Test name
Test status
Simulation time	60001393468 ps
CPU time	192.94 seconds
Started	Dec 24 12:51:55 PM PST 23
Finished	Dec 24 12:55:09 PM PST 23
Peak memory	255396 kb
Host	smart-256e6031-4224-4671-b400-26de0ef8edd2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1371509124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1371509124 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.1276127328
Short name	T325
Test name
Test status
Simulation time	180048728848 ps
CPU time	937.36 seconds
Started	Dec 24 12:51:56 PM PST 23
Finished	Dec 24 01:07:36 PM PST 23
Peak memory	299016 kb
Host	smart-d966aec8-d8ff-4145-81b8-0d6885e6878e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1276127328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.1276127328 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.475087590
Short name	T245
Test name
Test status
Simulation time	95008116 ps
CPU time	3.67 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	215592 kb
Host	smart-98075c6c-363e-4454-9e04-447fca03415e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475087590 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.kmac_test_vectors_kmac.475087590 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.291498083
Short name	T779
Test name
Test status
Simulation time	134588015 ps
CPU time	4.33 seconds
Started	Dec 24 12:52:01 PM PST 23
Finished	Dec 24 12:52:07 PM PST 23
Peak memory	215740 kb
Host	smart-15dafacd-f010-4407-b6d7-fe6ced7a7880
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291498083 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 36.kmac_test_vectors_kmac_xof.291498083 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.2818347982
Short name	T659
Test name
Test status
Simulation time	201356459615 ps
CPU time	1949.51 seconds
Started	Dec 24 12:51:59 PM PST 23
Finished	Dec 24 01:24:30 PM PST 23
Peak memory	389912 kb
Host	smart-759faa13-d990-4cb4-9c5d-bb460e5c4309
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2818347982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2818347982 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.4108288783
Short name	T369
Test name
Test status
Simulation time	111960935193 ps
CPU time	1466.11 seconds
Started	Dec 24 12:51:52 PM PST 23
Finished	Dec 24 01:16:20 PM PST 23
Peak memory	377060 kb
Host	smart-3a86c433-818c-4649-84d6-cb4daf65c884
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4108288783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.4108288783 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.2000967402
Short name	T199
Test name
Test status
Simulation time	69722089121 ps
CPU time	1311.7 seconds
Started	Dec 24 12:52:06 PM PST 23
Finished	Dec 24 01:13:59 PM PST 23
Peak memory	330236 kb
Host	smart-7bb10f64-b8c2-4865-929d-db04e3037eef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2000967402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2000967402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.3067208081
Short name	T331
Test name
Test status
Simulation time	101300630355 ps
CPU time	1016.27 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 01:08:58 PM PST 23
Peak memory	294080 kb
Host	smart-2c09347d-1fa1-4a19-9400-d71f13c12970
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3067208081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3067208081 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.2287450915
Short name	T576
Test name
Test status
Simulation time	106091457740 ps
CPU time	4102.83 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 02:00:25 PM PST 23
Peak memory	653436 kb
Host	smart-9c9a146a-7220-4605-9c30-f42f6f3ec82f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2287450915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2287450915 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.3141090223
Short name	T1126
Test name
Test status
Simulation time	229452658130 ps
CPU time	3518.24 seconds
Started	Dec 24 12:52:01 PM PST 23
Finished	Dec 24 01:50:42 PM PST 23
Peak memory	567252 kb
Host	smart-b11cfb01-5f01-42ae-90c3-79bc79fee666
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3141090223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3141090223 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.4098672637
Short name	T647
Test name
Test status
Simulation time	41349191 ps
CPU time	0.76 seconds
Started	Dec 24 12:51:57 PM PST 23
Finished	Dec 24 12:51:59 PM PST 23
Peak memory	205172 kb
Host	smart-90a7506f-dafd-4913-b15d-8bd150158958
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098672637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.4098672637 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.2436942393
Short name	T340
Test name
Test status
Simulation time	8445699425 ps
CPU time	178.27 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 12:55:04 PM PST 23
Peak memory	237588 kb
Host	smart-fc9fd2ca-2cbd-4df4-bae5-3281a51e22fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436942393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2436942393 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.1014221961
Short name	T793
Test name
Test status
Simulation time	3953203246 ps
CPU time	321.13 seconds
Started	Dec 24 12:52:06 PM PST 23
Finished	Dec 24 12:57:29 PM PST 23
Peak memory	228688 kb
Host	smart-b099af42-f0c0-4ccb-b06f-d9a49d4483ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014221961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1014221961 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.2030016126
Short name	T406
Test name
Test status
Simulation time	25942835843 ps
CPU time	256.3 seconds
Started	Dec 24 12:52:01 PM PST 23
Finished	Dec 24 12:56:18 PM PST 23
Peak memory	243788 kb
Host	smart-284acdf4-6cc4-40be-9f24-ec9efba5c6a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030016126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2030016126 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.2433477694
Short name	T1011
Test name
Test status
Simulation time	212792961 ps
CPU time	4.86 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 12:52:11 PM PST 23
Peak memory	223860 kb
Host	smart-2dc86b4b-abe4-44eb-a8d1-af6419f8505f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433477694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2433477694 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.2525403558
Short name	T735
Test name
Test status
Simulation time	4157223654 ps
CPU time	6.6 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 12:52:12 PM PST 23
Peak memory	207168 kb
Host	smart-30aa4c8d-901f-4c29-b194-a8cd50fa3274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525403558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2525403558 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.2650198573
Short name	T654
Test name
Test status
Simulation time	111670122 ps
CPU time	1.34 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	215556 kb
Host	smart-2db1a400-3a43-4aea-bc14-4ee8135fcefa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650198573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2650198573 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.2127822237
Short name	T436
Test name
Test status
Simulation time	109556855771 ps
CPU time	2506.57 seconds
Started	Dec 24 12:51:57 PM PST 23
Finished	Dec 24 01:33:45 PM PST 23
Peak memory	454116 kb
Host	smart-f2df58aa-60db-4757-867a-6efd8c3eec2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127822237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.2127822237 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.2299466433
Short name	T781
Test name
Test status
Simulation time	1104140515 ps
CPU time	28.51 seconds
Started	Dec 24 12:51:59 PM PST 23
Finished	Dec 24 12:52:30 PM PST 23
Peak memory	223452 kb
Host	smart-3d1ff342-a8ad-44c0-acd5-9b3d3f23da44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299466433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2299466433 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.1166394772
Short name	T724
Test name
Test status
Simulation time	262524822 ps
CPU time	6.37 seconds
Started	Dec 24 12:52:07 PM PST 23
Finished	Dec 24 12:52:16 PM PST 23
Peak memory	223648 kb
Host	smart-f34263c7-cacf-42e5-a7ba-2385eaa23ccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166394772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1166394772 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.3912939543
Short name	T280
Test name
Test status
Simulation time	281777896 ps
CPU time	4.08 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 12:52:09 PM PST 23
Peak memory	215620 kb
Host	smart-73c25bf2-1eaa-4e1f-8c92-fdcd928e91fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3912939543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3912939543 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_stress_all_with_rand_reset.3162979698
Short name	T424
Test name
Test status
Simulation time	76540950202 ps
CPU time	911.52 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 01:07:13 PM PST 23
Peak memory	273352 kb
Host	smart-69779aa5-6d6b-4d29-a869-9be3c43a5604
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3162979698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all_with_rand_reset.3162979698 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.2139236330
Short name	T252
Test name
Test status
Simulation time	262300704 ps
CPU time	4.16 seconds
Started	Dec 24 12:51:59 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	215772 kb
Host	smart-1d812d4f-de3a-4a59-8075-cb9fe86dd655
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139236330 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.2139236330 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2131352069
Short name	T933
Test name
Test status
Simulation time	173591866 ps
CPU time	4.45 seconds
Started	Dec 24 12:51:59 PM PST 23
Finished	Dec 24 12:52:05 PM PST 23
Peak memory	215676 kb
Host	smart-f91d886d-877d-4c8c-9ddd-b8023cf27125
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131352069 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2131352069 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.1648947440
Short name	T264
Test name
Test status
Simulation time	18697729824 ps
CPU time	1405.99 seconds
Started	Dec 24 12:52:02 PM PST 23
Finished	Dec 24 01:15:30 PM PST 23
Peak memory	378248 kb
Host	smart-e794a193-51ac-466c-9236-aede33382283
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1648947440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1648947440 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.275484862
Short name	T217
Test name
Test status
Simulation time	65053564494 ps
CPU time	1634.87 seconds
Started	Dec 24 12:51:55 PM PST 23
Finished	Dec 24 01:19:11 PM PST 23
Peak memory	370120 kb
Host	smart-3469f43a-b6bb-4c52-95e9-e50b928a44c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=275484862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.275484862 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.145260515
Short name	T493
Test name
Test status
Simulation time	54771350865 ps
CPU time	1132.58 seconds
Started	Dec 24 12:52:11 PM PST 23
Finished	Dec 24 01:11:04 PM PST 23
Peak memory	335304 kb
Host	smart-1c914f96-9c59-4c8d-910d-5bf4d9bf607b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=145260515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.145260515 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.2424094174
Short name	T908
Test name
Test status
Simulation time	32555580278 ps
CPU time	867.64 seconds
Started	Dec 24 12:51:55 PM PST 23
Finished	Dec 24 01:06:24 PM PST 23
Peak memory	293652 kb
Host	smart-cce91c8e-eb17-45fb-8965-64d16adbb7cb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2424094174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2424094174 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.1089277501
Short name	T356
Test name
Test status
Simulation time	267682908716 ps
CPU time	4961.33 seconds
Started	Dec 24 12:51:55 PM PST 23
Finished	Dec 24 02:14:39 PM PST 23
Peak memory	651048 kb
Host	smart-f3ae95fb-607f-4648-93aa-2be1621721ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1089277501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1089277501 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.161628265
Short name	T817
Test name
Test status
Simulation time	142992131835 ps
CPU time	3940.92 seconds
Started	Dec 24 12:51:50 PM PST 23
Finished	Dec 24 01:57:33 PM PST 23
Peak memory	547176 kb
Host	smart-082357af-b4bb-4bb2-ad28-94fb22c77181
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=161628265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.161628265 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.483881887
Short name	T289
Test name
Test status
Simulation time	22401734 ps
CPU time	0.84 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:35 PM PST 23
Peak memory	204992 kb
Host	smart-198727c5-5876-415b-bed8-54f7200e6205
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483881887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.483881887 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.1745310137
Short name	T549
Test name
Test status
Simulation time	2683448447 ps
CPU time	66.16 seconds
Started	Dec 24 12:52:17 PM PST 23
Finished	Dec 24 12:53:24 PM PST 23
Peak memory	224124 kb
Host	smart-a11b6689-6496-4f97-9beb-5b421fe40a1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745310137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1745310137 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.895773528
Short name	T1009
Test name
Test status
Simulation time	17071509931 ps
CPU time	717.59 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 01:03:59 PM PST 23
Peak memory	240148 kb
Host	smart-cece54fa-b5ec-4915-9a91-13c631b4c3c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895773528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.895773528 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.3389572135
Short name	T301
Test name
Test status
Simulation time	30126100761 ps
CPU time	242.58 seconds
Started	Dec 24 12:52:11 PM PST 23
Finished	Dec 24 12:56:14 PM PST 23
Peak memory	239104 kb
Host	smart-a90d4936-5722-4ce6-9ea9-3da28b6420ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389572135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3389572135 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.3118068217
Short name	T872
Test name
Test status
Simulation time	6691894752 ps
CPU time	282.57 seconds
Started	Dec 24 12:52:15 PM PST 23
Finished	Dec 24 12:56:59 PM PST 23
Peak memory	264748 kb
Host	smart-c7424f22-8a02-4c37-b4a1-dbe9c772cfdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118068217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3118068217 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.3627558462
Short name	T891
Test name
Test status
Simulation time	839276421 ps
CPU time	4.44 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:38 PM PST 23
Peak memory	207212 kb
Host	smart-8ba62ffb-937f-4fdb-a677-90bedfa3016e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627558462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3627558462 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.1088067134
Short name	T1048
Test name
Test status
Simulation time	34512069 ps
CPU time	1.21 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:35 PM PST 23
Peak memory	215548 kb
Host	smart-c7e9f240-3d56-4397-a5d6-0f89b9c1154a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088067134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1088067134 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.550765098
Short name	T626
Test name
Test status
Simulation time	876935911764 ps
CPU time	3199.85 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 01:45:26 PM PST 23
Peak memory	485456 kb
Host	smart-65957bbf-384a-423c-a1fe-f2f0b1161f16
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550765098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an d_output.550765098 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.1165016277
Short name	T395
Test name
Test status
Simulation time	15131042561 ps
CPU time	266.4 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 12:56:32 PM PST 23
Peak memory	244844 kb
Host	smart-1efde939-9b69-441b-a4d0-6ebd24689f8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165016277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1165016277 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.1552738791
Short name	T786
Test name
Test status
Simulation time	3800522246 ps
CPU time	25.2 seconds
Started	Dec 24 12:52:04 PM PST 23
Finished	Dec 24 12:52:31 PM PST 23
Peak memory	223684 kb
Host	smart-4b0a4b5b-9d0d-45d3-b526-9f113d2b81ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552738791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1552738791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.1651590854
Short name	T441
Test name
Test status
Simulation time	33913021841 ps
CPU time	849.45 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 01:06:42 PM PST 23
Peak memory	350364 kb
Host	smart-89167f95-1f7b-4a51-84ab-7392686b43a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1651590854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1651590854 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_stress_all_with_rand_reset.2364356442
Short name	T311
Test name
Test status
Simulation time	204652287219 ps
CPU time	797.85 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 01:05:53 PM PST 23
Peak memory	257460 kb
Host	smart-c4675b62-37a4-4872-996b-c52e5979d98e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2364356442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.2364356442 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.3573341636
Short name	T837
Test name
Test status
Simulation time	178965890 ps
CPU time	4.4 seconds
Started	Dec 24 12:52:05 PM PST 23
Finished	Dec 24 12:52:11 PM PST 23
Peak memory	215716 kb
Host	smart-7fd7305c-5173-4d86-96e2-689109c946d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573341636 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.3573341636 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.4266883812
Short name	T504
Test name
Test status
Simulation time	274473956 ps
CPU time	4.24 seconds
Started	Dec 24 12:52:12 PM PST 23
Finished	Dec 24 12:52:17 PM PST 23
Peak memory	215528 kb
Host	smart-402566f2-610d-407b-a2e8-805acf524300
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266883812 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.4266883812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.1876933365
Short name	T1069
Test name
Test status
Simulation time	39181917250 ps
CPU time	1453.52 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 01:16:47 PM PST 23
Peak memory	390284 kb
Host	smart-1ee0335f-b5a4-489d-b0c5-644434c2e6cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1876933365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1876933365 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.3990853579
Short name	T257
Test name
Test status
Simulation time	19084824069 ps
CPU time	1355.8 seconds
Started	Dec 24 12:52:00 PM PST 23
Finished	Dec 24 01:14:38 PM PST 23
Peak memory	373616 kb
Host	smart-536fbffa-a6db-466c-b51a-70a06579cb8e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3990853579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.3990853579 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.660404154
Short name	T702
Test name
Test status
Simulation time	99091380735 ps
CPU time	1320.91 seconds
Started	Dec 24 12:52:03 PM PST 23
Finished	Dec 24 01:14:07 PM PST 23
Peak memory	328100 kb
Host	smart-8d26858f-d910-42fc-84a2-6b7f1857b5e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=660404154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.660404154 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.2359458746
Short name	T763
Test name
Test status
Simulation time	102937909531 ps
CPU time	926.32 seconds
Started	Dec 24 12:52:11 PM PST 23
Finished	Dec 24 01:07:39 PM PST 23
Peak memory	297020 kb
Host	smart-da1d1881-ffee-4b62-ad58-9a2791b09fba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2359458746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2359458746 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.3939288400
Short name	T294
Test name
Test status
Simulation time	1041733945431 ps
CPU time	5361.25 seconds
Started	Dec 24 12:52:09 PM PST 23
Finished	Dec 24 02:21:33 PM PST 23
Peak memory	665056 kb
Host	smart-7290dd4d-f9cb-4b1d-8973-5cac4d5d1cc4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3939288400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3939288400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.471724799
Short name	T220
Test name
Test status
Simulation time	220593144241 ps
CPU time	4087.5 seconds
Started	Dec 24 12:52:15 PM PST 23
Finished	Dec 24 02:00:24 PM PST 23
Peak memory	559344 kb
Host	smart-d1b64d8a-9673-4bfb-a7a2-faffe10bce26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=471724799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.471724799 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.567825471
Short name	T1044
Test name
Test status
Simulation time	47580135 ps
CPU time	0.77 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 12:52:36 PM PST 23
Peak memory	205044 kb
Host	smart-2bcbe3de-7c2f-4ccb-8b6c-c6fbbc40fbfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567825471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.567825471 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.1636833828
Short name	T914
Test name
Test status
Simulation time	1055695935 ps
CPU time	5.19 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:39 PM PST 23
Peak memory	216824 kb
Host	smart-1f116bf6-2939-4c44-9501-765b20391529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636833828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1636833828 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.1227527673
Short name	T652
Test name
Test status
Simulation time	8778935018 ps
CPU time	170.78 seconds
Started	Dec 24 12:52:36 PM PST 23
Finished	Dec 24 12:55:28 PM PST 23
Peak memory	224988 kb
Host	smart-93d2d051-d528-4641-ac17-98bcb2ebb133
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227527673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1227527673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.3804334117
Short name	T448
Test name
Test status
Simulation time	4220764002 ps
CPU time	94.17 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:54:09 PM PST 23
Peak memory	227912 kb
Host	smart-5d50635d-ac38-42bf-8fd4-ed5d713ad109
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804334117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3804334117 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.3160487812
Short name	T604
Test name
Test status
Simulation time	2275183193 ps
CPU time	47.88 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:53:22 PM PST 23
Peak memory	237624 kb
Host	smart-1e9f3fd4-015d-4478-aa3e-87bf63bec685
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160487812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3160487812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.2412061951
Short name	T978
Test name
Test status
Simulation time	189675247 ps
CPU time	1.77 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:52:37 PM PST 23
Peak memory	207004 kb
Host	smart-87e76c05-5d54-4261-a2a6-4936b51f0a02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412061951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2412061951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.2912316979
Short name	T346
Test name
Test status
Simulation time	72783760 ps
CPU time	1.27 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:52:38 PM PST 23
Peak memory	215532 kb
Host	smart-1c86e225-7af0-4144-a36d-287642c57a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912316979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2912316979 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.510405252
Short name	T560
Test name
Test status
Simulation time	109336923015 ps
CPU time	2324.48 seconds
Started	Dec 24 12:52:38 PM PST 23
Finished	Dec 24 01:31:24 PM PST 23
Peak memory	469592 kb
Host	smart-68d9237d-5818-4eb8-965b-57a4fbfcedd8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510405252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_an d_output.510405252 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.2860288012
Short name	T756
Test name
Test status
Simulation time	44555299439 ps
CPU time	162.15 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:55:18 PM PST 23
Peak memory	231856 kb
Host	smart-fcafe647-0c62-4673-a6f8-10404014017d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860288012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2860288012 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.1221887821
Short name	T1070
Test name
Test status
Simulation time	15226006307 ps
CPU time	67.11 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:53:42 PM PST 23
Peak memory	221848 kb
Host	smart-c3ec8896-6d43-415b-aa63-cf319e82c1f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221887821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1221887821 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all_with_rand_reset.2360126759
Short name	T870
Test name
Test status
Simulation time	151101466256 ps
CPU time	656.14 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 01:03:31 PM PST 23
Peak memory	286892 kb
Host	smart-dddb1ddd-592c-4e79-a112-c7fea091b454
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2360126759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all_with_rand_reset.2360126759 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.2814646497
Short name	T326
Test name
Test status
Simulation time	255816630 ps
CPU time	4.05 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:39 PM PST 23
Peak memory	215576 kb
Host	smart-d6a1fcc7-e826-4659-beb4-2164f52b3a52
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814646497 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.2814646497 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1336075648
Short name	T642
Test name
Test status
Simulation time	304048553 ps
CPU time	4.77 seconds
Started	Dec 24 12:52:37 PM PST 23
Finished	Dec 24 12:52:43 PM PST 23
Peak memory	209016 kb
Host	smart-a9242524-832f-42bb-806b-255700de3a98
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336075648 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1336075648 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.2527932404
Short name	T639
Test name
Test status
Simulation time	198663512225 ps
CPU time	1942.97 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 01:24:58 PM PST 23
Peak memory	377816 kb
Host	smart-7f400d19-2ce3-40e8-a357-5c2a28a1fa46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2527932404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2527932404 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.3383843339
Short name	T243
Test name
Test status
Simulation time	242832107265 ps
CPU time	1721.22 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 01:21:16 PM PST 23
Peak memory	371200 kb
Host	smart-40413a8a-62c6-4fad-a0a6-4e57ae8b6cb6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3383843339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.3383843339 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.2459132553
Short name	T770
Test name
Test status
Simulation time	49077131627 ps
CPU time	1315.26 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 01:14:31 PM PST 23
Peak memory	335396 kb
Host	smart-8757ce76-340f-46b1-9955-0457467ff55a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2459132553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2459132553 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.2780270350
Short name	T183
Test name
Test status
Simulation time	19688906916 ps
CPU time	766.88 seconds
Started	Dec 24 12:52:30 PM PST 23
Finished	Dec 24 01:05:19 PM PST 23
Peak memory	292940 kb
Host	smart-1e4fd9cc-b0fc-47e9-8ade-c643028025a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2780270350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2780270350 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.2691490982
Short name	T1062
Test name
Test status
Simulation time	101246171317 ps
CPU time	3951.84 seconds
Started	Dec 24 12:52:30 PM PST 23
Finished	Dec 24 01:58:25 PM PST 23
Peak memory	644712 kb
Host	smart-ca3c678c-e060-41fb-9eb8-2eb4672701a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2691490982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2691490982 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.2122240760
Short name	T1023
Test name
Test status
Simulation time	180559705472 ps
CPU time	3521.64 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 01:51:16 PM PST 23
Peak memory	561848 kb
Host	smart-696ca80b-6d85-4607-ab3c-b6f98427d710
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2122240760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.2122240760 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.1695301574
Short name	T50
Test name
Test status
Simulation time	14419902 ps
CPU time	0.77 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 12:49:01 PM PST 23
Peak memory	205028 kb
Host	smart-5b81a37e-4bf4-4247-9805-d7c108ff5dfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695301574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1695301574 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.3270523719
Short name	T272
Test name
Test status
Simulation time	14915346308 ps
CPU time	209.19 seconds
Started	Dec 24 12:48:53 PM PST 23
Finished	Dec 24 12:52:24 PM PST 23
Peak memory	239756 kb
Host	smart-be4eb735-a516-4c6c-906b-bdd03b8f1a07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270523719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3270523719 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.2716858896
Short name	T1017
Test name
Test status
Simulation time	3733690660 ps
CPU time	18.9 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	218964 kb
Host	smart-d8948f72-9ac6-4d11-8605-6d7565fa6112
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716858896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2716858896 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.374737226
Short name	T980
Test name
Test status
Simulation time	7742328655 ps
CPU time	103.77 seconds
Started	Dec 24 12:48:48 PM PST 23
Finished	Dec 24 12:50:33 PM PST 23
Peak memory	223644 kb
Host	smart-485c91d6-83c3-4a5b-8f31-fb81ebdadc86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374737226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.374737226 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.4083708258
Short name	T394
Test name
Test status
Simulation time	9229972687 ps
CPU time	47.62 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 12:49:48 PM PST 23
Peak memory	223700 kb
Host	smart-db00a605-c2c3-4d0b-b1ea-7eb6788e4ccc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4083708258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.4083708258 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.208010217
Short name	T744
Test name
Test status
Simulation time	225030672 ps
CPU time	4.63 seconds
Started	Dec 24 12:48:51 PM PST 23
Finished	Dec 24 12:49:02 PM PST 23
Peak memory	215492 kb
Host	smart-ea8cf744-d190-4095-95b3-c276ed42d5de
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=208010217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.208010217 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.2390642574
Short name	T426
Test name
Test status
Simulation time	3728484850 ps
CPU time	5.23 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:49:08 PM PST 23
Peak memory	216720 kb
Host	smart-dc6afbc6-6ebc-49e7-86e2-5f03a7930d46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390642574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2390642574 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.1828659817
Short name	T859
Test name
Test status
Simulation time	7812541955 ps
CPU time	39.47 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 12:49:41 PM PST 23
Peak memory	228612 kb
Host	smart-19db7695-125f-4793-aed6-11fcf8ea0ac0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828659817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1828659817 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.962622658
Short name	T622
Test name
Test status
Simulation time	4294899647 ps
CPU time	84.43 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:50:22 PM PST 23
Peak memory	240380 kb
Host	smart-893308cb-6e51-4da0-9a96-79381b2418bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962622658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.962622658 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.182116301
Short name	T981
Test name
Test status
Simulation time	2958586121 ps
CPU time	4.28 seconds
Started	Dec 24 12:49:05 PM PST 23
Finished	Dec 24 12:49:11 PM PST 23
Peak memory	207356 kb
Host	smart-e40c5765-4a57-47fd-8d62-d2ed49422f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182116301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.182116301 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.2346283283
Short name	T645
Test name
Test status
Simulation time	50201682 ps
CPU time	1.32 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 12:49:06 PM PST 23
Peak memory	215496 kb
Host	smart-1f0d09b3-fae7-45e8-b898-38307cb16248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346283283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2346283283 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.4229985771
Short name	T592
Test name
Test status
Simulation time	5349246016 ps
CPU time	453.34 seconds
Started	Dec 24 12:48:32 PM PST 23
Finished	Dec 24 12:56:07 PM PST 23
Peak memory	267680 kb
Host	smart-b3a183b8-58cf-4a53-adf7-e2ef200d23be
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229985771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.4229985771 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.332776559
Short name	T290
Test name
Test status
Simulation time	5705301203 ps
CPU time	162.16 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:51:40 PM PST 23
Peak memory	237700 kb
Host	smart-6a54d0e5-a965-4927-8fcb-9af2dfd246c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332776559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.332776559 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sideload.4229949044
Short name	T596
Test name
Test status
Simulation time	10513133161 ps
CPU time	271.02 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:53:08 PM PST 23
Peak memory	240652 kb
Host	smart-beda2d73-bc87-4138-a802-2e98b1c5e36d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229949044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.4229949044 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.2158423521
Short name	T868
Test name
Test status
Simulation time	916527762 ps
CPU time	48 seconds
Started	Dec 24 12:48:26 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	223756 kb
Host	smart-b0627770-84c7-4542-9609-f308fa7ee425
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158423521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2158423521 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.2331703575
Short name	T681
Test name
Test status
Simulation time	3550084497 ps
CPU time	257.29 seconds
Started	Dec 24 12:48:44 PM PST 23
Finished	Dec 24 12:53:02 PM PST 23
Peak memory	256944 kb
Host	smart-56ad8108-04dd-400d-8db0-dc4f3ffaf160
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2331703575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2331703575 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_stress_all_with_rand_reset.301027940
Short name	T895
Test name
Test status
Simulation time	55552743243 ps
CPU time	1657.27 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 01:16:52 PM PST 23
Peak memory	348020 kb
Host	smart-052c2a92-ce02-4b4e-971d-684bc5603ca1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=301027940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.301027940 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.3346286428
Short name	T734
Test name
Test status
Simulation time	494143363 ps
CPU time	4.94 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:49:02 PM PST 23
Peak memory	215584 kb
Host	smart-336d600b-1b61-4961-8cd7-44bf2c7984d1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346286428 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.3346286428 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.661171000
Short name	T672
Test name
Test status
Simulation time	217453851 ps
CPU time	4.32 seconds
Started	Dec 24 12:49:11 PM PST 23
Finished	Dec 24 12:49:17 PM PST 23
Peak memory	215792 kb
Host	smart-a2f09a2d-5abf-4ac3-9043-8402c9a00339
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661171000 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.kmac_test_vectors_kmac_xof.661171000 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.3791818200
Short name	T1055
Test name
Test status
Simulation time	98527400948 ps
CPU time	1880.09 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 01:20:19 PM PST 23
Peak memory	393420 kb
Host	smart-75a86618-c711-484e-b2d8-abc4d20a3797
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3791818200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3791818200 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.2253662339
Short name	T74
Test name
Test status
Simulation time	224527235102 ps
CPU time	1713.68 seconds
Started	Dec 24 12:48:53 PM PST 23
Finished	Dec 24 01:17:29 PM PST 23
Peak memory	370804 kb
Host	smart-91135248-3bb3-4e08-b43c-3ac41380e4aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2253662339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2253662339 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.3879703053
Short name	T358
Test name
Test status
Simulation time	191764166631 ps
CPU time	1291.38 seconds
Started	Dec 24 12:48:38 PM PST 23
Finished	Dec 24 01:10:11 PM PST 23
Peak memory	330076 kb
Host	smart-7fb4252c-e030-444b-b9f3-204576a7e87c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3879703053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3879703053 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.758236996
Short name	T941
Test name
Test status
Simulation time	38222176359 ps
CPU time	818.65 seconds
Started	Dec 24 12:48:38 PM PST 23
Finished	Dec 24 01:02:18 PM PST 23
Peak memory	295988 kb
Host	smart-28af1137-56e9-4f2e-a20e-ee11ecf81b87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=758236996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.758236996 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.1762765556
Short name	T273
Test name
Test status
Simulation time	215233874761 ps
CPU time	4078.53 seconds
Started	Dec 24 12:48:36 PM PST 23
Finished	Dec 24 01:56:37 PM PST 23
Peak memory	666956 kb
Host	smart-c01a650d-9489-4176-ae8c-24ebe8c43493
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1762765556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1762765556 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.2708258091
Short name	T807
Test name
Test status
Simulation time	864651880464 ps
CPU time	4325.46 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 02:00:39 PM PST 23
Peak memory	559772 kb
Host	smart-2eb472f4-198e-45c0-9e8e-180d3f7fe769
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2708258091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2708258091 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.3516316952
Short name	T1025
Test name
Test status
Simulation time	134247943 ps
CPU time	0.83 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:52:38 PM PST 23
Peak memory	205388 kb
Host	smart-d747ffe6-60bb-46ac-b08e-209e4847342c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516316952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3516316952 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.1009758454
Short name	T148
Test name
Test status
Simulation time	16973307881 ps
CPU time	91.68 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 12:54:08 PM PST 23
Peak memory	227204 kb
Host	smart-c40ba854-fffc-4e4d-912e-c59d9af1df36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009758454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1009758454 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.2055526265
Short name	T1003
Test name
Test status
Simulation time	7191232249 ps
CPU time	178.51 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:55:36 PM PST 23
Peak memory	224336 kb
Host	smart-62fa17ab-f3d9-40f7-a388-eeda4700d754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055526265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2055526265 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.3983148745
Short name	T740
Test name
Test status
Simulation time	869090637 ps
CPU time	21.85 seconds
Started	Dec 24 12:52:29 PM PST 23
Finished	Dec 24 12:52:53 PM PST 23
Peak memory	223832 kb
Host	smart-0cd5ce77-7c11-4b05-bdf6-218a3213cb67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983148745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3983148745 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.3495234101
Short name	T607
Test name
Test status
Simulation time	2938514624 ps
CPU time	57.91 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:53:34 PM PST 23
Peak memory	240052 kb
Host	smart-37de8273-4a6f-4000-80e8-ac738ac0c874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495234101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3495234101 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.3100459743
Short name	T491
Test name
Test status
Simulation time	3896315594 ps
CPU time	6.53 seconds
Started	Dec 24 12:52:30 PM PST 23
Finished	Dec 24 12:52:39 PM PST 23
Peak memory	207412 kb
Host	smart-abcfc852-7712-4ab6-a112-ddcf813dbcf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100459743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3100459743 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.1213621980
Short name	T612
Test name
Test status
Simulation time	791987578 ps
CPU time	8.45 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:52:46 PM PST 23
Peak memory	216724 kb
Host	smart-655c3f07-ecdb-4205-87cf-8c3e0c99adc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213621980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1213621980 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.2235485851
Short name	T563
Test name
Test status
Simulation time	167100055126 ps
CPU time	1988.47 seconds
Started	Dec 24 12:52:30 PM PST 23
Finished	Dec 24 01:25:41 PM PST 23
Peak memory	410956 kb
Host	smart-7c594467-eb50-4b4e-b049-6668817af444
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235485851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a nd_output.2235485851 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.963040512
Short name	T438
Test name
Test status
Simulation time	32702159169 ps
CPU time	225.83 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 12:56:19 PM PST 23
Peak memory	237964 kb
Host	smart-23402c87-57aa-4de9-bc38-7a2ecb87c685
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963040512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.963040512 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.3247904049
Short name	T162
Test name
Test status
Simulation time	1439066946 ps
CPU time	35.45 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:53:10 PM PST 23
Peak memory	218212 kb
Host	smart-065cd170-d5ee-489f-bebe-03f2cce5914e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247904049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3247904049 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.2773006513
Short name	T293
Test name
Test status
Simulation time	43070845158 ps
CPU time	1202.3 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 01:12:36 PM PST 23
Peak memory	389312 kb
Host	smart-18cbe8ab-fd01-45dd-b530-41d620fb3d62
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2773006513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2773006513 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.2811786413
Short name	T1078
Test name
Test status
Simulation time	27678373418 ps
CPU time	728.73 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 01:04:42 PM PST 23
Peak memory	292960 kb
Host	smart-263281e4-e8f0-4018-975f-b05a50d7d8f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2811786413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.2811786413 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.1784639192
Short name	T637
Test name
Test status
Simulation time	806730791 ps
CPU time	4.85 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:52:42 PM PST 23
Peak memory	215728 kb
Host	smart-37e661e3-5a94-42ba-8c47-d33df66c9a0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784639192 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.1784639192 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.541083803
Short name	T840
Test name
Test status
Simulation time	250191136 ps
CPU time	4.99 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 12:52:37 PM PST 23
Peak memory	215684 kb
Host	smart-60e63d20-c25d-4b39-ba0d-470b761fb815
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541083803 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 40.kmac_test_vectors_kmac_xof.541083803 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.1408195737
Short name	T721
Test name
Test status
Simulation time	39150192581 ps
CPU time	1589.81 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	399488 kb
Host	smart-9cce046a-e5f5-4d3e-b563-5349b1091389
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1408195737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.1408195737 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.2965367272
Short name	T484
Test name
Test status
Simulation time	148439313143 ps
CPU time	1652.15 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 01:20:09 PM PST 23
Peak memory	363932 kb
Host	smart-688074ae-8ce8-4d5c-bd7f-e413c39d1b9f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2965367272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2965367272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.3201659497
Short name	T286
Test name
Test status
Simulation time	82332105709 ps
CPU time	1186.29 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 01:12:23 PM PST 23
Peak memory	342228 kb
Host	smart-d1bda34f-3697-4ec6-a79a-97e9fc616746
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3201659497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3201659497 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.3417584888
Short name	T193
Test name
Test status
Simulation time	31697421595 ps
CPU time	912.59 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 01:07:46 PM PST 23
Peak memory	289088 kb
Host	smart-d6601398-cac6-44dd-a18a-b833cd977d4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3417584888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3417584888 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.4134739883
Short name	T658
Test name
Test status
Simulation time	188643042315 ps
CPU time	4183.07 seconds
Started	Dec 24 12:52:30 PM PST 23
Finished	Dec 24 02:02:16 PM PST 23
Peak memory	651396 kb
Host	smart-8827795a-0a73-44ee-a083-4d8e6641c170
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4134739883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.4134739883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.3540396646
Short name	T995
Test name
Test status
Simulation time	195355551997 ps
CPU time	4005.19 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 01:59:18 PM PST 23
Peak memory	567156 kb
Host	smart-47499060-11a2-49ae-b9b2-bec1e0c894aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3540396646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3540396646 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.1425117777
Short name	T275
Test name
Test status
Simulation time	138434567 ps
CPU time	0.8 seconds
Started	Dec 24 12:52:41 PM PST 23
Finished	Dec 24 12:52:43 PM PST 23
Peak memory	205192 kb
Host	smart-05090c98-5186-4be8-89bc-66b88132af7a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425117777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1425117777 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.1792314862
Short name	T717
Test name
Test status
Simulation time	3660929249 ps
CPU time	173.17 seconds
Started	Dec 24 12:52:44 PM PST 23
Finished	Dec 24 12:55:38 PM PST 23
Peak memory	238264 kb
Host	smart-e35a8869-e753-4d3a-97da-c01a1b0b94cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792314862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1792314862 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.3947647769
Short name	T578
Test name
Test status
Simulation time	14065235500 ps
CPU time	304.44 seconds
Started	Dec 24 12:52:33 PM PST 23
Finished	Dec 24 12:57:45 PM PST 23
Peak memory	227360 kb
Host	smart-838d6467-b66c-46ba-a22b-84d53e885111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947647769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3947647769 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.2121696311
Short name	T30
Test name
Test status
Simulation time	13601942873 ps
CPU time	129.82 seconds
Started	Dec 24 12:52:44 PM PST 23
Finished	Dec 24 12:54:54 PM PST 23
Peak memory	232020 kb
Host	smart-de8b836d-5967-47a7-84d6-be96e2122015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121696311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2121696311 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.174351346
Short name	T522
Test name
Test status
Simulation time	439032044 ps
CPU time	9.95 seconds
Started	Dec 24 12:52:41 PM PST 23
Finished	Dec 24 12:52:52 PM PST 23
Peak memory	221156 kb
Host	smart-fdecd775-190f-4ee6-bf75-eb036998ed0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174351346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.174351346 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.1258681632
Short name	T397
Test name
Test status
Simulation time	299212404 ps
CPU time	1.38 seconds
Started	Dec 24 12:52:40 PM PST 23
Finished	Dec 24 12:52:43 PM PST 23
Peak memory	206688 kb
Host	smart-8187a42e-d531-4634-8ef1-a9279f3b237b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258681632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1258681632 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.3347063887
Short name	T1131
Test name
Test status
Simulation time	62805029 ps
CPU time	1.15 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:36 PM PST 23
Peak memory	215660 kb
Host	smart-2e220492-7837-4aa3-a25f-f094d17e2407
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347063887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3347063887 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.1715074151
Short name	T1042
Test name
Test status
Simulation time	133570567495 ps
CPU time	2551.8 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 01:35:08 PM PST 23
Peak memory	454104 kb
Host	smart-0479d3dd-972d-4a63-9689-4c2030cf3676
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715074151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.1715074151 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.3773843456
Short name	T194
Test name
Test status
Simulation time	29047235702 ps
CPU time	195.82 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 12:55:53 PM PST 23
Peak memory	236460 kb
Host	smart-84d3f152-a5ba-4a29-b003-1d987f841ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773843456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3773843456 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.1079164133
Short name	T751
Test name
Test status
Simulation time	412325205 ps
CPU time	10.92 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 12:52:46 PM PST 23
Peak memory	219232 kb
Host	smart-7c98a3d3-407f-4d16-96c5-2e7e82b86c79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079164133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1079164133 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.2151340995
Short name	T282
Test name
Test status
Simulation time	9944647716 ps
CPU time	210.45 seconds
Started	Dec 24 12:52:44 PM PST 23
Finished	Dec 24 12:56:15 PM PST 23
Peak memory	253900 kb
Host	smart-d1755b1b-318d-4ad9-883f-9a6c9082c2da
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2151340995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2151340995 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.1149187528
Short name	T17
Test name
Test status
Simulation time	666775182 ps
CPU time	4.86 seconds
Started	Dec 24 12:52:31 PM PST 23
Finished	Dec 24 12:52:38 PM PST 23
Peak memory	215504 kb
Host	smart-1d4feb65-7c41-44a8-a88e-30057ab7a23c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149187528 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.1149187528 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3325203461
Short name	T772
Test name
Test status
Simulation time	133770805 ps
CPU time	3.95 seconds
Started	Dec 24 12:52:49 PM PST 23
Finished	Dec 24 12:52:54 PM PST 23
Peak memory	215684 kb
Host	smart-344c616a-17ae-4571-9888-339928c26522
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325203461 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3325203461 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.4175666536
Short name	T962
Test name
Test status
Simulation time	84248048051 ps
CPU time	1773.44 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 01:22:11 PM PST 23
Peak memory	377280 kb
Host	smart-7687298b-dfe9-4d3b-9269-bee72d09fde6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4175666536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.4175666536 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.1671755674
Short name	T1114
Test name
Test status
Simulation time	63741327274 ps
CPU time	1783.09 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 01:22:20 PM PST 23
Peak memory	374328 kb
Host	smart-ece3dce4-22a3-4c1a-9f01-4ba7b16be911
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1671755674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1671755674 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.2994269894
Short name	T828
Test name
Test status
Simulation time	102258415387 ps
CPU time	1324.83 seconds
Started	Dec 24 12:52:34 PM PST 23
Finished	Dec 24 01:14:42 PM PST 23
Peak memory	334804 kb
Host	smart-e9d6c17b-503d-4c0e-8783-1f2377b6f9e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2994269894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2994269894 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.3212727443
Short name	T1102
Test name
Test status
Simulation time	75405645171 ps
CPU time	910.01 seconds
Started	Dec 24 12:52:39 PM PST 23
Finished	Dec 24 01:07:50 PM PST 23
Peak memory	293312 kb
Host	smart-57ac5cc3-4cf4-4be1-93b0-43da3a5f5a5f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3212727443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3212727443 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.2237407714
Short name	T580
Test name
Test status
Simulation time	52291208240 ps
CPU time	4017.23 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 01:59:35 PM PST 23
Peak memory	647356 kb
Host	smart-42c76d91-5290-45c3-8a48-23335361f456
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2237407714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.2237407714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.3796964801
Short name	T373
Test name
Test status
Simulation time	2113940811286 ps
CPU time	4063.74 seconds
Started	Dec 24 12:52:35 PM PST 23
Finished	Dec 24 02:00:21 PM PST 23
Peak memory	570712 kb
Host	smart-4c0f31d6-b87b-418d-9e56-e405b3b6d728
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3796964801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.3796964801 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.1872567847
Short name	T1135
Test name
Test status
Simulation time	29701420 ps
CPU time	0.81 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 12:53:07 PM PST 23
Peak memory	205220 kb
Host	smart-3345932f-f5d2-48b9-9716-c75d2e525145
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872567847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1872567847 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.3764049983
Short name	T1046
Test name
Test status
Simulation time	1587452565 ps
CPU time	69.03 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:54:14 PM PST 23
Peak memory	225848 kb
Host	smart-009df506-9510-4e42-b5bd-9f0a3ce91866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764049983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3764049983 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.2379572778
Short name	T1098
Test name
Test status
Simulation time	21919825817 ps
CPU time	409.21 seconds
Started	Dec 24 12:52:40 PM PST 23
Finished	Dec 24 12:59:31 PM PST 23
Peak memory	230388 kb
Host	smart-6f852bd2-204d-4343-a97c-7d969cc35eb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379572778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2379572778 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.258827376
Short name	T698
Test name
Test status
Simulation time	5641667648 ps
CPU time	131.4 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:55:22 PM PST 23
Peak memory	236152 kb
Host	smart-aac6170a-fae5-4bda-a655-74fb2b3b817d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258827376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.258827376 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_error.2308827769
Short name	T452
Test name
Test status
Simulation time	52265822880 ps
CPU time	243.17 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 12:57:15 PM PST 23
Peak memory	256012 kb
Host	smart-d5ef40b4-56e0-42ca-8ea2-a1f407bcd76e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308827769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2308827769 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/42.kmac_key_error.2603017912
Short name	T706
Test name
Test status
Simulation time	588024105 ps
CPU time	3.38 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 12:53:15 PM PST 23
Peak memory	207252 kb
Host	smart-316e4594-d7a0-43bb-8923-f549c1f1efa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603017912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2603017912 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.1793993373
Short name	T663
Test name
Test status
Simulation time	34869094 ps
CPU time	1.17 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:53:11 PM PST 23
Peak memory	215724 kb
Host	smart-53a65d17-6ec8-4221-94d5-5d87cc4f0906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793993373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1793993373 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.677356765
Short name	T1013
Test name
Test status
Simulation time	112140051591 ps
CPU time	2434.13 seconds
Started	Dec 24 12:52:32 PM PST 23
Finished	Dec 24 01:33:09 PM PST 23
Peak memory	443280 kb
Host	smart-d036022f-ade7-4ec6-b739-492e0899e583
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677356765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an d_output.677356765 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.203299121
Short name	T514
Test name
Test status
Simulation time	50363044788 ps
CPU time	332.03 seconds
Started	Dec 24 12:52:38 PM PST 23
Finished	Dec 24 12:58:11 PM PST 23
Peak memory	243724 kb
Host	smart-8e94e6a5-031a-4ac0-bffe-467327344b03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203299121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.203299121 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.3260322865
Short name	T505
Test name
Test status
Simulation time	6814827897 ps
CPU time	48.62 seconds
Started	Dec 24 12:52:39 PM PST 23
Finished	Dec 24 12:53:28 PM PST 23
Peak memory	223800 kb
Host	smart-c0e7b7e6-4168-4521-b949-559e87980841
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260322865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3260322865 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.842325121
Short name	T843
Test name
Test status
Simulation time	170604692 ps
CPU time	4.56 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:53:14 PM PST 23
Peak memory	215712 kb
Host	smart-72ac7025-4262-4a67-9adc-66c58759a494
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=842325121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.842325121 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.93140843
Short name	T1010
Test name
Test status
Simulation time	168554981 ps
CPU time	4.32 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:08 PM PST 23
Peak memory	209036 kb
Host	smart-f1615e90-1959-4165-bb7b-ea869369a215
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93140843 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 42.kmac_test_vectors_kmac.93140843 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2993049653
Short name	T711
Test name
Test status
Simulation time	657809382 ps
CPU time	4.42 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:08 PM PST 23
Peak memory	215612 kb
Host	smart-8834c296-988d-499c-b96e-36d698eea3eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993049653 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2993049653 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.1864437062
Short name	T778
Test name
Test status
Simulation time	595396655128 ps
CPU time	1964.58 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 01:25:49 PM PST 23
Peak memory	377116 kb
Host	smart-e3c4be28-887f-47c9-bd1e-a9742cf0a2ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1864437062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1864437062 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.752453319
Short name	T251
Test name
Test status
Simulation time	134265045389 ps
CPU time	1452.69 seconds
Started	Dec 24 12:53:07 PM PST 23
Finished	Dec 24 01:17:24 PM PST 23
Peak memory	367952 kb
Host	smart-d83222dd-e774-47f5-af65-6bf1e8696cea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=752453319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.752453319 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.827521967
Short name	T823
Test name
Test status
Simulation time	16549183379 ps
CPU time	1150.71 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 01:12:16 PM PST 23
Peak memory	340596 kb
Host	smart-12263a1c-bdd8-4682-b7b5-a552e952d1c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=827521967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.827521967 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.518739104
Short name	T341
Test name
Test status
Simulation time	36025187682 ps
CPU time	741.84 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 01:05:28 PM PST 23
Peak memory	291692 kb
Host	smart-c97af952-c043-4c6a-9539-1e037fc033d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=518739104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.518739104 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.4030468991
Short name	T145
Test name
Test status
Simulation time	103579803967 ps
CPU time	4010.09 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:59:58 PM PST 23
Peak memory	648168 kb
Host	smart-e2ded43b-2bd4-41b4-a641-bdc6f9fabc61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4030468991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.4030468991 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.3879484619
Short name	T439
Test name
Test status
Simulation time	243577964686 ps
CPU time	4068.57 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 02:00:54 PM PST 23
Peak memory	568712 kb
Host	smart-198921a7-4923-42ad-849b-39fd7b1c8ad7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3879484619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.3879484619 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.3088532010
Short name	T419
Test name
Test status
Simulation time	26666950 ps
CPU time	0.79 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 12:53:07 PM PST 23
Peak memory	205168 kb
Host	smart-78391df3-28f5-4eb4-8e92-09cdc763d9c9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088532010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3088532010 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.3278082179
Short name	T35
Test name
Test status
Simulation time	620403861 ps
CPU time	24.68 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:29 PM PST 23
Peak memory	223868 kb
Host	smart-e6c6f364-7f03-4979-b09d-8228a576ea67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278082179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3278082179 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.299638094
Short name	T632
Test name
Test status
Simulation time	61057886830 ps
CPU time	323.32 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 12:58:29 PM PST 23
Peak memory	226796 kb
Host	smart-5957fec9-bc49-4934-af9a-592dc03df654
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299638094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.299638094 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.452197060
Short name	T661
Test name
Test status
Simulation time	19537379949 ps
CPU time	284.76 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 12:57:52 PM PST 23
Peak memory	243184 kb
Host	smart-9f21d6c7-9db0-4f9d-b3b6-fc77a8432692
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452197060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.452197060 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.1128779915
Short name	T551
Test name
Test status
Simulation time	9952903999 ps
CPU time	22.23 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:27 PM PST 23
Peak memory	223988 kb
Host	smart-ba4e7bb0-405a-4be3-a74c-9c8ec1263f4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128779915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1128779915 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.3293426551
Short name	T315
Test name
Test status
Simulation time	96754375 ps
CPU time	1.31 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 12:53:13 PM PST 23
Peak memory	207084 kb
Host	smart-dd098606-f9f3-4585-ba23-c606a4866583
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293426551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3293426551 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.202585325
Short name	T1041
Test name
Test status
Simulation time	77212499 ps
CPU time	1.27 seconds
Started	Dec 24 12:53:11 PM PST 23
Finished	Dec 24 12:53:15 PM PST 23
Peak memory	215632 kb
Host	smart-f5bd621b-c69d-4f6a-90ad-a5e9cfeeff87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202585325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.202585325 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.3872475481
Short name	T1125
Test name
Test status
Simulation time	1653361279 ps
CPU time	129.78 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:55:20 PM PST 23
Peak memory	230108 kb
Host	smart-809b101d-0cb8-4908-99b5-e329d3e1b04e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872475481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.3872475481 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.2918180058
Short name	T1031
Test name
Test status
Simulation time	85950598887 ps
CPU time	429.7 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 01:00:16 PM PST 23
Peak memory	249552 kb
Host	smart-b1b06c63-a7d8-42c1-8ca8-7172231a1edc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918180058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2918180058 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.4117033375
Short name	T69
Test name
Test status
Simulation time	3183207053 ps
CPU time	51.8 seconds
Started	Dec 24 12:53:01 PM PST 23
Finished	Dec 24 12:53:54 PM PST 23
Peak memory	223920 kb
Host	smart-69e7647d-d8c2-49e6-bbfd-8275a9d1270b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117033375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.4117033375 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.2937718991
Short name	T1066
Test name
Test status
Simulation time	127411923263 ps
CPU time	1088.13 seconds
Started	Dec 24 12:53:10 PM PST 23
Finished	Dec 24 01:11:21 PM PST 23
Peak memory	390376 kb
Host	smart-47f9fc5a-3637-4244-bfa9-c8255dfe718b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2937718991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2937718991 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_stress_all_with_rand_reset.719362935
Short name	T1021
Test name
Test status
Simulation time	135158395111 ps
CPU time	1339.15 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:15:26 PM PST 23
Peak memory	336372 kb
Host	smart-40ab0b3f-8d80-40fc-999f-a7dcbb3db301
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=719362935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.719362935 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.1451581022
Short name	T1005
Test name
Test status
Simulation time	685344075 ps
CPU time	4.66 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:09 PM PST 23
Peak memory	215648 kb
Host	smart-888cbd1a-53c2-40b8-8599-539eb49c937b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451581022 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.1451581022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1174076697
Short name	T1099
Test name
Test status
Simulation time	416003858 ps
CPU time	4.29 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 12:53:10 PM PST 23
Peak memory	208912 kb
Host	smart-2aa08965-b79f-41f6-9923-17c41052dbcd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174076697 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1174076697 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.1730377717
Short name	T472
Test name
Test status
Simulation time	67025764422 ps
CPU time	1816.48 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 01:23:27 PM PST 23
Peak memory	395936 kb
Host	smart-431b8eca-5f6d-4c56-8010-9fc84dbf17f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1730377717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.1730377717 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.3575066935
Short name	T334
Test name
Test status
Simulation time	121139207773 ps
CPU time	1483.47 seconds
Started	Dec 24 12:53:10 PM PST 23
Finished	Dec 24 01:17:56 PM PST 23
Peak memory	361604 kb
Host	smart-b46336cd-e399-43ad-bc2a-edb351c069dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3575066935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3575066935 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.1374794819
Short name	T1061
Test name
Test status
Simulation time	48642670562 ps
CPU time	1292.46 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 01:14:43 PM PST 23
Peak memory	329916 kb
Host	smart-f759114c-eea1-4d56-9929-79d288469c56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1374794819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.1374794819 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.1624952154
Short name	T417
Test name
Test status
Simulation time	367840925044 ps
CPU time	945.33 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:08:52 PM PST 23
Peak memory	297784 kb
Host	smart-53917c0c-3ecb-41a6-9ba9-cdcd191cee82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1624952154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1624952154 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.159517699
Short name	T1080
Test name
Test status
Simulation time	718232646560 ps
CPU time	4730.52 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 02:12:00 PM PST 23
Peak memory	652700 kb
Host	smart-7f269c67-242f-4eba-93d2-8f8d29380301
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=159517699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.159517699 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.4137727806
Short name	T227
Test name
Test status
Simulation time	44503029245 ps
CPU time	3494.63 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 01:51:21 PM PST 23
Peak memory	567828 kb
Host	smart-2f9b2d6a-0ad9-449f-85ce-cbf3ed71e530
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4137727806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.4137727806 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.2009232641
Short name	T288
Test name
Test status
Simulation time	54276157 ps
CPU time	0.82 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 12:53:13 PM PST 23
Peak memory	205092 kb
Host	smart-de9bcf7b-adc3-48c3-ade6-d10aa1e55f22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009232641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2009232641 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.1332294741
Short name	T1051
Test name
Test status
Simulation time	31902103561 ps
CPU time	145.62 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:55:30 PM PST 23
Peak memory	232924 kb
Host	smart-87dd7770-7116-42fa-b773-4d8d9ec73522
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332294741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1332294741 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.2942561755
Short name	T1087
Test name
Test status
Simulation time	7262164572 ps
CPU time	29.67 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 12:53:37 PM PST 23
Peak memory	215780 kb
Host	smart-d9e20c84-b82e-4fb1-9cc1-3c543b8b683e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942561755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2942561755 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.1252407588
Short name	T805
Test name
Test status
Simulation time	6560503033 ps
CPU time	48.5 seconds
Started	Dec 24 12:53:17 PM PST 23
Finished	Dec 24 12:54:06 PM PST 23
Peak memory	223508 kb
Host	smart-c60b5639-549f-4866-9f90-9e56988fb536
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252407588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1252407588 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.196730665
Short name	T766
Test name
Test status
Simulation time	6098992404 ps
CPU time	239.33 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:57:09 PM PST 23
Peak memory	255240 kb
Host	smart-8a95b892-0c4f-4a1d-abbf-c66e15746f38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196730665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.196730665 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.885375712
Short name	T62
Test name
Test status
Simulation time	2433822054 ps
CPU time	3.77 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:08 PM PST 23
Peak memory	207376 kb
Host	smart-b04c334e-77a4-4268-9736-ff9c06815274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885375712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.885375712 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.4000711461
Short name	T60
Test name
Test status
Simulation time	83968822 ps
CPU time	1.41 seconds
Started	Dec 24 12:53:07 PM PST 23
Finished	Dec 24 12:53:12 PM PST 23
Peak memory	215520 kb
Host	smart-4c383978-c4b5-49e3-8dcc-8bfdfa2be635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000711461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4000711461 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.2652446773
Short name	T936
Test name
Test status
Simulation time	27984670797 ps
CPU time	923.91 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:08:32 PM PST 23
Peak memory	318144 kb
Host	smart-ddc341c9-25e0-4cbf-adfa-632f1818eb80
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652446773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.2652446773 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.2732893256
Short name	T780
Test name
Test status
Simulation time	933521501 ps
CPU time	66.56 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 12:54:12 PM PST 23
Peak memory	224324 kb
Host	smart-347bce21-b38a-48e8-9cd1-bb8cac0f3a8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732893256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2732893256 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.1878649485
Short name	T643
Test name
Test status
Simulation time	1322061845 ps
CPU time	38.52 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 12:53:46 PM PST 23
Peak memory	218880 kb
Host	smart-6dd3adc9-c9fe-4de5-adfd-69a874c69b7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878649485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1878649485 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.3512125681
Short name	T882
Test name
Test status
Simulation time	19891965659 ps
CPU time	516.71 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:01:44 PM PST 23
Peak memory	298004 kb
Host	smart-7abce3ed-f60e-48cd-bc94-64bde6c8ffe9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3512125681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3512125681 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_stress_all_with_rand_reset.1799394721
Short name	T969
Test name
Test status
Simulation time	591013713195 ps
CPU time	1809.37 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 01:23:20 PM PST 23
Peak memory	370384 kb
Host	smart-766a9deb-4043-497c-b9f3-a3e9ba85eca8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1799394721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all_with_rand_reset.1799394721 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.374377906
Short name	T312
Test name
Test status
Simulation time	1032067519 ps
CPU time	5.37 seconds
Started	Dec 24 12:53:07 PM PST 23
Finished	Dec 24 12:53:16 PM PST 23
Peak memory	208480 kb
Host	smart-36efa891-d53a-4220-aa6d-83c42f0fa335
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374377906 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.kmac_test_vectors_kmac.374377906 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.29896942
Short name	T515
Test name
Test status
Simulation time	504023205 ps
CPU time	4.73 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 12:53:12 PM PST 23
Peak memory	215704 kb
Host	smart-3df55a01-9881-449a-97cb-5fc93d0baeae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29896942 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.kmac_test_vectors_kmac_xof.29896942 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.1884039175
Short name	T324
Test name
Test status
Simulation time	379365722214 ps
CPU time	1877.8 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 01:24:22 PM PST 23
Peak memory	388756 kb
Host	smart-e8964483-3be8-40a0-a4be-992c2350397b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1884039175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.1884039175 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.2930491868
Short name	T189
Test name
Test status
Simulation time	17849644371 ps
CPU time	1455.05 seconds
Started	Dec 24 12:53:02 PM PST 23
Finished	Dec 24 01:17:18 PM PST 23
Peak memory	376224 kb
Host	smart-2d5382eb-3445-451e-8cd3-de74ed184c40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2930491868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2930491868 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.3564952274
Short name	T846
Test name
Test status
Simulation time	123692360496 ps
CPU time	1241.91 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 01:13:52 PM PST 23
Peak memory	327944 kb
Host	smart-020be81c-5950-4315-90bf-621eac1f99e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3564952274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3564952274 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.1522896022
Short name	T535
Test name
Test status
Simulation time	282842909041 ps
CPU time	1014 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 01:10:04 PM PST 23
Peak memory	291776 kb
Host	smart-f6aaaea6-86e4-4327-b6d0-ca797706bcbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1522896022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1522896022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.3650730505
Short name	T363
Test name
Test status
Simulation time	74800142525 ps
CPU time	4084.45 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 02:01:15 PM PST 23
Peak memory	650548 kb
Host	smart-a08328d0-1898-4de4-80b0-87cdf0940b09
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3650730505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3650730505 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.840597535
Short name	T1103
Test name
Test status
Simulation time	273897788212 ps
CPU time	3515.51 seconds
Started	Dec 24 12:53:04 PM PST 23
Finished	Dec 24 01:51:42 PM PST 23
Peak memory	572532 kb
Host	smart-4f47a7dd-9fd3-44f1-940b-b0ec4c72b158
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=840597535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.840597535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.2752365998
Short name	T561
Test name
Test status
Simulation time	54088052 ps
CPU time	0.81 seconds
Started	Dec 24 12:53:17 PM PST 23
Finished	Dec 24 12:53:18 PM PST 23
Peak memory	205184 kb
Host	smart-eed8910b-de9a-4b8e-83e7-9fb67446ff4c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752365998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2752365998 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.2724059616
Short name	T690
Test name
Test status
Simulation time	6406838283 ps
CPU time	89.29 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 12:54:41 PM PST 23
Peak memory	228952 kb
Host	smart-2b12f2d6-8925-4f9b-879b-2cf76d5e26e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724059616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2724059616 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.2310533272
Short name	T527
Test name
Test status
Simulation time	5640416398 ps
CPU time	474.35 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 01:01:06 PM PST 23
Peak memory	230344 kb
Host	smart-bc448954-4652-4a69-8ff8-bafc7ed14958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310533272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2310533272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.4100194063
Short name	T753
Test name
Test status
Simulation time	13898056695 ps
CPU time	18.55 seconds
Started	Dec 24 12:53:11 PM PST 23
Finished	Dec 24 12:53:32 PM PST 23
Peak memory	223588 kb
Host	smart-6b66c794-be2b-4a78-ac11-652cccc52a94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100194063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.4100194063 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_key_error.2996400721
Short name	T655
Test name
Test status
Simulation time	3113366014 ps
CPU time	2.83 seconds
Started	Dec 24 12:53:11 PM PST 23
Finished	Dec 24 12:53:16 PM PST 23
Peak memory	207048 kb
Host	smart-e8e08f70-7e55-45ae-b5f7-f8211ce95c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996400721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2996400721 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.1914456757
Short name	T548
Test name
Test status
Simulation time	383210759 ps
CPU time	1.37 seconds
Started	Dec 24 12:53:07 PM PST 23
Finished	Dec 24 12:53:12 PM PST 23
Peak memory	215616 kb
Host	smart-0b283f2d-87ef-4351-a145-4bf4af76a11b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914456757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1914456757 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.2675077037
Short name	T185
Test name
Test status
Simulation time	29803066295 ps
CPU time	1150.35 seconds
Started	Dec 24 12:53:10 PM PST 23
Finished	Dec 24 01:12:23 PM PST 23
Peak memory	352840 kb
Host	smart-7ef4bf2f-e1d9-4cf2-a1ab-99c01464a183
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675077037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.2675077037 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.4159163736
Short name	T4
Test name
Test status
Simulation time	13231006578 ps
CPU time	308.84 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 12:58:19 PM PST 23
Peak memory	243388 kb
Host	smart-b758830b-1014-47bc-90ff-99a4232797be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159163736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.4159163736 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.4109879720
Short name	T813
Test name
Test status
Simulation time	508153207 ps
CPU time	11.74 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 12:53:17 PM PST 23
Peak memory	219804 kb
Host	smart-3c17b625-8196-4a6c-8b39-8172e9416152
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109879720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4109879720 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.1085761302
Short name	T364
Test name
Test status
Simulation time	65088923442 ps
CPU time	1411.16 seconds
Started	Dec 24 12:53:06 PM PST 23
Finished	Dec 24 01:16:41 PM PST 23
Peak memory	379196 kb
Host	smart-7e4f9a97-773e-4f1e-8f37-9a1cc8572426
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1085761302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1085761302 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.2300608406
Short name	T28
Test name
Test status
Simulation time	51698580267 ps
CPU time	420.83 seconds
Started	Dec 24 12:53:10 PM PST 23
Finished	Dec 24 01:00:13 PM PST 23
Peak memory	256360 kb
Host	smart-59eca40f-9e09-45f1-958b-ae51aa2a9a95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2300608406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.2300608406 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.2127270866
Short name	T910
Test name
Test status
Simulation time	66463237 ps
CPU time	3.74 seconds
Started	Dec 24 12:53:15 PM PST 23
Finished	Dec 24 12:53:19 PM PST 23
Peak memory	215756 kb
Host	smart-e74d9631-89df-4473-82a4-3153f4794cc5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127270866 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.2127270866 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1454747211
Short name	T646
Test name
Test status
Simulation time	903143819 ps
CPU time	4.47 seconds
Started	Dec 24 12:53:14 PM PST 23
Finished	Dec 24 12:53:19 PM PST 23
Peak memory	215776 kb
Host	smart-718a6df9-8925-44d7-999a-dde374979c38
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454747211 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1454747211 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.1406626047
Short name	T666
Test name
Test status
Simulation time	313354328732 ps
CPU time	1675.53 seconds
Started	Dec 24 12:53:10 PM PST 23
Finished	Dec 24 01:21:08 PM PST 23
Peak memory	390900 kb
Host	smart-bbf61b10-5db0-4fa8-b85a-91f6f23827dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1406626047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.1406626047 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.980405077
Short name	T784
Test name
Test status
Simulation time	97526404005 ps
CPU time	1879.63 seconds
Started	Dec 24 12:53:03 PM PST 23
Finished	Dec 24 01:24:23 PM PST 23
Peak memory	374280 kb
Host	smart-e4ddac5c-d534-4135-8445-e2adbd437efd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=980405077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.980405077 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.1599852759
Short name	T291
Test name
Test status
Simulation time	301747800308 ps
CPU time	1391.94 seconds
Started	Dec 24 12:53:08 PM PST 23
Finished	Dec 24 01:16:23 PM PST 23
Peak memory	331536 kb
Host	smart-34129edf-101a-41c6-91d0-b5664dfa7a2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1599852759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.1599852759 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.2723828972
Short name	T381
Test name
Test status
Simulation time	9719558588 ps
CPU time	761.36 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:05:48 PM PST 23
Peak memory	290624 kb
Host	smart-269108c2-7ce8-45e9-8771-1c4a7f0f2618
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2723828972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.2723828972 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.252857185
Short name	T606
Test name
Test status
Simulation time	164147425016 ps
CPU time	3876.19 seconds
Started	Dec 24 12:53:05 PM PST 23
Finished	Dec 24 01:57:43 PM PST 23
Peak memory	650768 kb
Host	smart-209a9949-bb39-4ba1-8932-025b202e75b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=252857185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.252857185 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.3598189519
Short name	T254
Test name
Test status
Simulation time	1473474068316 ps
CPU time	4378.34 seconds
Started	Dec 24 12:53:11 PM PST 23
Finished	Dec 24 02:06:12 PM PST 23
Peak memory	571976 kb
Host	smart-de62bc04-8201-43f1-a523-fb87a3799882
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3598189519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3598189519 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.679762890
Short name	T745
Test name
Test status
Simulation time	16271898 ps
CPU time	0.81 seconds
Started	Dec 24 12:53:44 PM PST 23
Finished	Dec 24 12:53:51 PM PST 23
Peak memory	205104 kb
Host	smart-c145cab2-19c1-4b58-b21a-f9b8b9b4a6fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679762890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.679762890 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.544696960
Short name	T697
Test name
Test status
Simulation time	17895376946 ps
CPU time	160.91 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 12:56:31 PM PST 23
Peak memory	233140 kb
Host	smart-6800c3e5-e7aa-4098-afac-e5d75cccf76c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544696960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.544696960 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.2123603058
Short name	T852
Test name
Test status
Simulation time	11826324175 ps
CPU time	339.39 seconds
Started	Dec 24 12:53:52 PM PST 23
Finished	Dec 24 12:59:36 PM PST 23
Peak memory	228384 kb
Host	smart-0884bebd-b393-4453-ba49-cd5842420fe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123603058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2123603058 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.3780089112
Short name	T653
Test name
Test status
Simulation time	26160685690 ps
CPU time	91.71 seconds
Started	Dec 24 12:53:47 PM PST 23
Finished	Dec 24 12:55:24 PM PST 23
Peak memory	227300 kb
Host	smart-d52c9e42-b34c-4733-b1a4-7654a5149010
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780089112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3780089112 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.2052255673
Short name	T1110
Test name
Test status
Simulation time	8078469064 ps
CPU time	161.02 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 12:56:31 PM PST 23
Peak memory	240300 kb
Host	smart-a5d97417-44e9-47bb-b68d-b0f6bdc9d7c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052255673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2052255673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.3110718128
Short name	T470
Test name
Test status
Simulation time	9497446487 ps
CPU time	6.14 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 12:53:56 PM PST 23
Peak memory	207428 kb
Host	smart-b70f8be5-9fba-4650-b66a-50083ec924a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110718128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3110718128 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.2732423890
Short name	T696
Test name
Test status
Simulation time	32758668 ps
CPU time	1.36 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 12:53:51 PM PST 23
Peak memory	216744 kb
Host	smart-233575eb-3333-4c00-afdc-eee8c15068d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732423890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2732423890 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.607424859
Short name	T398
Test name
Test status
Simulation time	73509675173 ps
CPU time	1661.27 seconds
Started	Dec 24 12:53:46 PM PST 23
Finished	Dec 24 01:21:32 PM PST 23
Peak memory	412424 kb
Host	smart-d0a7b594-9423-4a66-b0c0-48e9109ccd79
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607424859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an d_output.607424859 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.3480731877
Short name	T350
Test name
Test status
Simulation time	37383082083 ps
CPU time	221.33 seconds
Started	Dec 24 12:53:40 PM PST 23
Finished	Dec 24 12:57:28 PM PST 23
Peak memory	237620 kb
Host	smart-38a33cd5-be2f-4f69-b89d-6a10d7137a39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480731877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3480731877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.519044418
Short name	T789
Test name
Test status
Simulation time	6731578840 ps
CPU time	43.25 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 12:54:33 PM PST 23
Peak memory	223876 kb
Host	smart-24065427-fa44-4c48-8ece-71553859408b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519044418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.519044418 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.3224357027
Short name	T809
Test name
Test status
Simulation time	300835145501 ps
CPU time	1934.04 seconds
Started	Dec 24 12:53:44 PM PST 23
Finished	Dec 24 01:26:04 PM PST 23
Peak memory	461900 kb
Host	smart-7d7ab069-1fa9-44c0-8750-65e6074a1e1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3224357027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3224357027 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_stress_all_with_rand_reset.623447552
Short name	T37
Test name
Test status
Simulation time	225198416175 ps
CPU time	1436.61 seconds
Started	Dec 24 12:53:40 PM PST 23
Finished	Dec 24 01:17:44 PM PST 23
Peak memory	327072 kb
Host	smart-1bc5fb5a-c619-4cbe-9225-78ba291e8515
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=623447552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all_with_rand_reset.623447552 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.743407591
Short name	T210
Test name
Test status
Simulation time	384301109 ps
CPU time	4.41 seconds
Started	Dec 24 12:53:50 PM PST 23
Finished	Dec 24 12:54:01 PM PST 23
Peak memory	215688 kb
Host	smart-a0082ee6-79a8-4a3c-bf83-465ddfe95624
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743407591 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.kmac_test_vectors_kmac.743407591 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.3774101403
Short name	T348
Test name
Test status
Simulation time	332682947 ps
CPU time	4.34 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 12:53:54 PM PST 23
Peak memory	208572 kb
Host	smart-abc0dc0d-4e2c-4572-8e84-3ca531439b3c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774101403 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.3774101403 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.299836062
Short name	T693
Test name
Test status
Simulation time	19977776684 ps
CPU time	1636.55 seconds
Started	Dec 24 12:53:41 PM PST 23
Finished	Dec 24 01:21:04 PM PST 23
Peak memory	394900 kb
Host	smart-f952ef1f-68b2-478f-8bdf-1189849a1132
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=299836062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.299836062 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.2373849067
Short name	T938
Test name
Test status
Simulation time	176349317391 ps
CPU time	1859.54 seconds
Started	Dec 24 12:53:47 PM PST 23
Finished	Dec 24 01:24:53 PM PST 23
Peak memory	374768 kb
Host	smart-3b590ace-500f-436d-a842-c7476a9059db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2373849067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.2373849067 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.2506719893
Short name	T1097
Test name
Test status
Simulation time	47850995820 ps
CPU time	1201.78 seconds
Started	Dec 24 12:53:46 PM PST 23
Finished	Dec 24 01:13:53 PM PST 23
Peak memory	328652 kb
Host	smart-0ff5ad4f-91ef-4c49-ac7a-d09890164195
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2506719893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2506719893 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.2447820888
Short name	T566
Test name
Test status
Simulation time	176337325669 ps
CPU time	940.24 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 01:09:30 PM PST 23
Peak memory	294796 kb
Host	smart-da901d72-5e5f-4e9d-9f54-d78494694d4c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2447820888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2447820888 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.1033405040
Short name	T1045
Test name
Test status
Simulation time	92168942333 ps
CPU time	4311.69 seconds
Started	Dec 24 12:53:47 PM PST 23
Finished	Dec 24 02:05:45 PM PST 23
Peak memory	665472 kb
Host	smart-d89a948e-24cc-479c-92fd-586943cd9101
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1033405040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1033405040 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.3336093100
Short name	T368
Test name
Test status
Simulation time	3649755504014 ps
CPU time	5504.78 seconds
Started	Dec 24 12:53:50 PM PST 23
Finished	Dec 24 02:25:41 PM PST 23
Peak memory	569468 kb
Host	smart-bb09f3a4-b177-4bd9-ba0c-7c9b0459a4a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3336093100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.3336093100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.1079021464
Short name	T242
Test name
Test status
Simulation time	20755027 ps
CPU time	0.79 seconds
Started	Dec 24 12:53:50 PM PST 23
Finished	Dec 24 12:53:57 PM PST 23
Peak memory	205204 kb
Host	smart-1f00e956-9bd4-4bef-b9f4-16fbc532ba5f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079021464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1079021464 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.3705946626
Short name	T111
Test name
Test status
Simulation time	8880006433 ps
CPU time	49.53 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 12:54:40 PM PST 23
Peak memory	223888 kb
Host	smart-90f5d8fe-0af1-4cbd-a9b7-996ef8ad9eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705946626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3705946626 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.1877206394
Short name	T230
Test name
Test status
Simulation time	20809759041 ps
CPU time	197.19 seconds
Started	Dec 24 12:53:44 PM PST 23
Finished	Dec 24 12:57:07 PM PST 23
Peak memory	224808 kb
Host	smart-998b8614-02b3-464d-b53f-d7662d60d065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877206394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1877206394 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.880350107
Short name	T423
Test name
Test status
Simulation time	600718119 ps
CPU time	33.25 seconds
Started	Dec 24 12:53:44 PM PST 23
Finished	Dec 24 12:54:23 PM PST 23
Peak memory	221444 kb
Host	smart-3d71136f-4e62-42b1-9475-18858e08c11b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880350107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.880350107 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.1207152880
Short name	T48
Test name
Test status
Simulation time	15951779258 ps
CPU time	87.22 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 12:55:17 PM PST 23
Peak memory	240240 kb
Host	smart-d8071f0f-8818-42c9-bb75-318230e53a67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207152880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1207152880 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.2697325287
Short name	T63
Test name
Test status
Simulation time	1933117359 ps
CPU time	5.65 seconds
Started	Dec 24 12:53:44 PM PST 23
Finished	Dec 24 12:53:56 PM PST 23
Peak memory	207208 kb
Host	smart-c5141ea8-925e-4158-9b72-1152a883404a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697325287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2697325287 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.3795610430
Short name	T616
Test name
Test status
Simulation time	103792719 ps
CPU time	1.27 seconds
Started	Dec 24 12:53:47 PM PST 23
Finished	Dec 24 12:53:54 PM PST 23
Peak memory	215596 kb
Host	smart-88d77ce3-ccef-4586-9f41-e2cec43338f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795610430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3795610430 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.3428115951
Short name	T1037
Test name
Test status
Simulation time	202835928321 ps
CPU time	1332.86 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 01:16:03 PM PST 23
Peak memory	346936 kb
Host	smart-f8e9bf11-ba21-4d64-ac92-16dc3b909a8d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428115951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.3428115951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.3928457992
Short name	T847
Test name
Test status
Simulation time	24016479433 ps
CPU time	326.31 seconds
Started	Dec 24 12:53:46 PM PST 23
Finished	Dec 24 12:59:17 PM PST 23
Peak memory	244908 kb
Host	smart-7ea0b2fb-5f1f-443f-9c00-166934e022d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928457992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3928457992 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.3368595437
Short name	T276
Test name
Test status
Simulation time	5509594758 ps
CPU time	30.44 seconds
Started	Dec 24 12:53:45 PM PST 23
Finished	Dec 24 12:54:21 PM PST 23
Peak memory	217836 kb
Host	smart-e24bed2d-966f-40a2-837f-63aa33b22314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368595437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3368595437 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.2175322119
Short name	T531
Test name
Test status
Simulation time	1463934016 ps
CPU time	15.34 seconds
Started	Dec 24 12:53:40 PM PST 23
Finished	Dec 24 12:54:02 PM PST 23
Peak memory	222212 kb
Host	smart-2e745818-b2a5-4c94-bbcf-e8bf7cda8b08
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2175322119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2175322119 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.3083496224
Short name	T425
Test name
Test status
Simulation time	260865330 ps
CPU time	4.03 seconds
Started	Dec 24 12:53:41 PM PST 23
Finished	Dec 24 12:53:52 PM PST 23
Peak memory	215668 kb
Host	smart-6786515b-6fa2-4d51-b02b-a952c88b1f5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083496224 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.3083496224 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.4043016408
Short name	T344
Test name
Test status
Simulation time	131600374 ps
CPU time	4.17 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 12:53:54 PM PST 23
Peak memory	208492 kb
Host	smart-2d6655fe-791d-4f25-b67f-8995c0ee76fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043016408 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.4043016408 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.2660496049
Short name	T214
Test name
Test status
Simulation time	104157058637 ps
CPU time	1594.43 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 01:20:25 PM PST 23
Peak memory	390604 kb
Host	smart-07edefd8-8fac-4bdd-8d07-7dc6d03d6567
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2660496049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.2660496049 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.2807512548
Short name	T464
Test name
Test status
Simulation time	18491175984 ps
CPU time	1389.38 seconds
Started	Dec 24 12:53:46 PM PST 23
Finished	Dec 24 01:17:01 PM PST 23
Peak memory	373468 kb
Host	smart-bd270342-8691-44e1-9002-65ce884559d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2807512548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2807512548 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.3980313957
Short name	T579
Test name
Test status
Simulation time	275937333511 ps
CPU time	1398.23 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 01:17:08 PM PST 23
Peak memory	329940 kb
Host	smart-5ed99e2c-1362-47ee-8cf4-6bce33858ca8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3980313957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3980313957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.544781693
Short name	T248
Test name
Test status
Simulation time	83332751580 ps
CPU time	933.92 seconds
Started	Dec 24 12:53:41 PM PST 23
Finished	Dec 24 01:09:22 PM PST 23
Peak memory	293692 kb
Host	smart-b83763dc-8beb-421d-90cb-2803db29f928
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=544781693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.544781693 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.2698175200
Short name	T1065
Test name
Test status
Simulation time	144345895965 ps
CPU time	4012.44 seconds
Started	Dec 24 12:53:48 PM PST 23
Finished	Dec 24 02:00:47 PM PST 23
Peak memory	642924 kb
Host	smart-f58446b1-fd19-402b-a21f-4b665931aea3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2698175200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2698175200 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.1689572
Short name	T1113
Test name
Test status
Simulation time	90143099411 ps
CPU time	3406.46 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 01:50:35 PM PST 23
Peak memory	560952 kb
Host	smart-78ab4e43-130a-43fa-ac88-0d97f54548f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1689572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1689572 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.3625365187
Short name	T51
Test name
Test status
Simulation time	30343026 ps
CPU time	0.79 seconds
Started	Dec 24 12:54:15 PM PST 23
Finished	Dec 24 12:54:20 PM PST 23
Peak memory	205200 kb
Host	smart-dde3a638-4a33-4c86-86ea-a0c636f7f601
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625365187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3625365187 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.1943858942
Short name	T848
Test name
Test status
Simulation time	72769806173 ps
CPU time	329.81 seconds
Started	Dec 24 12:54:17 PM PST 23
Finished	Dec 24 12:59:51 PM PST 23
Peak memory	247476 kb
Host	smart-beab3466-5e76-4b1d-9733-10d7e5455c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943858942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1943858942 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.1601554887
Short name	T544
Test name
Test status
Simulation time	47865260908 ps
CPU time	353.28 seconds
Started	Dec 24 12:54:04 PM PST 23
Finished	Dec 24 01:00:05 PM PST 23
Peak memory	228584 kb
Host	smart-0374ecbf-b94e-4670-b219-621b2eb1063b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601554887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1601554887 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.3722178817
Short name	T109
Test name
Test status
Simulation time	29000674096 ps
CPU time	228.69 seconds
Started	Dec 24 12:54:19 PM PST 23
Finished	Dec 24 12:58:11 PM PST 23
Peak memory	242360 kb
Host	smart-a0c4828a-9347-43bb-b5e3-efcb27e0249c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722178817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3722178817 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.1310731378
Short name	T623
Test name
Test status
Simulation time	12805193049 ps
CPU time	160.26 seconds
Started	Dec 24 12:54:16 PM PST 23
Finished	Dec 24 12:57:00 PM PST 23
Peak memory	248396 kb
Host	smart-56dab0a6-8535-4dd7-8937-3cc49434a55e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310731378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1310731378 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.882860898
Short name	T26
Test name
Test status
Simulation time	1029763328 ps
CPU time	6.45 seconds
Started	Dec 24 12:54:13 PM PST 23
Finished	Dec 24 12:54:25 PM PST 23
Peak memory	207272 kb
Host	smart-cdf4459d-08be-4360-9dba-d1dab4693921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882860898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.882860898 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.2642005241
Short name	T265
Test name
Test status
Simulation time	1378627785 ps
CPU time	7.57 seconds
Started	Dec 24 12:54:04 PM PST 23
Finished	Dec 24 12:54:19 PM PST 23
Peak memory	223828 kb
Host	smart-a61a997a-d5f0-4dff-b727-c8bfbe59edfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642005241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2642005241 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.3516725518
Short name	T1081
Test name
Test status
Simulation time	29348595568 ps
CPU time	854.24 seconds
Started	Dec 24 12:53:42 PM PST 23
Finished	Dec 24 01:08:04 PM PST 23
Peak memory	298212 kb
Host	smart-e7637857-61ba-4547-9706-0e499030764a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516725518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.3516725518 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.1903964182
Short name	T304
Test name
Test status
Simulation time	4145128918 ps
CPU time	288.62 seconds
Started	Dec 24 12:53:43 PM PST 23
Finished	Dec 24 12:58:39 PM PST 23
Peak memory	246896 kb
Host	smart-6c235ff1-7ad0-4907-91f9-ca78f8c6fd92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903964182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1903964182 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.1571901308
Short name	T589
Test name
Test status
Simulation time	1142469748 ps
CPU time	16.64 seconds
Started	Dec 24 12:53:46 PM PST 23
Finished	Dec 24 12:54:07 PM PST 23
Peak memory	219760 kb
Host	smart-e4e92aa6-5d60-4b7a-a679-10968a64c3ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571901308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1571901308 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.1948761192
Short name	T38
Test name
Test status
Simulation time	170344074683 ps
CPU time	976.46 seconds
Started	Dec 24 12:54:27 PM PST 23
Finished	Dec 24 01:10:45 PM PST 23
Peak memory	337832 kb
Host	smart-248f0635-5db8-4b61-905f-8b3e93673f0a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1948761192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1948761192 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_stress_all_with_rand_reset.1451197115
Short name	T228
Test name
Test status
Simulation time	72428124679 ps
CPU time	528.05 seconds
Started	Dec 24 12:54:09 PM PST 23
Finished	Dec 24 01:03:05 PM PST 23
Peak memory	274252 kb
Host	smart-de18ff06-5738-4596-8129-09ad07e81be6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1451197115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.1451197115 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.3261565443
Short name	T913
Test name
Test status
Simulation time	1060863530 ps
CPU time	4.98 seconds
Started	Dec 24 12:54:06 PM PST 23
Finished	Dec 24 12:54:17 PM PST 23
Peak memory	208384 kb
Host	smart-61efe6bb-e58e-4644-859c-3e02672a74c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261565443 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.3261565443 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3580076408
Short name	T259
Test name
Test status
Simulation time	266453312 ps
CPU time	5.18 seconds
Started	Dec 24 12:54:21 PM PST 23
Finished	Dec 24 12:54:28 PM PST 23
Peak memory	215692 kb
Host	smart-fa48122f-2ecb-4374-9974-54efd37408b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580076408 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3580076408 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.1828045980
Short name	T750
Test name
Test status
Simulation time	104180925427 ps
CPU time	1550.62 seconds
Started	Dec 24 12:54:12 PM PST 23
Finished	Dec 24 01:20:09 PM PST 23
Peak memory	390028 kb
Host	smart-68b9bc96-dfd6-47bb-a455-57e7fafcd8ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1828045980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.1828045980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.3097826104
Short name	T979
Test name
Test status
Simulation time	92741369505 ps
CPU time	1858.58 seconds
Started	Dec 24 12:54:12 PM PST 23
Finished	Dec 24 01:25:17 PM PST 23
Peak memory	378740 kb
Host	smart-7b0942c4-f661-43fe-bb49-fd230cf4d31f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3097826104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3097826104 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.3009364846
Short name	T1093
Test name
Test status
Simulation time	124420267794 ps
CPU time	1140.8 seconds
Started	Dec 24 12:54:22 PM PST 23
Finished	Dec 24 01:13:25 PM PST 23
Peak memory	335932 kb
Host	smart-be976308-9c3a-4790-abc0-47d145506c6e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3009364846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3009364846 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.3540189634
Short name	T383
Test name
Test status
Simulation time	126985412830 ps
CPU time	942.47 seconds
Started	Dec 24 12:54:21 PM PST 23
Finished	Dec 24 01:10:06 PM PST 23
Peak memory	296952 kb
Host	smart-6c23f948-508b-4a68-88b0-ac01eb8089ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3540189634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3540189634 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.814390259
Short name	T662
Test name
Test status
Simulation time	713833585147 ps
CPU time	3729.77 seconds
Started	Dec 24 12:54:13 PM PST 23
Finished	Dec 24 01:56:29 PM PST 23
Peak memory	631688 kb
Host	smart-cbcfec22-8d61-4d95-b113-aa3411e7b563
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=814390259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.814390259 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.1505661136
Short name	T1008
Test name
Test status
Simulation time	43927443702 ps
CPU time	3407.75 seconds
Started	Dec 24 12:54:21 PM PST 23
Finished	Dec 24 01:51:12 PM PST 23
Peak memory	565856 kb
Host	smart-5da75cb4-430d-49ad-b803-817f735f8c44
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1505661136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1505661136 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.201333940
Short name	T1128
Test name
Test status
Simulation time	45847173 ps
CPU time	0.77 seconds
Started	Dec 24 12:54:12 PM PST 23
Finished	Dec 24 12:54:19 PM PST 23
Peak memory	205144 kb
Host	smart-516d0225-473d-47ae-93cd-b9d207737dfc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201333940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.201333940 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.556071496
Short name	T253
Test name
Test status
Simulation time	31860479673 ps
CPU time	149.13 seconds
Started	Dec 24 12:54:19 PM PST 23
Finished	Dec 24 12:56:51 PM PST 23
Peak memory	233544 kb
Host	smart-02a2e834-e1d4-4299-b4bf-40e72b9c8f7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556071496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.556071496 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.1311760492
Short name	T71
Test name
Test status
Simulation time	7426952152 ps
CPU time	611.18 seconds
Started	Dec 24 12:54:05 PM PST 23
Finished	Dec 24 01:04:23 PM PST 23
Peak memory	231408 kb
Host	smart-6ba32100-70f5-45b3-9e41-683b3636a0f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311760492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1311760492 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.1871293575
Short name	T1109
Test name
Test status
Simulation time	13913848421 ps
CPU time	104.78 seconds
Started	Dec 24 12:54:14 PM PST 23
Finished	Dec 24 12:56:04 PM PST 23
Peak memory	230160 kb
Host	smart-9f101118-733d-4a8e-978a-e4011b917ff8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871293575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1871293575 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.2747101724
Short name	T831
Test name
Test status
Simulation time	3337222661 ps
CPU time	261.93 seconds
Started	Dec 24 12:54:23 PM PST 23
Finished	Dec 24 12:58:46 PM PST 23
Peak memory	256904 kb
Host	smart-13ad4a67-881f-4c0c-9255-a757a52f9be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747101724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2747101724 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.1245437459
Short name	T1092
Test name
Test status
Simulation time	2371503482 ps
CPU time	3.9 seconds
Started	Dec 24 12:54:13 PM PST 23
Finished	Dec 24 12:54:23 PM PST 23
Peak memory	207344 kb
Host	smart-9525c402-cf0e-414d-9835-a934c620543a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245437459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1245437459 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.2874940256
Short name	T396
Test name
Test status
Simulation time	359269614 ps
CPU time	6.41 seconds
Started	Dec 24 12:54:06 PM PST 23
Finished	Dec 24 12:54:18 PM PST 23
Peak memory	221432 kb
Host	smart-16b52355-5303-4883-96c8-c4a4cbe374c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874940256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2874940256 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.2409830447
Short name	T329
Test name
Test status
Simulation time	40115905472 ps
CPU time	1126.89 seconds
Started	Dec 24 12:54:21 PM PST 23
Finished	Dec 24 01:13:10 PM PST 23
Peak memory	325332 kb
Host	smart-7b7ff959-92ec-43fc-ba3c-3a9411077e9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409830447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.2409830447 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.4292463379
Short name	T983
Test name
Test status
Simulation time	8017758159 ps
CPU time	154.5 seconds
Started	Dec 24 12:54:20 PM PST 23
Finished	Dec 24 12:56:57 PM PST 23
Peak memory	235244 kb
Host	smart-9c943fe9-ae7a-4f21-9f5a-69ec97b903d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292463379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.4292463379 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.1486754215
Short name	T1142
Test name
Test status
Simulation time	7731786073 ps
CPU time	64.8 seconds
Started	Dec 24 12:54:16 PM PST 23
Finished	Dec 24 12:55:25 PM PST 23
Peak memory	218808 kb
Host	smart-8e8cf53f-6e85-485f-8604-3bd2c99fe0d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486754215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1486754215 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.3441912520
Short name	T918
Test name
Test status
Simulation time	4524766446 ps
CPU time	75.36 seconds
Started	Dec 24 12:54:21 PM PST 23
Finished	Dec 24 12:55:38 PM PST 23
Peak memory	241208 kb
Host	smart-49be58a7-512c-4971-ad75-c5af3edd283c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3441912520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3441912520 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_stress_all_with_rand_reset.1978618164
Short name	T567
Test name
Test status
Simulation time	98868713444 ps
CPU time	2667.8 seconds
Started	Dec 24 12:54:06 PM PST 23
Finished	Dec 24 01:38:40 PM PST 23
Peak memory	414128 kb
Host	smart-6f8b5e67-9f15-4ad5-af49-c8bce5c77c29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1978618164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.1978618164 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.2619485400
Short name	T235
Test name
Test status
Simulation time	60070414 ps
CPU time	3.81 seconds
Started	Dec 24 12:54:04 PM PST 23
Finished	Dec 24 12:54:15 PM PST 23
Peak memory	215684 kb
Host	smart-8e951cb7-c635-4119-81ff-ea31c30e2d6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619485400 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.2619485400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.1944104167
Short name	T498
Test name
Test status
Simulation time	167736958 ps
CPU time	4 seconds
Started	Dec 24 12:54:11 PM PST 23
Finished	Dec 24 12:54:22 PM PST 23
Peak memory	215612 kb
Host	smart-bc21cafd-f05d-4e06-a304-9b9d307cfc2b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944104167 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.1944104167 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.515242498
Short name	T232
Test name
Test status
Simulation time	978082178206 ps
CPU time	2067.3 seconds
Started	Dec 24 12:54:20 PM PST 23
Finished	Dec 24 01:28:50 PM PST 23
Peak memory	393832 kb
Host	smart-01ebd9f4-d7d9-4cbf-94dd-29d477241b81
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=515242498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.515242498 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.2676104303
Short name	T79
Test name
Test status
Simulation time	387634050018 ps
CPU time	1849.91 seconds
Started	Dec 24 12:54:13 PM PST 23
Finished	Dec 24 01:25:09 PM PST 23
Peak memory	387048 kb
Host	smart-19d6a7dd-1c3d-4e91-a65b-607fd47f60f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2676104303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2676104303 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.2749035693
Short name	T856
Test name
Test status
Simulation time	15726739759 ps
CPU time	1138.13 seconds
Started	Dec 24 12:54:06 PM PST 23
Finished	Dec 24 01:13:10 PM PST 23
Peak memory	335500 kb
Host	smart-cbf1eabf-a40e-4f29-bfa2-59ee15963361
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2749035693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2749035693 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.2940473657
Short name	T516
Test name
Test status
Simulation time	155755406767 ps
CPU time	893.85 seconds
Started	Dec 24 12:54:04 PM PST 23
Finished	Dec 24 01:09:06 PM PST 23
Peak memory	286404 kb
Host	smart-81fa0b2f-a7b8-4b71-8054-e8faf9bc0f38
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2940473657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2940473657 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.3537746513
Short name	T338
Test name
Test status
Simulation time	54321214646 ps
CPU time	4243.1 seconds
Started	Dec 24 12:54:24 PM PST 23
Finished	Dec 24 02:05:09 PM PST 23
Peak memory	655012 kb
Host	smart-fea2315c-5979-4cb6-b286-800a37fc5cfb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3537746513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.3537746513 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.1069687014
Short name	T1047
Test name
Test status
Simulation time	433653839865 ps
CPU time	3663.69 seconds
Started	Dec 24 12:54:15 PM PST 23
Finished	Dec 24 01:55:24 PM PST 23
Peak memory	564224 kb
Host	smart-95bbf507-aba1-4dca-9a09-767761a057f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1069687014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1069687014 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.789161386
Short name	T480
Test name
Test status
Simulation time	26993138 ps
CPU time	0.77 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 12:48:41 PM PST 23
Peak memory	205204 kb
Host	smart-f3639fee-2ce1-4c8a-b99c-e4bebbe33559
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789161386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.789161386 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.2963696324
Short name	T886
Test name
Test status
Simulation time	34046169873 ps
CPU time	170 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:51:46 PM PST 23
Peak memory	235216 kb
Host	smart-c2dfc9a4-224f-4b51-80b1-6db4b31223a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963696324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2963696324 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.180961008
Short name	T317
Test name
Test status
Simulation time	23302867673 ps
CPU time	206.05 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:52:24 PM PST 23
Peak memory	241872 kb
Host	smart-9ab8c4b6-e885-46fb-b3d3-497b83db2203
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180961008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.180961008 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.2060642425
Short name	T945
Test name
Test status
Simulation time	5078824006 ps
CPU time	112.62 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 12:50:57 PM PST 23
Peak memory	223784 kb
Host	smart-bfedc53f-5a98-4497-94c1-deed808ed31c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060642425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2060642425 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.1623888335
Short name	T845
Test name
Test status
Simulation time	841841494 ps
CPU time	20.82 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:31 PM PST 23
Peak memory	223764 kb
Host	smart-1ee874e2-7522-42ba-9ec7-6baa088e5333
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1623888335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1623888335 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.72623313
Short name	T1004
Test name
Test status
Simulation time	3794805056 ps
CPU time	26.16 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 12:49:31 PM PST 23
Peak memory	219548 kb
Host	smart-f21c3907-2822-4fd9-a750-22400a53272d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=72623313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.72623313 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.2736347612
Short name	T211
Test name
Test status
Simulation time	13985093195 ps
CPU time	13.48 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:49:12 PM PST 23
Peak memory	215568 kb
Host	smart-99009819-c9a6-47d2-90d5-f2b7162bb5bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736347612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2736347612 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.2179316827
Short name	T633
Test name
Test status
Simulation time	14534124632 ps
CPU time	196.47 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:52:27 PM PST 23
Peak memory	241776 kb
Host	smart-b4dcdce8-a9bb-4645-b916-f1a582f729f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179316827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2179316827 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.3150209472
Short name	T808
Test name
Test status
Simulation time	28127434581 ps
CPU time	192.05 seconds
Started	Dec 24 12:48:55 PM PST 23
Finished	Dec 24 12:52:09 PM PST 23
Peak memory	248640 kb
Host	smart-f4e4fde3-fe05-48e0-b3a4-e7090179bb6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150209472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3150209472 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.3829998983
Short name	T728
Test name
Test status
Simulation time	856717860 ps
CPU time	2.53 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:48:39 PM PST 23
Peak memory	207112 kb
Host	smart-2402af25-cb8e-4213-ad99-3a9e40515357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829998983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3829998983 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.3777731651
Short name	T959
Test name
Test status
Simulation time	45836788 ps
CPU time	1.38 seconds
Started	Dec 24 12:49:04 PM PST 23
Finished	Dec 24 12:49:08 PM PST 23
Peak memory	215616 kb
Host	smart-b5acd74f-847b-45b3-8ae5-8d84deaca5c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777731651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3777731651 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.2548779346
Short name	T1143
Test name
Test status
Simulation time	64031710539 ps
CPU time	1703.59 seconds
Started	Dec 24 12:48:38 PM PST 23
Finished	Dec 24 01:17:03 PM PST 23
Peak memory	398716 kb
Host	smart-11cd80c6-8577-49af-908e-a61462c97134
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548779346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an d_output.2548779346 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_sideload.963641617
Short name	T405
Test name
Test status
Simulation time	20225549015 ps
CPU time	140.95 seconds
Started	Dec 24 12:49:06 PM PST 23
Finished	Dec 24 12:51:29 PM PST 23
Peak memory	230344 kb
Host	smart-368f6818-d1df-4025-8b9d-2d89a1f4a573
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963641617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.963641617 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.1899126370
Short name	T1056
Test name
Test status
Simulation time	427935746 ps
CPU time	9.13 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 12:49:10 PM PST 23
Peak memory	218708 kb
Host	smart-5a9de6f5-0e13-4873-9233-2f2b12103e2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899126370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1899126370 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.2617846320
Short name	T819
Test name
Test status
Simulation time	70618346024 ps
CPU time	1379.84 seconds
Started	Dec 24 12:48:46 PM PST 23
Finished	Dec 24 01:11:47 PM PST 23
Peak memory	372600 kb
Host	smart-791c58e0-f9dc-4669-bcba-e653981c1a5b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2617846320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2617846320 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.2077418121
Short name	T732
Test name
Test status
Simulation time	25839997931 ps
CPU time	667.9 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 01:00:09 PM PST 23
Peak memory	298048 kb
Host	smart-c534ce7e-2235-4016-a9a6-0f9cab453ded
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2077418121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.2077418121 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.513163872
Short name	T953
Test name
Test status
Simulation time	504478966 ps
CPU time	3.8 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 12:49:18 PM PST 23
Peak memory	215704 kb
Host	smart-8f384aae-14bf-4e19-af28-ab917de9142d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513163872 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.kmac_test_vectors_kmac.513163872 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3434161667
Short name	T924
Test name
Test status
Simulation time	253439899 ps
CPU time	4.58 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:49:01 PM PST 23
Peak memory	215732 kb
Host	smart-818fc1b3-ad7d-4f68-8210-0c8eedfe71f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434161667 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3434161667 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.315300142
Short name	T428
Test name
Test status
Simulation time	93480011704 ps
CPU time	1679.34 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 01:16:58 PM PST 23
Peak memory	376496 kb
Host	smart-ab568aa1-5228-47ae-bb1a-9201d08e5a2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=315300142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.315300142 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.3506643762
Short name	T677
Test name
Test status
Simulation time	33595897435 ps
CPU time	1389.59 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 01:12:10 PM PST 23
Peak memory	374688 kb
Host	smart-653bb3c7-94b0-4007-a3b3-0272a4a3c1e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3506643762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3506643762 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.2348214553
Short name	T966
Test name
Test status
Simulation time	48231671934 ps
CPU time	1269.53 seconds
Started	Dec 24 12:49:03 PM PST 23
Finished	Dec 24 01:10:15 PM PST 23
Peak memory	331192 kb
Host	smart-b8049ad1-70be-4e29-919d-c5b15693cd51
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2348214553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2348214553 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2875604065
Short name	T16
Test name
Test status
Simulation time	119952947590 ps
CPU time	851.47 seconds
Started	Dec 24 12:49:06 PM PST 23
Finished	Dec 24 01:03:19 PM PST 23
Peak memory	296360 kb
Host	smart-ea171055-e7e2-40e5-8447-4d665bd4727c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2875604065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2875604065 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.3122345636
Short name	T898
Test name
Test status
Simulation time	67377100452 ps
CPU time	4147.7 seconds
Started	Dec 24 12:49:03 PM PST 23
Finished	Dec 24 01:58:13 PM PST 23
Peak memory	659156 kb
Host	smart-ab6c648f-8244-4d0b-a82b-b523b988f5cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3122345636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3122345636 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.3264427668
Short name	T801
Test name
Test status
Simulation time	20196439 ps
CPU time	0.79 seconds
Started	Dec 24 12:48:30 PM PST 23
Finished	Dec 24 12:48:32 PM PST 23
Peak memory	205204 kb
Host	smart-b96a6e82-7d73-4c21-97c6-bbde3c653849
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264427668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3264427668 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.4142424944
Short name	T543
Test name
Test status
Simulation time	12751845837 ps
CPU time	301.83 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 12:53:35 PM PST 23
Peak memory	246872 kb
Host	smart-dff27c8f-9794-40a4-aaa9-8ab15c853ee4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142424944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4142424944 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.1524286538
Short name	T372
Test name
Test status
Simulation time	71613909767 ps
CPU time	193.98 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 12:51:57 PM PST 23
Peak memory	236304 kb
Host	smart-ea67a963-d14b-4f07-a0f0-a9aa00bc220a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524286538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1524286538 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.4175576873
Short name	T321
Test name
Test status
Simulation time	46707627894 ps
CPU time	539.67 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:57:58 PM PST 23
Peak memory	230480 kb
Host	smart-111813de-bfcf-4bf4-ac2e-af37302964a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175576873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.4175576873 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.1389190790
Short name	T824
Test name
Test status
Simulation time	591938670 ps
CPU time	21.35 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 12:48:57 PM PST 23
Peak memory	223688 kb
Host	smart-0ab91ee1-cbf4-4f44-bf08-6bdb49130715
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1389190790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1389190790 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.4168570176
Short name	T1123
Test name
Test status
Simulation time	1735651860 ps
CPU time	22.68 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:48:57 PM PST 23
Peak memory	219948 kb
Host	smart-02f2c783-8d02-4e72-8ca5-1c4a311a7c83
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4168570176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.4168570176 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.2722232233
Short name	T1086
Test name
Test status
Simulation time	4953222698 ps
CPU time	11.64 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:48:46 PM PST 23
Peak memory	216256 kb
Host	smart-7cd3dd6c-5d67-4398-ab16-fae434699576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722232233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2722232233 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.804563707
Short name	T402
Test name
Test status
Simulation time	29009374351 ps
CPU time	276.28 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:53:11 PM PST 23
Peak memory	244164 kb
Host	smart-e0e9e4f3-274e-4d59-8823-25c2b8e1b880
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804563707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.804563707 +enable_masking=0 +sw_ key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.2439090825
Short name	T699
Test name
Test status
Simulation time	3770359550 ps
CPU time	266.01 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:53:26 PM PST 23
Peak memory	252008 kb
Host	smart-9307a042-b227-45ea-bb9e-4536e8be6996
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439090825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2439090825 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.4135891520
Short name	T719
Test name
Test status
Simulation time	3587002351 ps
CPU time	4.08 seconds
Started	Dec 24 12:48:39 PM PST 23
Finished	Dec 24 12:48:45 PM PST 23
Peak memory	207328 kb
Host	smart-9822c8b9-4885-4b31-ba95-66a752a5110e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135891520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4135891520 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.2737473462
Short name	T467
Test name
Test status
Simulation time	45606766 ps
CPU time	1.31 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 12:48:44 PM PST 23
Peak memory	215452 kb
Host	smart-98eb26ca-9268-45d1-9443-c85f2b5c51f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737473462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2737473462 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.683669050
Short name	T564
Test name
Test status
Simulation time	11765743405 ps
CPU time	323.06 seconds
Started	Dec 24 12:48:37 PM PST 23
Finished	Dec 24 12:54:02 PM PST 23
Peak memory	248872 kb
Host	smart-7e862780-6262-4660-a8d0-c41c68514fc4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683669050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and _output.683669050 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.2793543481
Short name	T367
Test name
Test status
Simulation time	15170528376 ps
CPU time	167.77 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:51:25 PM PST 23
Peak memory	236752 kb
Host	smart-7d30e556-4667-4216-b3bd-a987932bae5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793543481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2793543481 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.2456918810
Short name	T47
Test name
Test status
Simulation time	53139597107 ps
CPU time	408.2 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 12:55:45 PM PST 23
Peak memory	248604 kb
Host	smart-66b329a5-72f2-45a7-8ac4-5f1294ced4c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456918810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2456918810 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.326233140
Short name	T299
Test name
Test status
Simulation time	379616130 ps
CPU time	19.74 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:49:19 PM PST 23
Peak memory	216900 kb
Host	smart-7cf3a9b0-abac-4df6-a0cd-fef419b90c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326233140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.326233140 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.3253418446
Short name	T270
Test name
Test status
Simulation time	101050873467 ps
CPU time	2277 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 01:26:53 PM PST 23
Peak memory	458836 kb
Host	smart-b966a82d-b242-4e53-a911-323b3b53f313
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3253418446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3253418446 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.3486369779
Short name	T874
Test name
Test status
Simulation time	256819988 ps
CPU time	3.97 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 12:48:37 PM PST 23
Peak memory	208904 kb
Host	smart-0bde7412-6b42-44d0-b17c-315861a36d73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486369779 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.3486369779 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.586699980
Short name	T1052
Test name
Test status
Simulation time	858627852 ps
CPU time	4.62 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 12:48:37 PM PST 23
Peak memory	215728 kb
Host	smart-887ee135-8a61-4a74-bcff-f3e8337de134
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586699980 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.kmac_test_vectors_kmac_xof.586699980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.1085052400
Short name	T347
Test name
Test status
Simulation time	531324139503 ps
CPU time	1721.83 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 01:17:17 PM PST 23
Peak memory	378220 kb
Host	smart-401873c1-2f5b-488d-b19a-ef56bcd1be2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1085052400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.1085052400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.1218645269
Short name	T714
Test name
Test status
Simulation time	36123745610 ps
CPU time	1418.85 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 01:12:24 PM PST 23
Peak memory	373400 kb
Host	smart-5a049dc3-22c8-4095-943d-c4b7a827537b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1218645269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.1218645269 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.3126459250
Short name	T225
Test name
Test status
Simulation time	47025149041 ps
CPU time	1206.74 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 01:08:43 PM PST 23
Peak memory	335408 kb
Host	smart-f90cb7d1-ccbf-425c-b261-71b932d45bd8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3126459250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3126459250 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.1985435604
Short name	T649
Test name
Test status
Simulation time	41186137953 ps
CPU time	788.69 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 01:01:43 PM PST 23
Peak memory	294608 kb
Host	smart-964563f2-8324-4291-aa7d-dc14492886a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1985435604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1985435604 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.102213100
Short name	T1074
Test name
Test status
Simulation time	210025563012 ps
CPU time	3720.1 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 01:50:44 PM PST 23
Peak memory	640572 kb
Host	smart-5322f6a3-e2a0-4b7a-a428-a6de33d0d37f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=102213100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.102213100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.3775020664
Short name	T246
Test name
Test status
Simulation time	887412403818 ps
CPU time	4515.3 seconds
Started	Dec 24 12:48:51 PM PST 23
Finished	Dec 24 02:04:08 PM PST 23
Peak memory	548372 kb
Host	smart-a7860566-cafc-459f-9902-2c072e5652c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3775020664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3775020664 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.222774817
Short name	T497
Test name
Test status
Simulation time	13591276 ps
CPU time	0.75 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 12:48:44 PM PST 23
Peak memory	205220 kb
Host	smart-8e6ca624-551b-4e90-86a8-627c3cffd19d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222774817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.222774817 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.3378830388
Short name	T1049
Test name
Test status
Simulation time	6980640989 ps
CPU time	156.66 seconds
Started	Dec 24 12:48:46 PM PST 23
Finished	Dec 24 12:51:24 PM PST 23
Peak memory	235068 kb
Host	smart-61b955f1-bb3c-46ff-8317-6b357a38ef1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378830388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3378830388 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.3867962651
Short name	T542
Test name
Test status
Simulation time	8304243097 ps
CPU time	156.52 seconds
Started	Dec 24 12:48:37 PM PST 23
Finished	Dec 24 12:51:15 PM PST 23
Peak memory	233644 kb
Host	smart-a1f7d1cd-474c-49ca-ac2a-d4393e2e30b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867962651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3867962651 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.103883378
Short name	T539
Test name
Test status
Simulation time	108000775862 ps
CPU time	761.56 seconds
Started	Dec 24 12:48:32 PM PST 23
Finished	Dec 24 01:01:15 PM PST 23
Peak memory	231752 kb
Host	smart-98a02d9c-4b80-4dd2-8f04-81500e8e8114
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103883378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.103883378 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.1430342692
Short name	T742
Test name
Test status
Simulation time	2310292950 ps
CPU time	45.45 seconds
Started	Dec 24 12:48:33 PM PST 23
Finished	Dec 24 12:49:20 PM PST 23
Peak memory	223856 kb
Host	smart-667fff07-2455-4f39-a3a1-1e8cd8d3fb63
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1430342692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1430342692 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.751138068
Short name	T296
Test name
Test status
Simulation time	537296831 ps
CPU time	9.75 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:19 PM PST 23
Peak memory	218680 kb
Host	smart-0fce403d-fc17-4dea-a4fd-3fb4a6daaaf5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=751138068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.751138068 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.169741222
Short name	T146
Test name
Test status
Simulation time	11144645178 ps
CPU time	46.1 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:49:22 PM PST 23
Peak memory	215712 kb
Host	smart-904fd522-9b5f-4d89-9af9-a76141a6322f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169741222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.169741222 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.4136843208
Short name	T1060
Test name
Test status
Simulation time	95997466510 ps
CPU time	185.6 seconds
Started	Dec 24 12:48:35 PM PST 23
Finished	Dec 24 12:51:44 PM PST 23
Peak memory	238800 kb
Host	smart-ae89671d-34fb-4f77-a6f5-882463092dae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136843208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.4136843208 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.3962069953
Short name	T96
Test name
Test status
Simulation time	31139167053 ps
CPU time	219.8 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:52:51 PM PST 23
Peak memory	256632 kb
Host	smart-70a8508e-85ef-4cd2-baa4-0879af6abf01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962069953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3962069953 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.2380405031
Short name	T1100
Test name
Test status
Simulation time	1659366238 ps
CPU time	4.93 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 12:49:06 PM PST 23
Peak memory	207248 kb
Host	smart-1b47758f-7746-44f6-83ef-a68e8b6d1fba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380405031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2380405031 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.1867505378
Short name	T1028
Test name
Test status
Simulation time	51400285 ps
CPU time	1.01 seconds
Started	Dec 24 12:48:52 PM PST 23
Finished	Dec 24 12:48:55 PM PST 23
Peak memory	215624 kb
Host	smart-b98eab07-dc74-47b0-a007-0d6d39bd37c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867505378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1867505378 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.1793049100
Short name	T556
Test name
Test status
Simulation time	20001157025 ps
CPU time	455.32 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 12:56:11 PM PST 23
Peak memory	264876 kb
Host	smart-23b8ea23-48bd-4313-a6f9-459459671ec8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793049100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.1793049100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.4280339399
Short name	T973
Test name
Test status
Simulation time	2624800472 ps
CPU time	51.05 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:50:02 PM PST 23
Peak memory	224384 kb
Host	smart-835b65ad-aa85-4b1a-b541-ab18de3b3bb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280339399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.4280339399 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.1350103208
Short name	T794
Test name
Test status
Simulation time	7572675630 ps
CPU time	55.66 seconds
Started	Dec 24 12:48:36 PM PST 23
Finished	Dec 24 12:49:33 PM PST 23
Peak memory	223808 kb
Host	smart-4ddcf4bf-ceaf-437a-a9cc-71f37b4f403b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350103208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1350103208 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.3681404005
Short name	T897
Test name
Test status
Simulation time	5735366803 ps
CPU time	37.25 seconds
Started	Dec 24 12:48:34 PM PST 23
Finished	Dec 24 12:49:13 PM PST 23
Peak memory	217056 kb
Host	smart-d068aa53-94b3-44ad-8d99-66b2c8ea5a47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681404005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3681404005 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.2279842560
Short name	T587
Test name
Test status
Simulation time	188059004438 ps
CPU time	981.78 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 01:05:18 PM PST 23
Peak memory	309880 kb
Host	smart-f99573f9-69f9-45af-ae20-2e6178c62443
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2279842560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2279842560 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_stress_all_with_rand_reset.2123080839
Short name	T390
Test name
Test status
Simulation time	223047708097 ps
CPU time	922.56 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 01:04:27 PM PST 23
Peak memory	267988 kb
Host	smart-2015fee6-cdd0-4552-9cf8-1665c86c7646
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2123080839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.2123080839 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.3407569554
Short name	T481
Test name
Test status
Simulation time	681372945 ps
CPU time	4.53 seconds
Started	Dec 24 12:48:36 PM PST 23
Finished	Dec 24 12:48:43 PM PST 23
Peak memory	215648 kb
Host	smart-45a845ad-3dd4-4fd9-a4c1-a7d741075282
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407569554 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.3407569554 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.862481150
Short name	T602
Test name
Test status
Simulation time	164572838 ps
CPU time	4.4 seconds
Started	Dec 24 12:48:51 PM PST 23
Finished	Dec 24 12:48:56 PM PST 23
Peak memory	215656 kb
Host	smart-0fa3ed0c-56a7-4b86-aa55-b94e13348a3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862481150 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.kmac_test_vectors_kmac_xof.862481150 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.2155301992
Short name	T261
Test name
Test status
Simulation time	66788031366 ps
CPU time	1757.3 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 01:18:02 PM PST 23
Peak memory	387232 kb
Host	smart-90043914-3d59-4fb5-8a29-f34befc151e5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2155301992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2155301992 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.3926097774
Short name	T475
Test name
Test status
Simulation time	74462722734 ps
CPU time	1430.71 seconds
Started	Dec 24 12:48:42 PM PST 23
Finished	Dec 24 01:12:34 PM PST 23
Peak memory	377024 kb
Host	smart-25d5a133-3a92-47c0-b124-13ca719174e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3926097774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3926097774 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.2885236243
Short name	T569
Test name
Test status
Simulation time	192957900311 ps
CPU time	1367.98 seconds
Started	Dec 24 12:48:38 PM PST 23
Finished	Dec 24 01:11:27 PM PST 23
Peak memory	330912 kb
Host	smart-61560db1-2e8b-42e8-9da0-889a1e431178
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2885236243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2885236243 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.1574255152
Short name	T440
Test name
Test status
Simulation time	295542818941 ps
CPU time	936.87 seconds
Started	Dec 24 12:48:52 PM PST 23
Finished	Dec 24 01:04:30 PM PST 23
Peak memory	294356 kb
Host	smart-c8e16a10-a78f-41c4-be94-9f3aff93b516
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1574255152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1574255152 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.3330492289
Short name	T650
Test name
Test status
Simulation time	2838947961251 ps
CPU time	5949.79 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 02:27:43 PM PST 23
Peak memory	645248 kb
Host	smart-b75e0e6b-1639-4e68-9493-20da45b48279
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3330492289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3330492289 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.3780025795
Short name	T657
Test name
Test status
Simulation time	43519007623 ps
CPU time	3302.47 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 01:43:45 PM PST 23
Peak memory	566068 kb
Host	smart-39f1b64d-0e92-4d89-898e-b7df8f81e0c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3780025795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3780025795 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.402923757
Short name	T1067
Test name
Test status
Simulation time	49688146 ps
CPU time	0.78 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:49:12 PM PST 23
Peak memory	205100 kb
Host	smart-b14eb959-ae5e-4c34-b8dd-365992354c6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402923757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.402923757 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.2960316018
Short name	T760
Test name
Test status
Simulation time	16624546845 ps
CPU time	300.1 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:53:58 PM PST 23
Peak memory	243872 kb
Host	smart-7c8d0757-badb-4559-b9ba-ed6995af08d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960316018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2960316018 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.4090857330
Short name	T445
Test name
Test status
Simulation time	16224105139 ps
CPU time	276.22 seconds
Started	Dec 24 12:48:55 PM PST 23
Finished	Dec 24 12:53:33 PM PST 23
Peak memory	242864 kb
Host	smart-6574c4b1-db1c-43c0-96ee-0aa92852a029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090857330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4090857330 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.1557006976
Short name	T229
Test name
Test status
Simulation time	20024043654 ps
CPU time	480.04 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 12:57:01 PM PST 23
Peak memory	236760 kb
Host	smart-31e4f667-3f81-4056-a2d3-0240bb08fac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557006976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1557006976 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.1474568246
Short name	T909
Test name
Test status
Simulation time	1351745559 ps
CPU time	9.83 seconds
Started	Dec 24 12:48:58 PM PST 23
Finished	Dec 24 12:49:10 PM PST 23
Peak memory	222996 kb
Host	smart-f51416df-b311-429e-b518-82cf0e3a7e22
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1474568246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1474568246 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.653967984
Short name	T456
Test name
Test status
Simulation time	1519310370 ps
CPU time	20.68 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:30 PM PST 23
Peak memory	217208 kb
Host	smart-8f7bdc41-dc6c-48ea-9516-fc431a7b3652
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=653967984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.653967984 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.1684787856
Short name	T992
Test name
Test status
Simulation time	1610842553 ps
CPU time	10.68 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:49:22 PM PST 23
Peak memory	223728 kb
Host	smart-29140160-6fc0-4920-a065-4c0aa7810cdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684787856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1684787856 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.3044792303
Short name	T673
Test name
Test status
Simulation time	25782858176 ps
CPU time	350.59 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:54:49 PM PST 23
Peak memory	248132 kb
Host	smart-90270f59-237d-4598-96ff-79a57fb0db4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044792303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3044792303 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_error.1088639292
Short name	T314
Test name
Test status
Simulation time	1985911522 ps
CPU time	39.12 seconds
Started	Dec 24 12:48:45 PM PST 23
Finished	Dec 24 12:49:26 PM PST 23
Peak memory	231964 kb
Host	smart-ea01d1db-db75-4ab8-a1c6-8021c0c68bcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088639292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1088639292 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.2453496166
Short name	T833
Test name
Test status
Simulation time	106424200 ps
CPU time	1.24 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:49:04 PM PST 23
Peak memory	206356 kb
Host	smart-7dd2c33c-be3b-44ac-baf3-f70c9c7435c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453496166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2453496166 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.815460258
Short name	T389
Test name
Test status
Simulation time	166954844 ps
CPU time	1.22 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:49:00 PM PST 23
Peak memory	215828 kb
Host	smart-ab562a15-9fbc-4b1b-b2ca-cf3f8865e1e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815460258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.815460258 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.2031558836
Short name	T865
Test name
Test status
Simulation time	82312672318 ps
CPU time	1113.54 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 01:07:17 PM PST 23
Peak memory	329536 kb
Host	smart-70eb3b50-2c67-4ac1-b9ae-d0ff13f1a6be
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031558836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.2031558836 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.3870588442
Short name	T638
Test name
Test status
Simulation time	38841007283 ps
CPU time	274.5 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:53:38 PM PST 23
Peak memory	242408 kb
Host	smart-7e509b0f-f781-4c1a-9620-1065b14603a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3870588442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3870588442 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.4056978235
Short name	T747
Test name
Test status
Simulation time	29082184835 ps
CPU time	281.37 seconds
Started	Dec 24 12:48:31 PM PST 23
Finished	Dec 24 12:53:14 PM PST 23
Peak memory	240448 kb
Host	smart-27ca8d59-5d95-4937-895d-7ee88d888ec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056978235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.4056978235 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.445180664
Short name	T685
Test name
Test status
Simulation time	3106845178 ps
CPU time	38.4 seconds
Started	Dec 24 12:48:46 PM PST 23
Finished	Dec 24 12:49:26 PM PST 23
Peak memory	219304 kb
Host	smart-72d65bd1-ac0a-4dc0-878c-ffd106849401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445180664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.445180664 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.1080366400
Short name	T1124
Test name
Test status
Simulation time	15236784319 ps
CPU time	1100.14 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 01:07:25 PM PST 23
Peak memory	361100 kb
Host	smart-7d9cc651-6971-45a2-b1f0-a6fe32c14073
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1080366400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1080366400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.1498763129
Short name	T78
Test name
Test status
Simulation time	976984091 ps
CPU time	4.7 seconds
Started	Dec 24 12:48:52 PM PST 23
Finished	Dec 24 12:48:59 PM PST 23
Peak memory	215716 kb
Host	smart-2a4b2bbd-cf3e-4919-a0c9-b1a328f24df5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498763129 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.1498763129 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1801180895
Short name	T221
Test name
Test status
Simulation time	231657775 ps
CPU time	4.19 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	215596 kb
Host	smart-f75ab4f8-10a2-40eb-973d-87dcde1ceeea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801180895 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1801180895 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.1117305637
Short name	T1032
Test name
Test status
Simulation time	382813362124 ps
CPU time	2004.52 seconds
Started	Dec 24 12:48:41 PM PST 23
Finished	Dec 24 01:22:08 PM PST 23
Peak memory	378916 kb
Host	smart-00468adc-e9b2-491a-be51-ed5d6891501b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1117305637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1117305637 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.1244544288
Short name	T888
Test name
Test status
Simulation time	241896598633 ps
CPU time	1648.11 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 01:16:27 PM PST 23
Peak memory	370164 kb
Host	smart-4de82538-e12c-4d4e-93de-2f4e97f73936
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1244544288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.1244544288 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.2270490203
Short name	T931
Test name
Test status
Simulation time	95409966642 ps
CPU time	1356.92 seconds
Started	Dec 24 12:48:59 PM PST 23
Finished	Dec 24 01:11:38 PM PST 23
Peak memory	339388 kb
Host	smart-96d73e97-64d8-4d04-b557-cb251b30a997
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2270490203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2270490203 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.3139307793
Short name	T374
Test name
Test status
Simulation time	33432696709 ps
CPU time	979.46 seconds
Started	Dec 24 12:48:32 PM PST 23
Finished	Dec 24 01:04:53 PM PST 23
Peak memory	297084 kb
Host	smart-8689ae50-b3da-4286-80d8-f81223749a08
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3139307793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3139307793 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.4113270065
Short name	T954
Test name
Test status
Simulation time	210837636691 ps
CPU time	4041.35 seconds
Started	Dec 24 12:48:54 PM PST 23
Finished	Dec 24 01:56:18 PM PST 23
Peak memory	644908 kb
Host	smart-ee5b0163-b201-4d96-b7b0-10ad7f82dfae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4113270065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.4113270065 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.2095700169
Short name	T44
Test name
Test status
Simulation time	241239316431 ps
CPU time	3308.4 seconds
Started	Dec 24 12:48:50 PM PST 23
Finished	Dec 24 01:44:00 PM PST 23
Peak memory	564416 kb
Host	smart-298af938-30fe-48dc-909d-9bfc647d9ecd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2095700169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.2095700169 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.4027613942
Short name	T538
Test name
Test status
Simulation time	32371182 ps
CPU time	0.85 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 12:49:15 PM PST 23
Peak memory	205084 kb
Host	smart-8f906a9c-e5d6-40ca-b8a1-fc291e4b8cd4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027613942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4027613942 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.3247302854
Short name	T619
Test name
Test status
Simulation time	835105808 ps
CPU time	18.75 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:49:22 PM PST 23
Peak memory	223776 kb
Host	smart-87c13176-b4ba-486b-a842-e0bd28d4298c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247302854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3247302854 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.3416741033
Short name	T871
Test name
Test status
Simulation time	6103481227 ps
CPU time	120.62 seconds
Started	Dec 24 12:49:10 PM PST 23
Finished	Dec 24 12:51:13 PM PST 23
Peak memory	230404 kb
Host	smart-eaef83ec-e1c6-4505-93f9-df81a500f273
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416741033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3416741033 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.3831394813
Short name	T353
Test name
Test status
Simulation time	3541084142 ps
CPU time	271.78 seconds
Started	Dec 24 12:48:55 PM PST 23
Finished	Dec 24 12:53:29 PM PST 23
Peak memory	227008 kb
Host	smart-dd282888-1724-4540-8699-cf9a2112bc2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831394813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3831394813 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.1290406477
Short name	T462
Test name
Test status
Simulation time	475752170 ps
CPU time	8.67 seconds
Started	Dec 24 12:49:10 PM PST 23
Finished	Dec 24 12:49:21 PM PST 23
Peak memory	215512 kb
Host	smart-da17653b-80f1-4236-ab09-a08c03559542
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1290406477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1290406477 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.44424918
Short name	T236
Test name
Test status
Simulation time	460766437 ps
CPU time	27.94 seconds
Started	Dec 24 12:48:50 PM PST 23
Finished	Dec 24 12:49:19 PM PST 23
Peak memory	223668 kb
Host	smart-25336e21-ca12-4d5f-aa83-97b5c10b2c35
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=44424918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.44424918 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.394937922
Short name	T300
Test name
Test status
Simulation time	5948716497 ps
CPU time	49.6 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:49:49 PM PST 23
Peak memory	217048 kb
Host	smart-f0af6a9f-115c-4cda-9cf7-0f03c76f458a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394937922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.394937922 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.3198368615
Short name	T495
Test name
Test status
Simulation time	36043083182 ps
CPU time	289.05 seconds
Started	Dec 24 12:49:00 PM PST 23
Finished	Dec 24 12:53:53 PM PST 23
Peak memory	243648 kb
Host	smart-3f3dedac-7c7c-411d-b343-b83559bec229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198368615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3198368615 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.3470074263
Short name	T550
Test name
Test status
Simulation time	3037552218 ps
CPU time	61.43 seconds
Started	Dec 24 12:48:57 PM PST 23
Finished	Dec 24 12:50:01 PM PST 23
Peak memory	233024 kb
Host	smart-45ee6da9-f160-414d-832e-97e25a3db3cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470074263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3470074263 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.1107711215
Short name	T541
Test name
Test status
Simulation time	969623672 ps
CPU time	3.29 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 12:49:17 PM PST 23
Peak memory	207148 kb
Host	smart-faab0cdc-3e68-4dd0-9aef-9b30d0f1c8bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107711215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1107711215 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.2317669109
Short name	T565
Test name
Test status
Simulation time	169520650 ps
CPU time	1.38 seconds
Started	Dec 24 12:49:06 PM PST 23
Finished	Dec 24 12:49:09 PM PST 23
Peak memory	215624 kb
Host	smart-1aabbf7a-cfcb-4aa6-8cf3-9dbd1b37110b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317669109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2317669109 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.708065216
Short name	T577
Test name
Test status
Simulation time	211246909963 ps
CPU time	1549.57 seconds
Started	Dec 24 12:49:05 PM PST 23
Finished	Dec 24 01:14:57 PM PST 23
Peak memory	366984 kb
Host	smart-4866c53f-3ad4-4e98-ae2d-c5968cdcbc76
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708065216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and _output.708065216 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.1599157733
Short name	T41
Test name
Test status
Simulation time	73201474012 ps
CPU time	291.72 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 12:53:55 PM PST 23
Peak memory	246468 kb
Host	smart-8bc6273c-2522-4077-981d-8dd09eedc313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599157733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1599157733 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.8816975
Short name	T963
Test name
Test status
Simulation time	3055813018 ps
CPU time	230.44 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 12:53:01 PM PST 23
Peak memory	240860 kb
Host	smart-1dd54474-d6d5-4a35-a4c1-053a570026f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8816975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.8816975 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.1252311836
Short name	T267
Test name
Test status
Simulation time	58037940936 ps
CPU time	70.36 seconds
Started	Dec 24 12:48:56 PM PST 23
Finished	Dec 24 12:50:08 PM PST 23
Peak memory	223844 kb
Host	smart-026de842-5ad9-444f-904d-f8ad770d8e30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252311836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1252311836 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.910271566
Short name	T352
Test name
Test status
Simulation time	3711873757 ps
CPU time	16.2 seconds
Started	Dec 24 12:49:09 PM PST 23
Finished	Dec 24 12:49:28 PM PST 23
Peak memory	215692 kb
Host	smart-fbfed221-fb89-44e1-89c9-07e68bb346c2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=910271566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.910271566 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.461101805
Short name	T911
Test name
Test status
Simulation time	615295812 ps
CPU time	4.21 seconds
Started	Dec 24 12:49:03 PM PST 23
Finished	Dec 24 12:49:10 PM PST 23
Peak memory	208136 kb
Host	smart-e6a59276-81e4-493a-a8ed-ee11bec2c1c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461101805 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.461101805 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.1447254683
Short name	T972
Test name
Test status
Simulation time	689941427 ps
CPU time	4.89 seconds
Started	Dec 24 12:49:02 PM PST 23
Finished	Dec 24 12:49:10 PM PST 23
Peak memory	208492 kb
Host	smart-a4bc2de9-c5e8-4ed7-84e6-d527b855f25e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447254683 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.1447254683 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.1407492989
Short name	T339
Test name
Test status
Simulation time	65754154468 ps
CPU time	1629.83 seconds
Started	Dec 24 12:49:07 PM PST 23
Finished	Dec 24 01:16:20 PM PST 23
Peak memory	374000 kb
Host	smart-25c9d30c-9e3a-4416-9078-8a68a929f486
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1407492989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1407492989 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.4273839520
Short name	T815
Test name
Test status
Simulation time	79851969092 ps
CPU time	1457.98 seconds
Started	Dec 24 12:49:01 PM PST 23
Finished	Dec 24 01:13:22 PM PST 23
Peak memory	370020 kb
Host	smart-8db35adf-b2b2-4118-a1d1-cc00b7c9bf65
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4273839520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.4273839520 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.2602897537
Short name	T295
Test name
Test status
Simulation time	279628552185 ps
CPU time	1336.51 seconds
Started	Dec 24 12:49:12 PM PST 23
Finished	Dec 24 01:11:31 PM PST 23
Peak memory	333896 kb
Host	smart-e0b4f888-c993-467c-91ae-d9c1c537ad87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2602897537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2602897537 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.1500418828
Short name	T896
Test name
Test status
Simulation time	203229222602 ps
CPU time	1065.12 seconds
Started	Dec 24 12:49:04 PM PST 23
Finished	Dec 24 01:06:52 PM PST 23
Peak memory	294768 kb
Host	smart-21447ebe-e2b4-4671-a692-c1a861372729
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1500418828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1500418828 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.3189997853
Short name	T466
Test name
Test status
Simulation time	201773241261 ps
CPU time	4128.65 seconds
Started	Dec 24 12:49:08 PM PST 23
Finished	Dec 24 01:58:00 PM PST 23
Peak memory	641912 kb
Host	smart-0de3d007-1add-48f6-b4b2-0f0bbe7b9bb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3189997853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.3189997853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.1465114819
Short name	T444
Test name
Test status
Simulation time	43982898012 ps
CPU time	3126.84 seconds
Started	Dec 24 12:49:10 PM PST 23
Finished	Dec 24 01:41:20 PM PST 23
Peak memory	556952 kb
Host	smart-8d3998c9-30f9-457d-a72f-c307727536e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1465114819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1465114819 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

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