Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102637878	1			T2	5		T3	1		T55	5
all_values[1]	102637878	1			T2	5		T3	1		T55	5
all_values[2]	102637878	1			T2	5		T3	1		T55	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721586

1

T2

7

T3

3

T55

7

auto[1]

307192048

1

T2

8

T55

8

T89

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306357873

1

T2

12

T3

3

T55

3

auto[1]

1555761

1

T2

3

T55

12

T89

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	227876	1			T3	1		T89	2		T84	1
all_values[0]	auto[0]	auto[1]	2482	1			T2	1		T55	1		T89	2
all_values[0]	auto[1]	auto[0]	101891415	1			T2	4		T55	1		T89	1
all_values[0]	auto[1]	auto[1]	516105	1			T55	3		T56	3		T148	1
all_values[1]	auto[0]	auto[0]	232052	1			T2	3		T3	1		T55	1
all_values[1]	auto[0]	auto[1]	1829	1			T2	1		T55	3		T58	3
all_values[1]	auto[1]	auto[0]	101887239	1			T2	1		T89	2		T57	3
all_values[1]	auto[1]	auto[1]	516758	1			T55	1		T89	2		T58	2
all_values[2]	auto[0]	auto[0]	255374	1			T2	1		T3	1		T89	1
all_values[2]	auto[0]	auto[1]	1973	1			T2	1		T55	2		T58	2
all_values[2]	auto[1]	auto[0]	101863917	1			T2	3		T55	1		T89	2
all_values[2]	auto[1]	auto[1]	516614	1			T55	2		T89	2		T58	3