Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349603 |
1 |
|
|
T4 |
780 |
|
T5 |
18 |
|
T6 |
4674 |
auto[1] |
356002 |
1 |
|
|
T13 |
256 |
|
T14 |
16 |
|
T15 |
74 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176928 |
1 |
|
|
T4 |
188 |
|
T5 |
5 |
|
T6 |
1140 |
lower_val |
175251 |
1 |
|
|
T4 |
154 |
|
T5 |
6 |
|
T6 |
1198 |
zero_val |
2115 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
352224 |
1 |
|
|
T4 |
392 |
|
T5 |
10 |
|
T6 |
2348 |
lower_val |
353363 |
1 |
|
|
T4 |
388 |
|
T5 |
8 |
|
T6 |
2326 |
zero_val |
18 |
1 |
|
|
T17 |
2 |
|
T136 |
2 |
|
T137 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43703 |
1 |
|
|
T4 |
100 |
|
T5 |
4 |
|
T6 |
584 |
higher_val |
higher_val |
auto[1] |
44759 |
1 |
|
|
T13 |
30 |
|
T14 |
1 |
|
T15 |
8 |
higher_val |
lower_val |
auto[0] |
43937 |
1 |
|
|
T4 |
88 |
|
T5 |
1 |
|
T6 |
556 |
higher_val |
lower_val |
auto[1] |
44526 |
1 |
|
|
T13 |
30 |
|
T14 |
6 |
|
T15 |
12 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T138 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T17 |
1 |
|
T139 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43163 |
1 |
|
|
T4 |
73 |
|
T5 |
4 |
|
T6 |
602 |
lower_val |
higher_val |
auto[1] |
43986 |
1 |
|
|
T13 |
32 |
|
T14 |
2 |
|
T15 |
10 |
lower_val |
lower_val |
auto[0] |
43755 |
1 |
|
|
T4 |
81 |
|
T5 |
2 |
|
T6 |
596 |
lower_val |
lower_val |
auto[1] |
44342 |
1 |
|
|
T13 |
24 |
|
T14 |
1 |
|
T15 |
8 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T140 |
1 |
|
T138 |
1 |
|
T141 |
1 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T17 |
1 |
|
T136 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
752 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
293 |
1 |
|
|
T15 |
2 |
|
T28 |
3 |
|
T29 |
1 |
zero_val |
lower_val |
auto[0] |
762 |
1 |
|
|
T4 |
1 |
|
T6 |
4 |
|
T13 |
4 |
zero_val |
lower_val |
auto[1] |
308 |
1 |
|
|
T13 |
2 |
|
T28 |
3 |
|
T29 |
2 |