Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10354	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9436	1			T4	17		T6	30		T17	23
len_5001_7500	15666	1			T4	17		T6	30		T13	5
len_2501_5000	9484	1			T4	17		T6	30		T17	16
len_1025_2500	5521	1			T4	10		T6	16		T17	11
len_769_1024	6349	1			T4	2		T6	4		T13	25
len_513_768	6755	1			T4	2		T6	2		T13	30
len_257_512	21365	1			T4	2		T6	244		T13	46
len_0_256	260705	1			T4	290		T5	9		T6	1897
len_keccak_block_sizes[72]	725	1			T4	2		T6	3		T29	1
len_keccak_block_sizes[104]	625	1			T4	2		T6	3		T28	1
len_keccak_block_sizes[136]	522	1			T4	2		T6	3		T35	1
len_keccak_block_sizes[144]	428	1			T4	2		T6	3		T13	1
len_keccak_block_sizes[168]	319	1			T6	3		T136	3		T155	3
len_1	765	1			T4	2		T6	3		T28	2
len_0	1299	1			T4	2		T6	3		T13	1