Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102637878	1			T2	5		T3	1		T55	5
all_pins[1]	102637878	1			T2	5		T3	1		T55	5
all_pins[2]	102637878	1			T2	5		T3	1		T55	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	248320874	1			T2	15		T3	3		T55	9
values[0x1]	59592760	1			T55	6		T89	2		T57	4
transitions[0x0=>0x1]	59138275	1			T55	5		T89	2		T57	2
transitions[0x1=>0x0]	59138296	1			T55	5		T89	2		T57	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102121773	1			T2	5		T3	1		T55	2
all_pins[0]	values[0x1]	516105	1			T55	3		T56	3		T148	1
all_pins[0]	transitions[0x0=>0x1]	220522	1			T55	3		T56	3		T148	1
all_pins[0]	transitions[0x1=>0x0]	58432712	1			T55	1		T57	2		T58	3
all_pins[1]	values[0x0]	43909583	1			T2	5		T3	1		T55	4
all_pins[1]	values[0x1]	58728295	1			T55	1		T57	2		T58	3
all_pins[1]	transitions[0x0=>0x1]	58571505	1			T55	1		T58	3		T148	4
all_pins[1]	transitions[0x1=>0x0]	191570	1			T55	2		T89	2		T56	2
all_pins[2]	values[0x0]	102289518	1			T2	5		T3	1		T55	3
all_pins[2]	values[0x1]	348360	1			T55	2		T89	2		T57	2
all_pins[2]	transitions[0x0=>0x1]	346248	1			T55	1		T89	2		T57	2
all_pins[2]	transitions[0x1=>0x0]	514014	1			T55	2		T56	3		T148	1