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 LINE       70
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T51,T110
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T51,T110,T111

 LINE       89
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T51,T110,T111
1	0	0	Covered	T51,T110,T111

 LINE       139
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[1024:1535]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2))
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T51

 LINE       139
 SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2)
                 ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T51

 LINE       178
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T51,T110,T111
0	1	0	Covered	T3,T84,T87
1	0	0	Covered	T3,T87,T88

 LINE       178
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T51,T110

 LINE       679
 EXPRESSION (cfg_shadowed_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T51,T82
1	1	Covered	T52,T50,T81

 LINE       1303
 EXPRESSION (entropy_period_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1390
 EXPRESSION (entropy_refresh_threshold_shadowed_we & cfg_regwen_qs)
             ------------------1------------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T51,T98
1	1	Covered	T1,T52,T81

 LINE       1540
 EXPRESSION (key_share0_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1564
 EXPRESSION (key_share0_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1588
 EXPRESSION (key_share0_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1612
 EXPRESSION (key_share0_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1636
 EXPRESSION (key_share0_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1660
 EXPRESSION (key_share0_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1684
 EXPRESSION (key_share0_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1708
 EXPRESSION (key_share0_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1732
 EXPRESSION (key_share0_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1756
 EXPRESSION (key_share0_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1780
 EXPRESSION (key_share0_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1804
 EXPRESSION (key_share0_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1828
 EXPRESSION (key_share0_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1852
 EXPRESSION (key_share0_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1876
 EXPRESSION (key_share0_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1900
 EXPRESSION (key_share0_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1924
 EXPRESSION (key_share1_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1948
 EXPRESSION (key_share1_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1972
 EXPRESSION (key_share1_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       1996
 EXPRESSION (key_share1_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2020
 EXPRESSION (key_share1_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2044
 EXPRESSION (key_share1_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2068
 EXPRESSION (key_share1_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2092
 EXPRESSION (key_share1_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2116
 EXPRESSION (key_share1_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2140
 EXPRESSION (key_share1_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2164
 EXPRESSION (key_share1_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2188
 EXPRESSION (key_share1_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2212
 EXPRESSION (key_share1_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2236
 EXPRESSION (key_share1_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2260
 EXPRESSION (key_share1_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2284
 EXPRESSION (key_share1_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2304
 EXPRESSION (key_len_we & cfg_regwen_qs)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2336
 EXPRESSION (prefix_0_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2368
 EXPRESSION (prefix_1_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2400
 EXPRESSION (prefix_2_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2432
 EXPRESSION (prefix_3_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2464
 EXPRESSION (prefix_4_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2496
 EXPRESSION (prefix_5_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2528
 EXPRESSION (prefix_6_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2560
 EXPRESSION (prefix_7_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2592
 EXPRESSION (prefix_8_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2624
 EXPRESSION (prefix_9_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2656
 EXPRESSION (prefix_10_we & cfg_regwen_qs)
             ------1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T50,T51
1	1	Covered	T1,T52,T50

 LINE       2716
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2717
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2718
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2719
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2720
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_REGWEN_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2721
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_SHADOWED_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2722
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T50

 LINE       2723
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2724
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_PERIOD_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2725
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2726
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2727
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2728
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2729
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2730
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2731
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2732
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2733
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2734
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2735
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2736
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2737
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2738
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2739
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2740
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2741
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2742
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2743
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2744
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2745
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2746
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2747
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2748
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2749
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2750
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2751
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2752
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2753
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2754
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2755
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2756
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2757
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2758
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2759
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2760
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2761
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2762
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2763
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2764
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_LEN_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2765
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2766
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2767
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2768
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2769
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2770
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2771
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2772
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2773
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_8_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2774
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_9_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2775
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_10_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2776
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T52

 LINE       2779
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2779
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2783
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T84,T87

 LINE       2783
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b1111 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
61 (addr_hit[60] & ((\|(4'...	Covered	T1,T3,T52
60 (addr_hit[59] & ((\|(4'...	Covered	T1,T3,T50
59 (addr_hit[58] & ((\|(4'...	Covered	T1,T3,T51
58 (addr_hit[57] & ((\|(4'...	Covered	T1,T3,T50
57 (addr_hit[56] & ((\|(4'...	Covered	T1,T3,T52
56 (addr_hit[55] & ((\|(4'...	Covered	T1,T3,T50
55 (addr_hit[54] & ((\|(4'...	Covered	T1,T3,T50
54 (addr_hit[53] & ((\|(4'...	Covered	T1,T3,T52
53 (addr_hit[52] & ((\|(4'...	Covered	T1,T3,T52
52 (addr_hit[51] & ((\|(4'...	Covered	T1,T3,T52
51 (addr_hit[50] & ((\|(4'...	Covered	T1,T3,T52
50 (addr_hit[49] & ((\|(4'...	Covered	T1,T3,T52
49 (addr_hit[48] & ((\|(4'...	Covered	T1,T3,T50
48 (addr_hit[47] & ((\|(4'...	Covered	T1,T3,T52
47 (addr_hit[46] & ((\|(4'...	Covered	T1,T3,T50
46 (addr_hit[45] & ((\|(4'...	Covered	T1,T3,T52
45 (addr_hit[44] & ((\|(4'...	Covered	T3,T50,T81
44 (addr_hit[43] & ((\|(4'...	Covered	T1,T3,T52
43 (addr_hit[42] & ((\|(4'...	Covered	T1,T3,T52
42 (addr_hit[41] & ((\|(4'...	Covered	T1,T3,T51
41 (addr_hit[40] & ((\|(4'...	Covered	T1,T3,T50
40 (addr_hit[39] & ((\|(4'...	Covered	T1,T3,T50
39 (addr_hit[38] & ((\|(4'...	Covered	T1,T3,T52
38 (addr_hit[37] & ((\|(4'...	Covered	T1,T3,T52
37 (addr_hit[36] & ((\|(4'...	Covered	T1,T3,T50
36 (addr_hit[35] & ((\|(4'...	Covered	T1,T3,T51
35 (addr_hit[34] & ((\|(4'...	Covered	T1,T3,T50
34 (addr_hit[33] & ((\|(4'...	Covered	T1,T3,T52
33 (addr_hit[32] & ((\|(4'...	Covered	T1,T3,T52
32 (addr_hit[31] & ((\|(4'...	Covered	T1,T3,T50
31 (addr_hit[30] & ((\|(4'...	Covered	T1,T3,T52
30 (addr_hit[29] & ((\|(4'...	Covered	T3,T50,T51
29 (addr_hit[28] & ((\|(4'...	Covered	T1,T3,T52
28 (addr_hit[27] & ((\|(4'...	Covered	T1,T3,T50
27 (addr_hit[26] & ((\|(4'...	Covered	T1,T3,T51
26 (addr_hit[25] & ((\|(4'...	Covered	T1,T3,T52
25 (addr_hit[24] & ((\|(4'...	Covered	T1,T3,T52
24 (addr_hit[23] & ((\|(4'...	Covered	T1,T3,T52
23 (addr_hit[22] & ((\|(4'...	Covered	T1,T3,T50
22 (addr_hit[21] & ((\|(4'...	Covered	T1,T3,T50
21 (addr_hit[20] & ((\|(4'...	Covered	T1,T3,T51
20 (addr_hit[19] & ((\|(4'...	Covered	T1,T3,T52
19 (addr_hit[18] & ((\|(4'...	Covered	T1,T3,T52
18 (addr_hit[17] & ((\|(4'...	Covered	T1,T3,T52
17 (addr_hit[16] & ((\|(4'...	Covered	T3,T50,T81
16 (addr_hit[15] & ((\|(4'...	Covered	T1,T3,T52
15 (addr_hit[14] & ((\|(4'...	Covered	T1,T3,T52
14 (addr_hit[13] & ((\|(4'...	Covered	T1,T3,T52
13 (addr_hit[12] & ((\|(4'...	Covered	T1,T3,T50
12 (addr_hit[11] & ((\|(4'...	Covered	T1,T3,T52
11 (addr_hit[10] & ((\|(4'...	Covered	T1,T3,T52
10 (addr_hit[9] & ((\|(4'b...	Covered	T1,T3,T81
9 (addr_hit[8] & ((\|(4'b...	Covered	T1,T3,T52
8 (addr_hit[7] & ((\|(4'b...	Covered	T1,T3,T52
7 (addr_hit[6] & ((\|(4'b...	Covered	T3,T50,T51
6 (addr_hit[5] & ((\|(4'b...	Covered	T1,T3,T52
5 (addr_hit[4] & ((\|(4'b...	Covered	T3,T50,T51
4 (addr_hit[3] & ((\|(4'b...	Covered	T3,T51,T82
3 (addr_hit[2] & ((\|(4'b...	Covered	T1,T3,T55
2 (addr_hit[1] & ((\|(4'b...	Covered	T1,T2,T3
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       2783
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T52,T55
1	1	Covered	T1,T2,T3

 LINE       2783
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T52
1	1	Covered	T1,T2,T3

 LINE       2783
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T55
1	1	Covered	T1,T3,T55

 LINE       2783
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T3,T51,T82

 LINE       2783
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T52
1	1	Covered	T3,T50,T51

 LINE       2783
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T50,T81
1	1	Covered	T1,T3,T52

 LINE       2783
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T51,T83
1	1	Covered	T3,T50,T51

 LINE       2783
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T81
1	1	Covered	T1,T3,T52

 LINE       2783
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T1,T3,T52

 LINE       2783
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T1,T3,T81

 LINE       2783
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T1,T3,T52

 LINE       2783
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T1,T3,T52

 LINE       2783
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T52,T50
1	1	Covered	T1,T3,T50