Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343576 |
1 |
|
|
T4 |
20 |
|
T5 |
2 |
|
T6 |
2 |
auto[1] |
362210 |
1 |
|
|
T4 |
44 |
|
T5 |
746 |
|
T6 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176601 |
1 |
|
|
T4 |
16 |
|
T5 |
210 |
|
T6 |
210 |
lower_val |
174545 |
1 |
|
|
T4 |
14 |
|
T5 |
177 |
|
T6 |
210 |
zero_val |
2079 |
1 |
|
|
T4 |
5 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
353140 |
1 |
|
|
T4 |
44 |
|
T5 |
364 |
|
T6 |
382 |
lower_val |
352644 |
1 |
|
|
T4 |
20 |
|
T5 |
384 |
|
T6 |
398 |
zero_val |
2 |
1 |
|
|
T142 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42885 |
1 |
|
|
T5 |
1 |
|
T13 |
22 |
|
T14 |
11 |
higher_val |
higher_val |
auto[1] |
45323 |
1 |
|
|
T4 |
11 |
|
T5 |
101 |
|
T6 |
100 |
higher_val |
lower_val |
auto[0] |
42960 |
1 |
|
|
T13 |
12 |
|
T14 |
11 |
|
T16 |
30 |
higher_val |
lower_val |
auto[1] |
45433 |
1 |
|
|
T4 |
5 |
|
T5 |
108 |
|
T6 |
110 |
lower_val |
higher_val |
auto[0] |
42455 |
1 |
|
|
T4 |
3 |
|
T13 |
25 |
|
T14 |
1 |
lower_val |
higher_val |
auto[1] |
44585 |
1 |
|
|
T4 |
8 |
|
T5 |
86 |
|
T6 |
104 |
lower_val |
lower_val |
auto[0] |
42720 |
1 |
|
|
T4 |
1 |
|
T13 |
9 |
|
T14 |
3 |
lower_val |
lower_val |
auto[1] |
44785 |
1 |
|
|
T4 |
2 |
|
T5 |
91 |
|
T6 |
106 |
zero_val |
higher_val |
auto[0] |
758 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
292 |
1 |
|
|
T4 |
4 |
|
T15 |
1 |
|
T18 |
3 |
zero_val |
lower_val |
auto[0] |
721 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
308 |
1 |
|
|
T15 |
1 |
|
T18 |
1 |
|
T143 |
2 |