Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10351 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 9200 1 T4 2 T5 19 T6 17
len_5001_7500 14885 1 T5 18 T6 17 T13 41
len_2501_5000 9387 1 T5 18 T6 17 T13 8
len_1025_2500 5520 1 T5 11 T6 10 T13 1
len_769_1024 6752 1 T4 2 T5 2 T6 2
len_513_768 7178 1 T4 3 T5 2 T6 2
len_257_512 21760 1 T4 2 T5 2 T6 2
len_0_256 260415 1 T4 17 T5 274 T6 290
len_keccak_block_sizes[72] 726 1 T5 2 T6 2 T15 2
len_keccak_block_sizes[104] 627 1 T5 2 T6 2 T15 2
len_keccak_block_sizes[136] 528 1 T5 2 T6 2 T16 1
len_keccak_block_sizes[144] 428 1 T6 2 T16 1 T44 3
len_keccak_block_sizes[168] 332 1 T18 1 T44 3 T162 3
len_1 771 1 T5 2 T6 2 T15 2
len_0 1247 1 T5 2 T6 2 T15 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%