Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101197443	1			T1	8		T3	1		T60	5
all_pins[1]	101197443	1			T1	8		T3	1		T60	5
all_pins[2]	101197443	1			T1	8		T3	1		T60	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	245133342	1			T1	20		T3	3		T60	12
values[0x1]	58458987	1			T1	4		T60	3		T63	5
transitions[0x0=>0x1]	57975462	1			T1	3		T60	3		T63	4
transitions[0x1=>0x0]	57975487	1			T1	3		T60	3		T63	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100681442	1			T1	8		T3	1		T60	5
all_pins[0]	values[0x1]	516001	1			T61	2		T62	1		T140	2
all_pins[0]	transitions[0x0=>0x1]	221123	1			T61	2		T140	2		T153	2
all_pins[0]	transitions[0x1=>0x0]	57241589	1			T1	2		T60	2		T63	4
all_pins[1]	values[0x0]	43660976	1			T1	6		T3	1		T60	3
all_pins[1]	values[0x1]	57536467	1			T1	2		T60	2		T63	4
all_pins[1]	transitions[0x0=>0x1]	57350296	1			T1	1		T60	2		T63	3
all_pins[1]	transitions[0x1=>0x0]	220348	1			T1	1		T60	1		T140	1
all_pins[2]	values[0x0]	100790924	1			T1	6		T3	1		T60	4
all_pins[2]	values[0x1]	406519	1			T1	2		T60	1		T63	1
all_pins[2]	transitions[0x0=>0x1]	404043	1			T1	2		T60	1		T63	1
all_pins[2]	transitions[0x1=>0x0]	513550	1			T61	2		T140	1		T153	1