Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	744	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5938	1			T4	1		T13	13		T14	5
len_601_800	13484	1			T4	4		T13	26		T14	11
len_401_600	9112	1			T4	4		T13	12		T14	2
len_201_400	16842	1			T4	3		T13	8		T14	1
len_65_200	74734	1			T4	3		T13	3		T16	17
len_min_for_xof_require_squeeze	1017	1			T44	9		T33	1		T34	1
len_keccak_block_sizes[72]	751	1			T44	9		T50	1		T102	2
len_keccak_block_sizes[104]	762	1			T44	9		T102	1		T162	5
len_keccak_block_sizes[136]	762	1			T44	9		T102	1		T162	5
len_keccak_block_sizes[144]	295	1			T18	1		T162	5		T164	1
len_keccak_block_sizes[168]	283	1			T16	1		T162	5		T69	5
len_datapath_width	14462	1			T4	3		T13	1		T17	1
len_2_63	216225	1			T4	10		T5	374		T6	390
len_1	70	1			T16	1		T102	1		T33	1