Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	103874928	1			T59	1		T62	5		T63	8
all_values[1]	103874928	1			T59	1		T62	5		T63	8
all_values[2]	103874928	1			T59	1		T62	5		T63	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641035

1

T59

3

T62

10

T63

16

auto[1]

310983749

1

T62

5

T63

8

T64

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310059078

1

T59

3

T62

9

T63

6

auto[1]

1565706

1

T62

6

T63

18

T64

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	193526	1			T59	1		T63	1		T64	4
all_values[0]	auto[0]	auto[1]	2334	1			T62	1		T63	4		T64	1
all_values[0]	auto[1]	auto[0]	103159500	1			T62	3		T63	1		T64	1
all_values[0]	auto[1]	auto[1]	519568	1			T62	1		T63	2		T64	2
all_values[1]	auto[0]	auto[0]	238861	1			T59	1		T62	3		T63	2
all_values[1]	auto[0]	auto[1]	1910	1			T62	1		T63	4		T64	2
all_values[1]	auto[1]	auto[0]	103114165	1			T64	4		T65	4		T137	4
all_values[1]	auto[1]	auto[1]	519992	1			T62	1		T63	2		T64	1
all_values[2]	auto[0]	auto[0]	202618	1			T59	1		T62	3		T63	1
all_values[2]	auto[0]	auto[1]	1786	1			T62	2		T63	4		T64	1
all_values[2]	auto[1]	auto[0]	103150408	1			T63	1		T64	2		T65	1
all_values[2]	auto[1]	auto[1]	520116	1			T63	2		T64	2		T137	1