Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
388571 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
90 |
auto[1] |
321408 |
1 |
|
|
T4 |
778 |
|
T5 |
124 |
|
T6 |
78 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
177389 |
1 |
|
|
T4 |
172 |
|
T5 |
28 |
|
T6 |
43 |
lower_val |
176027 |
1 |
|
|
T4 |
204 |
|
T5 |
26 |
|
T6 |
31 |
zero_val |
2018 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T6 |
2 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
354181 |
1 |
|
|
T4 |
372 |
|
T5 |
76 |
|
T6 |
86 |
lower_val |
355790 |
1 |
|
|
T4 |
408 |
|
T5 |
50 |
|
T6 |
82 |
zero_val |
8 |
1 |
|
|
T141 |
2 |
|
T142 |
2 |
|
T143 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48574 |
1 |
|
|
T5 |
1 |
|
T6 |
14 |
|
T13 |
1 |
higher_val |
higher_val |
auto[1] |
39775 |
1 |
|
|
T4 |
78 |
|
T5 |
18 |
|
T6 |
10 |
higher_val |
lower_val |
auto[0] |
48613 |
1 |
|
|
T6 |
15 |
|
T15 |
75 |
|
T17 |
4 |
higher_val |
lower_val |
auto[1] |
40424 |
1 |
|
|
T4 |
94 |
|
T5 |
9 |
|
T6 |
4 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T142 |
2 |
|
T143 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
48511 |
1 |
|
|
T6 |
9 |
|
T15 |
55 |
|
T17 |
6 |
lower_val |
higher_val |
auto[1] |
39701 |
1 |
|
|
T4 |
116 |
|
T5 |
15 |
|
T6 |
6 |
lower_val |
lower_val |
auto[0] |
47934 |
1 |
|
|
T4 |
1 |
|
T6 |
6 |
|
T14 |
1 |
lower_val |
lower_val |
auto[1] |
39881 |
1 |
|
|
T4 |
87 |
|
T5 |
11 |
|
T6 |
10 |
zero_val |
higher_val |
auto[0] |
746 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
261 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T30 |
1 |
zero_val |
lower_val |
auto[0] |
761 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
250 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |