Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9663	1			T4	17		T5	5		T13	19
len_5001_7500	15801	1			T4	17		T5	13		T13	18
len_2501_5000	9540	1			T4	17		T13	18		T14	34
len_1025_2500	5547	1			T4	10		T5	3		T13	11
len_769_1024	6754	1			T4	2		T6	14		T13	2
len_513_768	7169	1			T4	2		T5	1		T6	16
len_257_512	21914	1			T4	2		T5	1		T6	6
len_0_256	260927	1			T4	290		T5	40		T6	21
len_keccak_block_sizes[72]	729	1			T4	2		T13	2		T14	2
len_keccak_block_sizes[104]	630	1			T4	2		T13	2		T15	2
len_keccak_block_sizes[136]	519	1			T4	2		T13	2		T50	1
len_keccak_block_sizes[144]	415	1			T4	2		T52	3		T120	2
len_keccak_block_sizes[168]	322	1			T52	3		T165	3		T166	3
len_1	748	1			T4	2		T13	2		T14	2
len_0	1290	1			T4	2		T5	3		T13	2