Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	103874928	1			T59	1		T62	5		T63	8
all_pins[1]	103874928	1			T59	1		T62	5		T63	8
all_pins[2]	103874928	1			T59	1		T62	5		T63	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	250949937	1			T59	3		T62	14		T63	19
values[0x1]	60674847	1			T62	1		T63	5		T64	7
transitions[0x0=>0x1]	60203492	1			T62	1		T63	5		T64	6
transitions[0x1=>0x0]	60203515	1			T62	1		T63	5		T64	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103355360	1			T59	1		T62	4		T63	6
all_pins[0]	values[0x1]	519568	1			T62	1		T63	2		T64	2
all_pins[0]	transitions[0x0=>0x1]	221399	1			T62	1		T63	2		T64	2
all_pins[0]	transitions[0x1=>0x0]	59483144	1			T63	2		T64	3		T65	2
all_pins[1]	values[0x0]	44093615	1			T59	1		T62	5		T63	6
all_pins[1]	values[0x1]	59781313	1			T63	2		T64	3		T65	2
all_pins[1]	transitions[0x0=>0x1]	59610416	1			T63	2		T64	3		T65	1
all_pins[1]	transitions[0x1=>0x0]	203069	1			T63	1		T64	2		T150	1
all_pins[2]	values[0x0]	103500962	1			T59	1		T62	5		T63	7
all_pins[2]	values[0x1]	373966	1			T63	1		T64	2		T65	1
all_pins[2]	transitions[0x0=>0x1]	371677	1			T63	1		T64	1		T150	2
all_pins[2]	transitions[0x1=>0x0]	517302	1			T62	1		T63	2		T64	1