Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	781	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6365	1			T5	2		T6	4		T16	22
len_601_800	14314	1			T5	9		T6	22		T16	45
len_401_600	9449	1			T5	5		T6	9		T16	33
len_201_400	17074	1			T5	3		T6	10		T16	10
len_65_200	74865	1			T5	23		T6	1		T16	5
len_min_for_xof_require_squeeze	1015	1			T50	1		T52	10		T104	1
len_keccak_block_sizes[72]	765	1			T5	1		T51	1		T52	5
len_keccak_block_sizes[104]	757	1			T52	5		T104	3		T26	1
len_keccak_block_sizes[136]	770	1			T5	2		T52	5		T104	1
len_keccak_block_sizes[144]	290	1			T52	5		T166	5		T167	5
len_keccak_block_sizes[168]	294	1			T52	5		T104	1		T166	5
len_datapath_width	14501	1			T5	1		T6	3		T14	246
len_2_63	216396	1			T4	390		T5	20		T6	34
len_1	60	1			T19	1		T50	1		T104	1