Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::state_read_mask_cg

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	3	5	62.50

Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
share	2	0	2	100.00	100	1	1	2
state_read_mask	4	0	4	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_mask_share_cross	8	3	5	62.50	100	1	1	0

Summary for Variable share

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for share

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11644793

1

T4

2730

T5

4939

T6

8852

auto[1]

27098716

1

T4

19500

T5

7886

T6

13674

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Summary for Variable state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for state_read_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	38619787	1			T4	22230		T5	12777		T6	22489
triple_byte_access	41237	1			T5	15		T6	9		T16	30
halfword_access	41445	1			T5	18		T6	13		T16	33
byte_access	41040	1			T5	15		T6	15		T16	29

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Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	3	5	62.50	3

Automatically Generated Cross Bins for state_mask_share_cross

Uncovered bins

share	state_read_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[triple_byte_access , halfword_access , byte_access]	--	--	3

Covered bins

share	state_read_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	11521071	1			T4	2730		T5	4891		T6	8815
auto[0]	triple_byte_access	41237	1			T5	15		T6	9		T16	30
auto[0]	halfword_access	41445	1			T5	18		T6	13		T16	33
auto[0]	byte_access	41040	1			T5	15		T6	15		T16	29
auto[1]	word_access	27098716	1			T4	19500		T5	7886		T6	13674