Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	82101493	1			T1	7		T2	8		T63	5
all_values[1]	82101493	1			T1	7		T2	8		T63	5
all_values[2]	82101493	1			T1	7		T2	8		T63	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609119

1

T1

12

T2

13

T63

6

auto[1]

245695360

1

T1

9

T2

11

T63

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245033136

1

T1

6

T2

15

T63

6

auto[1]

1271343

1

T1

15

T2

9

T63

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	202179	1			T2	4		T57	4		T58	1
all_values[0]	auto[0]	auto[1]	2155	1			T1	3		T2	1		T63	1
all_values[0]	auto[1]	auto[0]	81475533	1			T1	2		T2	1		T63	2
all_values[0]	auto[1]	auto[1]	421626	1			T1	2		T2	2		T63	2
all_values[1]	auto[0]	auto[0]	197887	1			T1	2		T2	1		T63	1
all_values[1]	auto[0]	auto[1]	1576	1			T1	3		T2	2		T63	3
all_values[1]	auto[1]	auto[0]	81479825	1			T2	4		T63	1		T85	2
all_values[1]	auto[1]	auto[1]	422205	1			T1	2		T2	1		T57	1
all_values[2]	auto[0]	auto[0]	203876	1			T1	2		T2	4		T63	1
all_values[2]	auto[0]	auto[1]	1446	1			T1	2		T2	1		T57	1
all_values[2]	auto[1]	auto[0]	81473836	1			T2	1		T63	1		T57	3
all_values[2]	auto[1]	auto[1]	422335	1			T1	3		T2	2		T63	3