Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
278318 |
1 |
|
|
T4 |
18 |
|
T5 |
68 |
|
T6 |
2 |
auto[1] |
298320 |
1 |
|
|
T6 |
16 |
|
T13 |
16 |
|
T14 |
154 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
143984 |
1 |
|
|
T4 |
4 |
|
T5 |
10 |
|
T6 |
5 |
lower_val |
143451 |
1 |
|
|
T4 |
5 |
|
T5 |
15 |
|
T6 |
8 |
zero_val |
1669 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
288444 |
1 |
|
|
T4 |
6 |
|
T5 |
34 |
|
T6 |
10 |
lower_val |
288184 |
1 |
|
|
T4 |
12 |
|
T5 |
34 |
|
T6 |
8 |
zero_val |
10 |
1 |
|
|
T135 |
2 |
|
T136 |
2 |
|
T137 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
34587 |
1 |
|
|
T4 |
2 |
|
T5 |
4 |
|
T17 |
93 |
higher_val |
higher_val |
auto[1] |
37363 |
1 |
|
|
T6 |
2 |
|
T13 |
6 |
|
T14 |
15 |
higher_val |
lower_val |
auto[0] |
34738 |
1 |
|
|
T4 |
2 |
|
T5 |
6 |
|
T17 |
97 |
higher_val |
lower_val |
auto[1] |
37291 |
1 |
|
|
T6 |
3 |
|
T13 |
2 |
|
T14 |
20 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T136 |
1 |
|
T138 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T135 |
1 |
|
T137 |
2 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
34371 |
1 |
|
|
T4 |
2 |
|
T5 |
7 |
|
T13 |
1 |
lower_val |
higher_val |
auto[1] |
37557 |
1 |
|
|
T6 |
5 |
|
T13 |
3 |
|
T14 |
19 |
lower_val |
lower_val |
auto[0] |
34461 |
1 |
|
|
T4 |
3 |
|
T5 |
8 |
|
T6 |
1 |
lower_val |
lower_val |
auto[1] |
37061 |
1 |
|
|
T6 |
2 |
|
T13 |
1 |
|
T14 |
17 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T135 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
597 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
249 |
1 |
|
|
T25 |
1 |
|
T139 |
1 |
|
T37 |
3 |
zero_val |
lower_val |
auto[0] |
580 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
243 |
1 |
|
|
T25 |
3 |
|
T139 |
3 |
|
T121 |
2 |