Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	8263	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	7525	1			T17	19		T50	36		T51	15
len_5001_7500	12260	1			T17	18		T50	90		T51	64
len_2501_5000	7742	1			T17	18		T50	22		T51	14
len_1025_2500	4519	1			T17	11		T50	11		T51	2
len_769_1024	5361	1			T5	6		T15	1		T16	20
len_513_768	5673	1			T5	11		T15	5		T16	24
len_257_512	16656	1			T5	9		T15	3		T16	15
len_0_256	214148	1			T4	9		T5	4		T6	9
len_keccak_block_sizes[72]	588	1			T17	2		T162	3		T46	2
len_keccak_block_sizes[104]	516	1			T17	2		T162	3		T46	2
len_keccak_block_sizes[136]	426	1			T17	2		T162	3		T46	2
len_keccak_block_sizes[144]	343	1			T162	3		T47	3		T163	3
len_keccak_block_sizes[168]	265	1			T162	3		T47	3		T163	3
len_1	633	1			T17	2		T162	3		T46	2
len_0	1054	1			T14	3		T17	2		T50	6