Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	82101493	1			T1	7		T2	8		T63	5
all_pins[1]	82101493	1			T1	7		T2	8		T63	5
all_pins[2]	82101493	1			T1	7		T2	8		T63	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	197508851	1			T1	18		T2	19		T63	9
values[0x1]	48795628	1			T1	3		T2	5		T63	6
transitions[0x0=>0x1]	48450247	1			T1	2		T2	4		T63	5
transitions[0x1=>0x0]	48450275	1			T1	2		T2	4		T63	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81679867	1			T1	5		T2	6		T63	3
all_pins[0]	values[0x1]	421626	1			T1	2		T2	2		T63	2
all_pins[0]	transitions[0x0=>0x1]	181356	1			T1	1		T2	1		T63	2
all_pins[0]	transitions[0x1=>0x0]	47897800	1			T2	2		T63	1		T85	3
all_pins[1]	values[0x0]	33963423	1			T1	6		T2	5		T63	4
all_pins[1]	values[0x1]	48138070	1			T1	1		T2	3		T63	1
all_pins[1]	transitions[0x0=>0x1]	48034398	1			T1	1		T2	3		T63	1
all_pins[1]	transitions[0x1=>0x0]	132260	1			T63	3		T57	2		T82	1
all_pins[2]	values[0x0]	81865561	1			T1	7		T2	8		T63	2
all_pins[2]	values[0x1]	235932	1			T63	3		T57	2		T82	1
all_pins[2]	transitions[0x0=>0x1]	234493	1			T63	2		T57	1		T85	3
all_pins[2]	transitions[0x1=>0x0]	420215	1			T1	2		T2	2		T63	1