Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	571	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4736	1			T5	3		T15	2		T16	16
len_601_800	10894	1			T5	12		T15	3		T16	30
len_401_600	7239	1			T5	4		T15	4		T16	19
len_201_400	14972	1			T5	1		T15	1		T16	4
len_65_200	61449	1			T5	2		T14	42		T15	2
len_min_for_xof_require_squeeze	832	1			T5	1		T50	1		T162	9
len_keccak_block_sizes[72]	604	1			T162	9		T47	5		T139	2
len_keccak_block_sizes[104]	593	1			T162	9		T47	5		T163	9
len_keccak_block_sizes[136]	600	1			T50	2		T162	9		T47	5
len_keccak_block_sizes[144]	255	1			T47	5		T166	1		T167	5
len_keccak_block_sizes[168]	265	1			T47	5		T36	1		T167	5
len_datapath_width	12144	1			T4	3		T6	3		T13	3
len_2_63	175359	1			T4	6		T5	3		T6	6
len_1	53	1			T14	1		T50	1		T139	2