Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9243949 |
1 |
|
|
T4 |
96 |
|
T5 |
4568 |
|
T6 |
96 |
auto[1] |
21743325 |
1 |
|
|
T4 |
450 |
|
T5 |
7228 |
|
T6 |
450 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
30886693 |
1 |
|
|
T4 |
546 |
|
T5 |
11774 |
|
T6 |
546 |
triple_byte_access |
33465 |
1 |
|
|
T5 |
9 |
|
T14 |
16 |
|
T15 |
4 |
halfword_access |
33631 |
1 |
|
|
T5 |
9 |
|
T14 |
21 |
|
T15 |
2 |
byte_access |
33485 |
1 |
|
|
T5 |
4 |
|
T14 |
19 |
|
T15 |
3 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
9143368 |
1 |
|
|
T4 |
96 |
|
T5 |
4546 |
|
T6 |
96 |
auto[0] |
triple_byte_access |
33465 |
1 |
|
|
T5 |
9 |
|
T14 |
16 |
|
T15 |
4 |
auto[0] |
halfword_access |
33631 |
1 |
|
|
T5 |
9 |
|
T14 |
21 |
|
T15 |
2 |
auto[0] |
byte_access |
33485 |
1 |
|
|
T5 |
4 |
|
T14 |
19 |
|
T15 |
3 |
auto[1] |
word_access |
21743325 |
1 |
|
|
T4 |
450 |
|
T5 |
7228 |
|
T6 |
450 |