Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 223 1 T1 7 T2 7 T63 4
all_values[1] 223 1 T1 7 T2 7 T63 4
all_values[2] 223 1 T1 7 T2 7 T63 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 364 1 T1 13 T2 11 T63 5
auto[1] 305 1 T1 8 T2 10 T63 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 243 1 T1 12 T2 5 T63 2
auto[1] 426 1 T1 9 T2 16 T63 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 379 1 T1 15 T2 11 T63 6
auto[1] 290 1 T1 6 T2 10 T63 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 43 1 T2 2 T57 2 T82 1
all_values[0] auto[0] auto[0] auto[1] 32 1 T1 2 T63 1 T85 2
all_values[0] auto[0] auto[1] auto[0] 39 1 T1 1 T63 1 T149 2
all_values[0] auto[0] auto[1] auto[1] 21 1 T1 1 T2 1 T63 1
all_values[0] auto[1] auto[0] auto[1] 47 1 T1 2 T2 2 T82 1
all_values[0] auto[1] auto[1] auto[1] 41 1 T1 1 T2 2 T63 1
all_values[1] auto[0] auto[0] auto[0] 41 1 T1 3 T63 1 T57 1
all_values[1] auto[0] auto[0] auto[1] 26 1 T2 2 T63 1 T131 1
all_values[1] auto[0] auto[1] auto[0] 34 1 T1 3 T57 1 T82 1
all_values[1] auto[0] auto[1] auto[1] 22 1 T2 2 T82 1 T85 2
all_values[1] auto[1] auto[0] auto[1] 53 1 T1 1 T2 2 T57 1
all_values[1] auto[1] auto[1] auto[1] 47 1 T2 1 T63 2 T57 1
all_values[2] auto[0] auto[0] auto[0] 51 1 T1 3 T57 1 T82 1
all_values[2] auto[0] auto[0] auto[1] 11 1 T2 1 T150 1 T151 1
all_values[2] auto[0] auto[1] auto[0] 35 1 T1 2 T2 3 T150 1
all_values[2] auto[0] auto[1] auto[1] 24 1 T63 1 T57 1 T85 2
all_values[2] auto[1] auto[0] auto[1] 60 1 T1 2 T2 2 T63 2
all_values[2] auto[1] auto[1] auto[1] 42 1 T2 1 T63 1 T82 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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