Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.46 96.58 92.46 100.00 88.64 94.67 98.84 97.02


Total test records in report: 1031
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T120 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2386254165 Jan 07 12:55:51 PM PST 24 Jan 07 12:57:45 PM PST 24 235579820 ps
T154 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.103706190 Jan 07 12:56:11 PM PST 24 Jan 07 12:57:43 PM PST 24 654651033 ps
T1004 /workspace/coverage/cover_reg_top/27.kmac_intr_test.3616094396 Jan 07 12:55:49 PM PST 24 Jan 07 12:57:13 PM PST 24 16574777 ps
T1005 /workspace/coverage/cover_reg_top/8.kmac_intr_test.1426423833 Jan 07 12:56:32 PM PST 24 Jan 07 12:58:24 PM PST 24 19944470 ps
T1006 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1050485827 Jan 07 12:55:59 PM PST 24 Jan 07 12:57:23 PM PST 24 126902631 ps
T1007 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2531701795 Jan 07 12:55:18 PM PST 24 Jan 07 12:57:04 PM PST 24 39906679 ps
T1008 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2738236749 Jan 07 12:56:15 PM PST 24 Jan 07 12:57:46 PM PST 24 38905892 ps
T1009 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.527157818 Jan 07 12:55:55 PM PST 24 Jan 07 12:57:29 PM PST 24 16918407 ps
T1010 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3810856851 Jan 07 12:56:26 PM PST 24 Jan 07 12:58:32 PM PST 24 36993265 ps
T1011 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2296640661 Jan 07 12:56:12 PM PST 24 Jan 07 12:58:02 PM PST 24 20286363 ps
T1012 /workspace/coverage/cover_reg_top/34.kmac_intr_test.185347032 Jan 07 12:55:48 PM PST 24 Jan 07 12:57:46 PM PST 24 18019869 ps
T1013 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1952406425 Jan 07 12:55:47 PM PST 24 Jan 07 12:57:10 PM PST 24 32379688 ps
T1014 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1822265615 Jan 07 12:56:00 PM PST 24 Jan 07 12:58:03 PM PST 24 26486738 ps
T159 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1288455068 Jan 07 12:56:09 PM PST 24 Jan 07 12:57:34 PM PST 24 126711298 ps
T1015 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3196476755 Jan 07 12:55:43 PM PST 24 Jan 07 12:57:17 PM PST 24 13855127 ps
T1016 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3693583367 Jan 07 12:55:39 PM PST 24 Jan 07 12:57:17 PM PST 24 241322426 ps
T1017 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1756103278 Jan 07 12:55:36 PM PST 24 Jan 07 12:57:07 PM PST 24 21192491 ps
T1018 /workspace/coverage/cover_reg_top/13.kmac_intr_test.76616886 Jan 07 12:56:04 PM PST 24 Jan 07 12:57:36 PM PST 24 13911203 ps
T1019 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1489384003 Jan 07 12:55:21 PM PST 24 Jan 07 12:56:52 PM PST 24 92179993 ps
T1020 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2024795958 Jan 07 12:56:25 PM PST 24 Jan 07 12:58:57 PM PST 24 172755738 ps
T1021 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3646248739 Jan 07 12:56:10 PM PST 24 Jan 07 12:58:06 PM PST 24 266359137 ps
T1022 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1712283897 Jan 07 12:55:51 PM PST 24 Jan 07 12:57:56 PM PST 24 194562493 ps
T1023 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2921073720 Jan 07 12:56:26 PM PST 24 Jan 07 12:57:54 PM PST 24 89289948 ps
T1024 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3968540278 Jan 07 12:56:18 PM PST 24 Jan 07 12:58:03 PM PST 24 89451202 ps
T1025 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4018823668 Jan 07 12:55:48 PM PST 24 Jan 07 12:57:39 PM PST 24 221335340 ps
T1026 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2715125120 Jan 07 12:55:51 PM PST 24 Jan 07 12:57:46 PM PST 24 121746970 ps
T1027 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3106797177 Jan 07 12:57:38 PM PST 24 Jan 07 12:59:09 PM PST 24 63178855 ps
T1028 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3338364714 Jan 07 12:55:14 PM PST 24 Jan 07 12:56:35 PM PST 24 27459555 ps
T1029 /workspace/coverage/cover_reg_top/39.kmac_intr_test.2739253906 Jan 07 12:55:54 PM PST 24 Jan 07 12:57:47 PM PST 24 17501577 ps
T1030 /workspace/coverage/cover_reg_top/1.kmac_intr_test.276770059 Jan 07 12:55:39 PM PST 24 Jan 07 12:57:13 PM PST 24 60485720 ps
T1031 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3874372155 Jan 07 12:55:47 PM PST 24 Jan 07 12:57:10 PM PST 24 52306215 ps

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3830732691
Short name T1
Test name
Test status
Simulation time 43604517 ps
CPU time 0.78 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 206936 kb
Host smart-69ee25d9-3422-40f3-b0af-b8fc7bbab647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830732691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3830732691 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.3092823103
Short name T16
Test name
Test status
Simulation time 41786032538 ps
CPU time 207.82 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:08:11 PM PST 24
Peak memory 236204 kb
Host smart-2991f63b-7b1a-42f4-b0ef-d593c6104840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092823103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3092823103 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.4042001581
Short name T84
Test name
Test status
Simulation time 129786899 ps
CPU time 2.89 seconds
Started Jan 07 12:56:15 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 207344 kb
Host smart-ffaee33d-e859-43ce-bf9c-83c40185ea5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042001581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.4042
001581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/40.kmac_stress_all_with_rand_reset.3319453126
Short name T36
Test name
Test status
Simulation time 24646452481 ps
CPU time 1060.24 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:23:36 PM PST 24
Peak memory 353356 kb
Host smart-96c5dc5e-fa11-4294-9577-c09a5a42a350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319453126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.3319453126 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_error.1259386282
Short name T5
Test name
Test status
Simulation time 1724576540 ps
CPU time 60.42 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:05:44 PM PST 24
Peak memory 240200 kb
Host smart-02f90014-a02a-4d4b-b0f4-8f1648355fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259386282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1259386282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.334937641
Short name T94
Test name
Test status
Simulation time 76779716 ps
CPU time 1.36 seconds
Started Jan 07 12:55:40 PM PST 24
Finished Jan 07 12:57:14 PM PST 24
Peak memory 215884 kb
Host smart-2a36a409-f6a3-440a-aa14-c08e5663e4fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334937641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.334937641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.2565252376
Short name T10
Test name
Test status
Simulation time 3182262602 ps
CPU time 32.42 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:05:07 PM PST 24
Peak memory 242396 kb
Host smart-39bdea49-4ff1-461a-8489-b481fc9434bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565252376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2565252376 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3488211529
Short name T7
Test name
Test status
Simulation time 114821425 ps
CPU time 1.16 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 215500 kb
Host smart-5f9b3ba9-4617-4a5f-8511-11bd8e59d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488211529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3488211529 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3278011305
Short name T47
Test name
Test status
Simulation time 151259183094 ps
CPU time 3892.95 seconds
Started Jan 07 01:03:59 PM PST 24
Finished Jan 07 02:08:56 PM PST 24
Peak memory 551956 kb
Host smart-af38c3bb-a84c-490c-91be-efef75825c24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3278011305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3278011305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4073745319
Short name T61
Test name
Test status
Simulation time 196721836 ps
CPU time 1.6 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 223724 kb
Host smart-522a9077-6267-4aba-8f36-2f2f5f73e8b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073745319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.4073745319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.kmac_error.1386128075
Short name T31
Test name
Test status
Simulation time 64170512385 ps
CPU time 312.2 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:11:04 PM PST 24
Peak memory 251008 kb
Host smart-931107b1-64d8-4789-a0dc-93301a15f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386128075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1386128075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.4014967005
Short name T22
Test name
Test status
Simulation time 1887655850 ps
CPU time 5.64 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 207272 kb
Host smart-5f87be2b-809d-4d7d-9b03-bdd5940100ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014967005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4014967005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2168893409
Short name T2
Test name
Test status
Simulation time 20697316 ps
CPU time 0.8 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 207108 kb
Host smart-299486f0-b6b7-4466-a0db-61f12947b430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168893409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2168893409 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4015801813
Short name T99
Test name
Test status
Simulation time 189211903 ps
CPU time 2.47 seconds
Started Jan 07 12:56:20 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 223284 kb
Host smart-8ccd178e-9597-400e-ae13-f3a0b3c67e0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015801813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.4015801813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3355766240
Short name T107
Test name
Test status
Simulation time 38115771 ps
CPU time 1.43 seconds
Started Jan 07 12:55:45 PM PST 24
Finished Jan 07 12:57:12 PM PST 24
Peak memory 215392 kb
Host smart-7b286dac-a9f5-41f5-88d9-5cfa7919cc5b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355766240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3355766240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2560154107
Short name T25
Test name
Test status
Simulation time 34801995834 ps
CPU time 1271.35 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:27:07 PM PST 24
Peak memory 410076 kb
Host smart-0bd3a9a9-149e-4cd0-a0fc-869723745829
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2560154107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2560154107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2918126659
Short name T153
Test name
Test status
Simulation time 148604920 ps
CPU time 4.07 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 207536 kb
Host smart-b03301c5-b9ed-4614-a131-adb79f1812df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918126659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.29181
26659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.874827356
Short name T135
Test name
Test status
Simulation time 124562458293 ps
CPU time 1330.62 seconds
Started Jan 07 01:05:05 PM PST 24
Finished Jan 07 01:27:17 PM PST 24
Peak memory 335176 kb
Host smart-f9d53353-a83e-4684-bc03-bdc79d402362
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=874827356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.874827356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3940130959
Short name T125
Test name
Test status
Simulation time 1040261874 ps
CPU time 20.13 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 207280 kb
Host smart-5ddfa20d-e5f0-4ff0-9e1d-c0a47261e130
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940130959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3940130
959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.603704785
Short name T157
Test name
Test status
Simulation time 1138580703 ps
CPU time 4.04 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 207264 kb
Host smart-fc652a1f-f667-48bd-ade4-2ef6cd9e3562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603704785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.60370
4785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1885644557
Short name T136
Test name
Test status
Simulation time 7392826794 ps
CPU time 60.99 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:05:17 PM PST 24
Peak memory 215756 kb
Host smart-f1cc561d-f049-471f-b7e2-a4af1d681bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885644557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1885644557 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1424557952
Short name T213
Test name
Test status
Simulation time 37316276 ps
CPU time 0.74 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 205132 kb
Host smart-65f269cd-99b4-4a7e-a0f5-19ee3c12aafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424557952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1424557952 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.2239747769
Short name T42
Test name
Test status
Simulation time 335462507228 ps
CPU time 1908.17 seconds
Started Jan 07 01:03:51 PM PST 24
Finished Jan 07 01:35:43 PM PST 24
Peak memory 388844 kb
Host smart-53ca9006-dfaf-44f6-9f91-344a806e82d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239747769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.2239747769 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3173435663
Short name T152
Test name
Test status
Simulation time 110127786 ps
CPU time 4.19 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:43 PM PST 24
Peak memory 215496 kb
Host smart-7f1068e1-dfc8-4c03-89b8-0d4e4b135fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173435663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3173
435663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1925491159
Short name T151
Test name
Test status
Simulation time 27652940 ps
CPU time 0.81 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 207084 kb
Host smart-5788d1de-db1c-482e-8dd2-fd5d7c36173d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925491159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1925491159 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.370590975
Short name T702
Test name
Test status
Simulation time 4462332817 ps
CPU time 39.31 seconds
Started Jan 07 01:03:51 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 217232 kb
Host smart-b8a9a965-3b8f-48b5-97e5-8c422054d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370590975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.370590975 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3380543745
Short name T38
Test name
Test status
Simulation time 36748290007 ps
CPU time 484.52 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:13:16 PM PST 24
Peak memory 295800 kb
Host smart-eca07814-09d7-41d8-9ec5-7249521e3f24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3380543745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3380543745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3225712347
Short name T83
Test name
Test status
Simulation time 63539077 ps
CPU time 0.93 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 12:56:55 PM PST 24
Peak memory 207148 kb
Host smart-c928b25c-f988-4ad1-94bf-c18d741ce9e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225712347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3225712
347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2531701795
Short name T1007
Test name
Test status
Simulation time 39906679 ps
CPU time 1.9 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:57:04 PM PST 24
Peak memory 223624 kb
Host smart-bcd779b9-6757-4123-b323-113e8cf2da75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531701795 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2531701795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3338364714
Short name T1028
Test name
Test status
Simulation time 27459555 ps
CPU time 1.08 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:56:35 PM PST 24
Peak memory 215404 kb
Host smart-a5a3bb74-055e-4207-9b42-82dea397d9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338364714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3338364714 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.3921529592
Short name T960
Test name
Test status
Simulation time 45116476 ps
CPU time 0.76 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 207012 kb
Host smart-e96a8852-aa62-49e2-85a7-a0cacdcb9d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921529592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3921529592 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2896601900
Short name T112
Test name
Test status
Simulation time 38137865 ps
CPU time 1.47 seconds
Started Jan 07 12:55:32 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 215296 kb
Host smart-522494aa-8919-480f-ae6c-cccdd9ae8914
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896601900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2896601900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1756103278
Short name T1017
Test name
Test status
Simulation time 21192491 ps
CPU time 0.69 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 12:57:07 PM PST 24
Peak memory 207060 kb
Host smart-2f60b13a-2a77-4eaa-b2a7-3ddb92257306
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756103278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1756103278
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.578740915
Short name T56
Test name
Test status
Simulation time 195325094 ps
CPU time 2.28 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 223032 kb
Host smart-76e32f66-bc3a-4a57-8f38-71cb6ff8a265
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578740915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_
shadow_reg_errors_with_csr_rw.578740915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3100057644
Short name T987
Test name
Test status
Simulation time 460341275 ps
CPU time 10.13 seconds
Started Jan 07 12:55:48 PM PST 24
Finished Jan 07 12:57:49 PM PST 24
Peak memory 207284 kb
Host smart-a208246a-62c2-4b5d-8aca-1c8dec9fdc2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100057644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3100057
644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1313534154
Short name T124
Test name
Test status
Simulation time 310735398 ps
CPU time 15.58 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 12:56:44 PM PST 24
Peak memory 207288 kb
Host smart-49c51b07-956f-411b-ab58-9c31621a108c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313534154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1313534
154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2751330660
Short name T938
Test name
Test status
Simulation time 23559204 ps
CPU time 1.05 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 12:56:34 PM PST 24
Peak memory 207176 kb
Host smart-8014264b-5884-48e4-9901-288a7b48abe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751330660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2751330
660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.276770059
Short name T1030
Test name
Test status
Simulation time 60485720 ps
CPU time 0.74 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 207056 kb
Host smart-b371b178-0673-46e1-9124-3b981a53a583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276770059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.276770059 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1245033668
Short name T168
Test name
Test status
Simulation time 37141822 ps
CPU time 0.7 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 206964 kb
Host smart-1995bc62-9dc9-4ab8-ae54-8ab752889bb7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245033668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1245033668
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3919440736
Short name T944
Test name
Test status
Simulation time 248220083 ps
CPU time 1.72 seconds
Started Jan 07 12:55:55 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 215516 kb
Host smart-0d43c11d-09d8-4642-8a4f-5a41420a8f55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919440736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3919440736 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2730087816
Short name T931
Test name
Test status
Simulation time 64248735 ps
CPU time 1.72 seconds
Started Jan 07 12:56:15 PM PST 24
Finished Jan 07 12:57:58 PM PST 24
Peak memory 223652 kb
Host smart-a1ee3029-3ee9-4f6f-af1c-b32b45a855c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730087816 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2730087816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.911825896
Short name T983
Test name
Test status
Simulation time 27030939 ps
CPU time 1.13 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:28 PM PST 24
Peak memory 207320 kb
Host smart-98e48fe1-b147-404f-987a-c9c35c6c7025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911825896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.911825896 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.1700965965
Short name T965
Test name
Test status
Simulation time 13561975 ps
CPU time 0.74 seconds
Started Jan 07 12:56:05 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 207096 kb
Host smart-0670c207-2a8c-4f92-a7f6-742ba996e85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700965965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1700965965 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3420589850
Short name T969
Test name
Test status
Simulation time 348342995 ps
CPU time 2.24 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:57:45 PM PST 24
Peak memory 215408 kb
Host smart-881ca1fa-0b2b-4107-8814-070cc13e954c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420589850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3420589850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4018823668
Short name T1025
Test name
Test status
Simulation time 221335340 ps
CPU time 0.97 seconds
Started Jan 07 12:55:48 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 215592 kb
Host smart-c813f106-8a9f-466d-a316-de1ca79ce2be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018823668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.4018823668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2668682831
Short name T978
Test name
Test status
Simulation time 292615924 ps
CPU time 2.07 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 215692 kb
Host smart-75a7b18a-212a-46c6-be60-bc41cad681c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668682831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2668682831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1932026949
Short name T115
Test name
Test status
Simulation time 511474140 ps
CPU time 3.21 seconds
Started Jan 07 12:55:31 PM PST 24
Finished Jan 07 12:56:51 PM PST 24
Peak memory 215484 kb
Host smart-29397a8e-5342-4e07-8b66-790db774a354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932026949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1932026949 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2546464709
Short name T161
Test name
Test status
Simulation time 298889181 ps
CPU time 5.09 seconds
Started Jan 07 12:55:45 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 215428 kb
Host smart-aff4f036-c037-4e3c-9790-bfc421e209d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546464709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2546
464709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1601384214
Short name T133
Test name
Test status
Simulation time 22328098 ps
CPU time 1.33 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 222852 kb
Host smart-a9817c68-5365-411e-8fae-0500355ab8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601384214 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1601384214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3038236626
Short name T930
Test name
Test status
Simulation time 22508163 ps
CPU time 0.9 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 207068 kb
Host smart-d8d69e6a-086a-4eaf-8e3e-926148b71a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038236626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3038236626 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.2240120064
Short name T82
Test name
Test status
Simulation time 42756644 ps
CPU time 0.71 seconds
Started Jan 07 12:55:44 PM PST 24
Finished Jan 07 12:57:31 PM PST 24
Peak memory 206996 kb
Host smart-06238ca8-e78d-450c-9a90-c52129dec3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240120064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2240120064 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2715125120
Short name T1026
Test name
Test status
Simulation time 121746970 ps
CPU time 2.67 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 215396 kb
Host smart-7692d98a-be9c-4a0d-9f57-7fe9eacd09f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715125120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2715125120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1822265615
Short name T1014
Test name
Test status
Simulation time 26486738 ps
CPU time 1 seconds
Started Jan 07 12:56:00 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 215512 kb
Host smart-668b2d1d-6197-46d4-8e4d-02ca3c8a1c4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822265615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.1822265615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4165268795
Short name T942
Test name
Test status
Simulation time 55287164 ps
CPU time 1.63 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 215808 kb
Host smart-04d982ab-5251-4f92-8786-cde31fcf06c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165268795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.4165268795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.103706190
Short name T154
Test name
Test status
Simulation time 654651033 ps
CPU time 2.24 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:43 PM PST 24
Peak memory 207200 kb
Host smart-097f0f24-bc2f-41c2-8d28-943cde7a6965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103706190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.10370
6190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2215126890
Short name T995
Test name
Test status
Simulation time 27126658 ps
CPU time 1.72 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 223592 kb
Host smart-db263fdc-7b8b-4056-b551-be3922ffb588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215126890 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2215126890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2809940927
Short name T1003
Test name
Test status
Simulation time 201565805 ps
CPU time 1.57 seconds
Started Jan 07 12:56:23 PM PST 24
Finished Jan 07 12:58:08 PM PST 24
Peak memory 207336 kb
Host smart-0699a847-eb71-48c4-b573-ba2649360298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809940927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.2809940927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3987919100
Short name T97
Test name
Test status
Simulation time 561738772 ps
CPU time 2.93 seconds
Started Jan 07 12:56:20 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 215952 kb
Host smart-c892dc2b-6bed-4e55-ab04-81326b99f8e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987919100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3987919100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.4051060342
Short name T113
Test name
Test status
Simulation time 109018825 ps
CPU time 3.26 seconds
Started Jan 07 12:56:19 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215544 kb
Host smart-c7771ce5-41f3-40ab-90c1-8b121d2d8aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051060342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.4051060342 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.734608763
Short name T119
Test name
Test status
Simulation time 533067196 ps
CPU time 2.86 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 218004 kb
Host smart-fd6779ef-565c-41ef-87ba-d0897349bcbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734608763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.73460
8763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.4086970284
Short name T55
Test name
Test status
Simulation time 22950126 ps
CPU time 1.45 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 215492 kb
Host smart-1590ab93-1b03-4403-a515-78b3004cc735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086970284 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.4086970284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3952913095
Short name T953
Test name
Test status
Simulation time 115555609 ps
CPU time 1.12 seconds
Started Jan 07 12:55:42 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 207164 kb
Host smart-b7fc0c3b-1b38-4138-85a4-91c116b98053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952913095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3952913095 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.76616886
Short name T1018
Test name
Test status
Simulation time 13911203 ps
CPU time 0.72 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 207016 kb
Host smart-cbff70e3-25cd-47da-9707-7c04e71a74e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76616886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.76616886 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2386254165
Short name T120
Test name
Test status
Simulation time 235579820 ps
CPU time 1.74 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:45 PM PST 24
Peak memory 215476 kb
Host smart-e1aaa685-15f9-4402-8e66-a1d79dce65ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386254165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2386254165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4133663138
Short name T989
Test name
Test status
Simulation time 39640794 ps
CPU time 1.7 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 215828 kb
Host smart-fd2cc8f2-8806-43a2-a96d-0af9df3ea8aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133663138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.4133663138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2506485125
Short name T959
Test name
Test status
Simulation time 243179502 ps
CPU time 1.63 seconds
Started Jan 07 12:56:14 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 215576 kb
Host smart-74073756-ab14-44fa-b7bc-7a2ee763a2af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506485125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2506485125 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1071469330
Short name T156
Test name
Test status
Simulation time 883058936 ps
CPU time 2.99 seconds
Started Jan 07 12:55:50 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 215424 kb
Host smart-53e08c13-866c-4068-acd4-b217d21d2a98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071469330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1071
469330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3076108445
Short name T996
Test name
Test status
Simulation time 20205354 ps
CPU time 1.18 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 215468 kb
Host smart-32e41a44-c4b4-4d26-b104-5ce3681d2d9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076108445 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3076108445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3570314573
Short name T952
Test name
Test status
Simulation time 54315105 ps
CPU time 1.08 seconds
Started Jan 07 12:55:42 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 207140 kb
Host smart-ad62868c-1748-4633-9c33-27d64a70ff34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570314573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3570314573 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3196476755
Short name T1015
Test name
Test status
Simulation time 13855127 ps
CPU time 0.74 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 207052 kb
Host smart-d73f6d4b-4cad-4143-b4f4-0cab80e8674e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196476755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3196476755 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1050485827
Short name T1006
Test name
Test status
Simulation time 126902631 ps
CPU time 0.97 seconds
Started Jan 07 12:55:59 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 215612 kb
Host smart-e5cb5bab-a01e-4e04-ac8a-4eff9d84f2af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050485827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1050485827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2202887241
Short name T988
Test name
Test status
Simulation time 80691582 ps
CPU time 1.31 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:37 PM PST 24
Peak memory 215524 kb
Host smart-66e124a8-51c9-49b6-8bec-00df67b50f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202887241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2202887241 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.27219410
Short name T963
Test name
Test status
Simulation time 17970771 ps
CPU time 1.46 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:16 PM PST 24
Peak memory 215496 kb
Host smart-39e69399-31a2-497b-997d-d1e622793f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219410 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.27219410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1952406425
Short name T1013
Test name
Test status
Simulation time 32379688 ps
CPU time 1.1 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 215364 kb
Host smart-e8a4470d-b8b6-42e0-9ac4-6b483e30eaf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952406425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1952406425 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.4099896931
Short name T962
Test name
Test status
Simulation time 14553996 ps
CPU time 0.73 seconds
Started Jan 07 12:55:48 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 207080 kb
Host smart-595ad818-1c1b-49c4-afc3-8f192142ac0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099896931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4099896931 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1271874714
Short name T956
Test name
Test status
Simulation time 98237998 ps
CPU time 1.58 seconds
Started Jan 07 12:56:02 PM PST 24
Finished Jan 07 12:57:58 PM PST 24
Peak memory 215536 kb
Host smart-696a315b-363a-4f37-b39d-03610d74cc45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271874714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1271874714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2880469693
Short name T968
Test name
Test status
Simulation time 45863194 ps
CPU time 1.29 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 215756 kb
Host smart-f7cb5011-8632-46f7-9df3-0b4173e74c2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880469693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2880469693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3536206168
Short name T955
Test name
Test status
Simulation time 148920456 ps
CPU time 3.73 seconds
Started Jan 07 12:56:22 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215604 kb
Host smart-aee32add-e813-4ebe-a86d-772cc6498221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536206168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3536206168 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.120298646
Short name T155
Test name
Test status
Simulation time 401920663 ps
CPU time 2.83 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:35 PM PST 24
Peak memory 215408 kb
Host smart-0eed7b52-4931-4c11-ba5a-976f83a212ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120298646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.12029
8646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.527157818
Short name T1009
Test name
Test status
Simulation time 16918407 ps
CPU time 1.29 seconds
Started Jan 07 12:55:55 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 215420 kb
Host smart-2116b68e-d589-452c-af43-0935ab6def39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527157818 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.527157818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.186264508
Short name T87
Test name
Test status
Simulation time 56297979 ps
CPU time 1.03 seconds
Started Jan 07 12:55:55 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 215428 kb
Host smart-4a989849-a7b9-44ad-a96e-e84918d6b192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186264508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.186264508 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2241852800
Short name T149
Test name
Test status
Simulation time 33727299 ps
CPU time 0.72 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 207012 kb
Host smart-8527d35b-15d1-4d76-8523-87293771e779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241852800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2241852800 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3458488846
Short name T932
Test name
Test status
Simulation time 84489342 ps
CPU time 1.44 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 215428 kb
Host smart-15ab1ac6-476f-4453-aae1-07a1a91893ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458488846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3458488846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1712283897
Short name T1022
Test name
Test status
Simulation time 194562493 ps
CPU time 1.25 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 215804 kb
Host smart-80461fe7-4c42-4536-956a-f89d50767a1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712283897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.1712283897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.30514468
Short name T975
Test name
Test status
Simulation time 48200988 ps
CPU time 2.38 seconds
Started Jan 07 12:56:01 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 215812 kb
Host smart-b5bb0682-dcc7-4695-8151-a98df7542099
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30514468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_
shadow_reg_errors_with_csr_rw.30514468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3414525937
Short name T958
Test name
Test status
Simulation time 39950974 ps
CPU time 1.32 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 215584 kb
Host smart-987695b7-9641-4c15-b07f-15eae516fa36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414525937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3414525937 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4230135870
Short name T972
Test name
Test status
Simulation time 210781927 ps
CPU time 4.94 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 215376 kb
Host smart-b494f2a8-90d0-4560-855b-70a996b2360d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230135870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4230
135870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2440345849
Short name T967
Test name
Test status
Simulation time 126786196 ps
CPU time 1.62 seconds
Started Jan 07 12:56:37 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 223560 kb
Host smart-f65504a1-0878-4c0c-97d5-441a8930e524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440345849 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2440345849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.24150721
Short name T981
Test name
Test status
Simulation time 13033967 ps
CPU time 0.89 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 206996 kb
Host smart-ec40a0b4-4d7e-4752-88f5-ab21494c0e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.24150721 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3707632149
Short name T1000
Test name
Test status
Simulation time 21182392 ps
CPU time 0.72 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 207008 kb
Host smart-383af9ca-47e9-4e77-9c56-ece60ad9d23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707632149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3707632149 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1669178710
Short name T935
Test name
Test status
Simulation time 110010570 ps
CPU time 1.68 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 207296 kb
Host smart-a4f49d59-896f-4c7e-8787-960958107fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669178710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1669178710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2024795958
Short name T1020
Test name
Test status
Simulation time 172755738 ps
CPU time 2.52 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:57 PM PST 24
Peak memory 223896 kb
Host smart-8bb5a8d8-6883-44e3-9151-c812097e6c86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024795958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2024795958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2328896469
Short name T991
Test name
Test status
Simulation time 173335317 ps
CPU time 2.6 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:16 PM PST 24
Peak memory 215528 kb
Host smart-9c2c6909-e52f-4bfc-96e5-07ca7eb55ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328896469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2328896469 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3780044847
Short name T158
Test name
Test status
Simulation time 241445411 ps
CPU time 5.24 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215288 kb
Host smart-3043164f-7cdd-440c-9edd-87346a9307f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780044847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3780
044847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2704299889
Short name T130
Test name
Test status
Simulation time 36537369 ps
CPU time 1.68 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:38 PM PST 24
Peak memory 223664 kb
Host smart-8eaff88a-354a-473e-99b9-9b341cce4db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704299889 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2704299889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3562931450
Short name T970
Test name
Test status
Simulation time 47319355 ps
CPU time 1.06 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 207276 kb
Host smart-a3f723ed-201d-43c8-9869-f39cf77b40da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562931450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3562931450 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.3229300811
Short name T954
Test name
Test status
Simulation time 21582986 ps
CPU time 0.76 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 207024 kb
Host smart-edb0a0e8-38b9-478f-a88b-d392b3cf48a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229300811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3229300811 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.510718087
Short name T964
Test name
Test status
Simulation time 76270974 ps
CPU time 2.15 seconds
Started Jan 07 12:56:21 PM PST 24
Finished Jan 07 12:58:08 PM PST 24
Peak memory 215560 kb
Host smart-41255c4d-ad0c-4460-aae2-586ea4a946c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510718087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.510718087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3106797177
Short name T1027
Test name
Test status
Simulation time 63178855 ps
CPU time 1.07 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:09 PM PST 24
Peak memory 215476 kb
Host smart-e944a316-c9b3-4474-9278-9500d5276202
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106797177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.3106797177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3807524078
Short name T93
Test name
Test status
Simulation time 347853210 ps
CPU time 2.73 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:50 PM PST 24
Peak memory 223852 kb
Host smart-907ff0ca-8d23-4569-8dd8-0a31ec309123
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807524078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3807524078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2282612588
Short name T110
Test name
Test status
Simulation time 340314633 ps
CPU time 3.23 seconds
Started Jan 07 12:55:57 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 215464 kb
Host smart-5d2a4334-6264-4da5-9b5b-b0f60f6f3061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282612588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2282612588 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.443170435
Short name T990
Test name
Test status
Simulation time 45928320 ps
CPU time 1.33 seconds
Started Jan 07 12:56:14 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 215412 kb
Host smart-7268a81e-3831-49c4-982d-794209319901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443170435 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.443170435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2296640661
Short name T1011
Test name
Test status
Simulation time 20286363 ps
CPU time 0.95 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 215228 kb
Host smart-38258d37-49c0-4f03-a721-c2e446c29ab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296640661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2296640661 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.838253227
Short name T169
Test name
Test status
Simulation time 91913433 ps
CPU time 0.74 seconds
Started Jan 07 12:56:06 PM PST 24
Finished Jan 07 12:57:45 PM PST 24
Peak memory 207004 kb
Host smart-2f0cdb7f-01c5-4171-9b91-7b0c8bb6503f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838253227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.838253227 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1808569952
Short name T974
Test name
Test status
Simulation time 126815041 ps
CPU time 1.69 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 215424 kb
Host smart-a90b2d90-1cd9-4465-a520-53510eaff2fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808569952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1808569952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3758572785
Short name T96
Test name
Test status
Simulation time 28027993 ps
CPU time 0.92 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 207160 kb
Host smart-a825f164-179e-4b8e-86bd-b60bd94032d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758572785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3758572785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.158282965
Short name T993
Test name
Test status
Simulation time 87280751 ps
CPU time 1.63 seconds
Started Jan 07 12:56:33 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 215796 kb
Host smart-bf9d1a79-59b2-4205-9fe7-52a6697ed756
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158282965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.158282965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3054285298
Short name T929
Test name
Test status
Simulation time 299120472 ps
CPU time 2.32 seconds
Started Jan 07 12:56:14 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215500 kb
Host smart-65d84615-ad9e-4753-9fe2-c6d69cb82af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054285298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3054285298 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.109122248
Short name T982
Test name
Test status
Simulation time 162433488 ps
CPU time 8.74 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:30 PM PST 24
Peak memory 207284 kb
Host smart-5a338b0a-4132-4e09-b9d4-3156ea2db327
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109122248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.10912224
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3433015085
Short name T945
Test name
Test status
Simulation time 54911161 ps
CPU time 1.08 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 215464 kb
Host smart-9ecf92cc-f980-47ec-ba71-0daed1c1d206
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433015085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3433015
085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.415257885
Short name T948
Test name
Test status
Simulation time 117271370 ps
CPU time 1.11 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 207204 kb
Host smart-ccc0b9d7-0e47-48ea-9fbb-9837a0a3c80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415257885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.415257885 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.425782893
Short name T966
Test name
Test status
Simulation time 14088413 ps
CPU time 0.75 seconds
Started Jan 07 12:55:28 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 206280 kb
Host smart-c04f6eca-e733-4808-8580-b19de4a6e880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425782893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.425782893 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1489384003
Short name T1019
Test name
Test status
Simulation time 92179993 ps
CPU time 2.47 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:56:52 PM PST 24
Peak memory 215400 kb
Host smart-d7696f67-c693-44c4-8e15-05cd4e3cdba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489384003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1489384003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1663216237
Short name T947
Test name
Test status
Simulation time 46921080 ps
CPU time 2.43 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 215956 kb
Host smart-303afdb6-97ab-4071-b93d-8b3cfbdf3ff0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663216237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.1663216237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2529627913
Short name T58
Test name
Test status
Simulation time 90102284 ps
CPU time 2.52 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:57:28 PM PST 24
Peak memory 215544 kb
Host smart-f801f70c-69a0-4ebc-8329-dfcdd4fdfa7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529627913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2529627913 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1697067225
Short name T994
Test name
Test status
Simulation time 124700120 ps
CPU time 2.33 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 12:57:30 PM PST 24
Peak memory 207224 kb
Host smart-1bac962d-a752-48db-ae19-3c876ed116b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697067225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.16970
67225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2304485383
Short name T949
Test name
Test status
Simulation time 13592361 ps
CPU time 0.77 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 206988 kb
Host smart-0d21c5a6-b364-41e4-9e80-09edbd40b399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304485383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2304485383 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.825010511
Short name T971
Test name
Test status
Simulation time 101615532 ps
CPU time 0.77 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 207040 kb
Host smart-7bcae538-d2f9-49eb-b0da-9cd596cc6c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825010511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.825010511 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.50131059
Short name T132
Test name
Test status
Simulation time 32719975 ps
CPU time 0.78 seconds
Started Jan 07 12:56:02 PM PST 24
Finished Jan 07 12:57:37 PM PST 24
Peak memory 206912 kb
Host smart-73936df7-a527-461d-9ad6-43ae9594bbbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50131059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.50131059 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.204717973
Short name T979
Test name
Test status
Simulation time 66846812 ps
CPU time 0.72 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 207076 kb
Host smart-ac1603ea-2e44-4fab-a43c-b76568e6c816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204717973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.204717973 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.3616094396
Short name T1004
Test name
Test status
Simulation time 16574777 ps
CPU time 0.74 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 207056 kb
Host smart-ec3bfeba-215d-4a13-893e-325cf1e3cff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616094396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3616094396 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2390671105
Short name T940
Test name
Test status
Simulation time 23806474 ps
CPU time 0.71 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 206968 kb
Host smart-50208a49-5b1d-4876-96f8-736040c48628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390671105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2390671105 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.225771644
Short name T946
Test name
Test status
Simulation time 45981226 ps
CPU time 0.74 seconds
Started Jan 07 12:55:59 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 207056 kb
Host smart-39dab14d-3f71-4df8-bd17-04cf60030520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225771644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.225771644 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.744198609
Short name T957
Test name
Test status
Simulation time 1677259874 ps
CPU time 10.31 seconds
Started Jan 07 12:55:32 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 215336 kb
Host smart-5453b0b6-b54c-44ce-a975-5eb2a8fdf90e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744198609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.74419860
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2249785586
Short name T997
Test name
Test status
Simulation time 3284668637 ps
CPU time 22.68 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 207464 kb
Host smart-d8296c89-e7cf-47b9-b6a4-5c042664723c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249785586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2249785
586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2418846860
Short name T985
Test name
Test status
Simulation time 67856644 ps
CPU time 1.13 seconds
Started Jan 07 12:55:50 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 207224 kb
Host smart-fb9a275a-2167-4fa5-b6d2-b9985c4a4e41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418846860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2418846
860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.365575752
Short name T109
Test name
Test status
Simulation time 256239505 ps
CPU time 2.01 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 223416 kb
Host smart-0bb4c1a6-208a-4dd6-a606-4c6fdba8aa93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365575752 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.365575752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3824976797
Short name T134
Test name
Test status
Simulation time 75413309 ps
CPU time 0.94 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 207140 kb
Host smart-b08b8f10-2187-494a-bf1a-50c4f533ebd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824976797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3824976797 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3451348653
Short name T980
Test name
Test status
Simulation time 17950410 ps
CPU time 0.78 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:20 PM PST 24
Peak memory 207108 kb
Host smart-cf22218c-cfc7-4dc6-b13a-5fc21abf5d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451348653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3451348653 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2849972300
Short name T117
Test name
Test status
Simulation time 302701312 ps
CPU time 1.24 seconds
Started Jan 07 12:55:31 PM PST 24
Finished Jan 07 12:56:54 PM PST 24
Peak memory 215384 kb
Host smart-51fdc673-b135-4df8-ad85-9ca4db83f2fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849972300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2849972300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3573265244
Short name T3
Test name
Test status
Simulation time 95600625 ps
CPU time 2.38 seconds
Started Jan 07 12:55:28 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 223056 kb
Host smart-b4c0a5af-a548-433e-a7f9-3b7290560e71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573265244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3573265244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3258280578
Short name T160
Test name
Test status
Simulation time 601575563 ps
CPU time 3.03 seconds
Started Jan 07 12:55:34 PM PST 24
Finished Jan 07 12:56:53 PM PST 24
Peak memory 207212 kb
Host smart-6b48532a-6b4a-4ae5-b722-6bd8ee62bb7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258280578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.32582
80578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.587059491
Short name T936
Test name
Test status
Simulation time 26668761 ps
CPU time 0.76 seconds
Started Jan 07 12:55:59 PM PST 24
Finished Jan 07 12:57:22 PM PST 24
Peak memory 207044 kb
Host smart-e9e87a52-0c6d-445f-a5a5-0e7cf5ffd285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587059491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.587059491 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3796400071
Short name T951
Test name
Test status
Simulation time 10719914 ps
CPU time 0.73 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 207020 kb
Host smart-5bde9de0-12d5-4c3e-bb42-40234f09aa12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796400071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3796400071 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.517548634
Short name T943
Test name
Test status
Simulation time 30246854 ps
CPU time 0.76 seconds
Started Jan 07 12:56:27 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 206968 kb
Host smart-89407cd9-45c0-43ce-8b46-fd3ee8cb0291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517548634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.517548634 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.185347032
Short name T1012
Test name
Test status
Simulation time 18019869 ps
CPU time 0.75 seconds
Started Jan 07 12:55:48 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 207068 kb
Host smart-b1c2d520-7700-48bf-be10-6593446c18f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185347032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.185347032 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1134899679
Short name T934
Test name
Test status
Simulation time 19659115 ps
CPU time 0.76 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 207016 kb
Host smart-67f26b9a-51cf-4f37-a2b0-ce293001f6ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134899679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1134899679 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3810856851
Short name T1010
Test name
Test status
Simulation time 36993265 ps
CPU time 0.77 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 207064 kb
Host smart-c6980f58-03aa-4c8c-9606-bdc4c51028a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810856851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3810856851 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1645224758
Short name T999
Test name
Test status
Simulation time 21444848 ps
CPU time 0.78 seconds
Started Jan 07 12:56:24 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 206932 kb
Host smart-f73ebda2-953b-4698-9b13-a8ad4efa9c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645224758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1645224758 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1261922142
Short name T150
Test name
Test status
Simulation time 57589711 ps
CPU time 0.74 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 207020 kb
Host smart-d812f611-f1d8-48ea-acb2-8a177e64b52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261922142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1261922142 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.2739253906
Short name T1029
Test name
Test status
Simulation time 17501577 ps
CPU time 0.75 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 206952 kb
Host smart-b91a51fc-0b71-47f1-8beb-119c3d81d8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739253906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2739253906 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3350947672
Short name T998
Test name
Test status
Simulation time 294492697 ps
CPU time 5.93 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 207212 kb
Host smart-84c3e501-4191-42e3-92b9-22251f66ddd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350947672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3350947
672 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3867374230
Short name T86
Test name
Test status
Simulation time 461035834 ps
CPU time 16.1 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 207352 kb
Host smart-e8e66ec3-10cc-42d8-b283-4cc72320aa87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867374230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3867374
230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2205317182
Short name T961
Test name
Test status
Simulation time 268431443 ps
CPU time 0.92 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 207032 kb
Host smart-a19eefab-67d1-480b-8484-96f582276f68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205317182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2205317
182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3582407440
Short name T933
Test name
Test status
Simulation time 78449114 ps
CPU time 1.19 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 215368 kb
Host smart-c352af32-b899-42b6-9216-8d00964b8ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582407440 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3582407440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.846133597
Short name T116
Test name
Test status
Simulation time 18018135 ps
CPU time 0.75 seconds
Started Jan 07 12:55:29 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 207096 kb
Host smart-87970290-5adb-4206-ad90-7285b07bc236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846133597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.846133597 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3331668554
Short name T118
Test name
Test status
Simulation time 14954183 ps
CPU time 1.07 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 215344 kb
Host smart-1424e652-bc24-46cb-b445-83d832fa1d4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331668554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3331668554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2767052930
Short name T937
Test name
Test status
Simulation time 12783509 ps
CPU time 0.71 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 206872 kb
Host smart-603c1ce8-4556-4ffa-af19-532ad68c5d06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767052930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2767052930
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3646248739
Short name T1021
Test name
Test status
Simulation time 266359137 ps
CPU time 1.61 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 207172 kb
Host smart-d86b1afc-e857-47bf-a2ed-586916d438e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646248739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3646248739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.333382933
Short name T95
Test name
Test status
Simulation time 1303434989 ps
CPU time 3.69 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:06 PM PST 24
Peak memory 223888 kb
Host smart-07b2a182-b530-4253-a6b9-830ef99024c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333382933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_
shadow_reg_errors_with_csr_rw.333382933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3413214927
Short name T81
Test name
Test status
Simulation time 76705788 ps
CPU time 1.49 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 215532 kb
Host smart-0ea79973-cc97-4614-bdf2-53135a62f5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413214927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3413214927 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2954043497
Short name T941
Test name
Test status
Simulation time 27297709 ps
CPU time 0.72 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 207096 kb
Host smart-647284ca-cede-4449-81a1-918c6d00fb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954043497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2954043497 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.4014374851
Short name T939
Test name
Test status
Simulation time 14100666 ps
CPU time 0.77 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 207012 kb
Host smart-ae63e5c0-bd68-4ace-8fb6-f438a5c88d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014374851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4014374851 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3947275022
Short name T131
Test name
Test status
Simulation time 23390496 ps
CPU time 0.76 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 206988 kb
Host smart-7cda8cd5-857f-4f22-9327-2a17d672d8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947275022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3947275022 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2551250545
Short name T1002
Test name
Test status
Simulation time 102985376 ps
CPU time 0.69 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 207008 kb
Host smart-df98b640-0081-455b-a982-3ce8257b3880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551250545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2551250545 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.442278176
Short name T85
Test name
Test status
Simulation time 17691545 ps
CPU time 0.77 seconds
Started Jan 07 12:56:37 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 206976 kb
Host smart-8022231e-27ba-44f1-92df-c53662b189fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442278176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.442278176 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.9473305
Short name T57
Test name
Test status
Simulation time 42721623 ps
CPU time 0.77 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 207028 kb
Host smart-5c8971ff-1fbe-4db6-b15c-e24f34e39291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9473305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.9473305 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.4272555522
Short name T1001
Test name
Test status
Simulation time 43059602 ps
CPU time 0.74 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:42 PM PST 24
Peak memory 207096 kb
Host smart-9433891f-f17c-4c9f-887d-a9b03b530d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272555522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.4272555522 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1119742245
Short name T973
Test name
Test status
Simulation time 49919556 ps
CPU time 2.17 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 223636 kb
Host smart-ecbb07c2-d9d5-4bad-b86d-2d8e3b8a4b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119742245 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1119742245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3058715225
Short name T108
Test name
Test status
Simulation time 172944673 ps
CPU time 2.46 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 215428 kb
Host smart-e2fe3e98-37d7-41bd-821d-aa4f39f89b20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058715225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3058715225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2690299224
Short name T101
Test name
Test status
Simulation time 215560716 ps
CPU time 1.68 seconds
Started Jan 07 12:56:03 PM PST 24
Finished Jan 07 12:58:21 PM PST 24
Peak memory 215852 kb
Host smart-f42f2f77-bc30-4195-9157-405338f517c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690299224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2690299224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.4025866252
Short name T114
Test name
Test status
Simulation time 101388978 ps
CPU time 1.53 seconds
Started Jan 07 12:55:59 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 215476 kb
Host smart-51ac24f4-791f-4a0d-b4ab-a6a508a41677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025866252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4025866252 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3693583367
Short name T1016
Test name
Test status
Simulation time 241322426 ps
CPU time 3 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 215472 kb
Host smart-be222358-2629-4baa-a7ae-771407688861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693583367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.36935
83367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1769383045
Short name T977
Test name
Test status
Simulation time 91463110 ps
CPU time 1.32 seconds
Started Jan 07 12:56:02 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 215556 kb
Host smart-eaf80c8f-f52f-49af-a2c3-9a8f2ecdb42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769383045 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1769383045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3968540278
Short name T1024
Test name
Test status
Simulation time 89451202 ps
CPU time 0.98 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 207088 kb
Host smart-517a0e19-89fe-4fb5-b023-8564b48b7fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968540278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3968540278 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.4228818842
Short name T111
Test name
Test status
Simulation time 75165235 ps
CPU time 0.78 seconds
Started Jan 07 12:56:03 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 207040 kb
Host smart-f237bf32-3d52-42b1-9907-0a98b26e8974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228818842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.4228818842 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3874372155
Short name T1031
Test name
Test status
Simulation time 52306215 ps
CPU time 1.05 seconds
Started Jan 07 12:55:47 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 215788 kb
Host smart-c4900ed3-e335-46d7-83de-d97135dd11b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874372155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3874372155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1650483179
Short name T59
Test name
Test status
Simulation time 98214549 ps
CPU time 2.3 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:20 PM PST 24
Peak memory 215436 kb
Host smart-1bdc4010-2ffc-43ef-bba0-240e6a32e738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650483179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.16504
83179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2738236749
Short name T1008
Test name
Test status
Simulation time 38905892 ps
CPU time 1.11 seconds
Started Jan 07 12:56:15 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 207224 kb
Host smart-ecc4cfb8-2e9c-4c53-9ae7-487d7dd2f460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738236749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2738236749 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1226076621
Short name T63
Test name
Test status
Simulation time 21534612 ps
CPU time 0.75 seconds
Started Jan 07 12:56:22 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 207016 kb
Host smart-61e2c0f0-1b32-4c46-a999-acfbf449bfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226076621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1226076621 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3867379176
Short name T992
Test name
Test status
Simulation time 91220904 ps
CPU time 2.31 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:28 PM PST 24
Peak memory 215424 kb
Host smart-58e529b3-96e2-4164-9654-b7f4bedc7f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867379176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3867379176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2748972861
Short name T984
Test name
Test status
Simulation time 38455627 ps
CPU time 0.97 seconds
Started Jan 07 12:56:17 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215576 kb
Host smart-773f4298-09f5-44f2-a18e-b8caca55a62c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748972861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2748972861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1481978238
Short name T98
Test name
Test status
Simulation time 130928860 ps
CPU time 1.79 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 215800 kb
Host smart-c40c826b-b6c9-4c64-9c97-abc58a5e27e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481978238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1481978238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.471834289
Short name T105
Test name
Test status
Simulation time 61223078 ps
CPU time 2.53 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 207252 kb
Host smart-1e5b9215-a2ff-4d26-855b-358f4275c389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471834289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.471834
289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3882215896
Short name T79
Test name
Test status
Simulation time 17851349 ps
CPU time 1.22 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 215432 kb
Host smart-d02d49e5-02f3-43bf-8020-70f341bbea97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882215896 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3882215896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3585919727
Short name T976
Test name
Test status
Simulation time 16219579 ps
CPU time 1.02 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 207284 kb
Host smart-d659feca-0c51-4ebe-9f2a-3dd4dd7a4492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585919727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3585919727 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.1426423833
Short name T1005
Test name
Test status
Simulation time 19944470 ps
CPU time 0.79 seconds
Started Jan 07 12:56:32 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 207076 kb
Host smart-c74a5f14-6c21-4cc4-83f7-90414a96bb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426423833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1426423833 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2339296122
Short name T60
Test name
Test status
Simulation time 133985123 ps
CPU time 1.14 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 215800 kb
Host smart-23ebf899-cd7d-44d8-a0cd-c38fcb022ac5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339296122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2339296122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2921073720
Short name T1023
Test name
Test status
Simulation time 89289948 ps
CPU time 1.56 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 215544 kb
Host smart-3ccab80c-e4c5-4232-81b8-1b7f3dcdad30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921073720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2921073720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3912904823
Short name T80
Test name
Test status
Simulation time 104817887 ps
CPU time 1.6 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 215484 kb
Host smart-d8d8ba01-2cf9-4bf3-aa39-13e1beeec755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912904823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3912904823 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2792168868
Short name T106
Test name
Test status
Simulation time 998045605 ps
CPU time 5.4 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 215368 kb
Host smart-a6f65df4-fbe6-4468-961a-9cc99760a4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792168868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.27921
68868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.435049813
Short name T950
Test name
Test status
Simulation time 29711458 ps
CPU time 1.3 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:58 PM PST 24
Peak memory 215516 kb
Host smart-e881f985-d4f6-4fec-a001-1e7f7e93ae32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435049813 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.435049813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2222243314
Short name T986
Test name
Test status
Simulation time 530737242 ps
CPU time 1.76 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 215432 kb
Host smart-0721b71e-512e-4314-85e6-b780d30b164e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222243314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2222243314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3753848182
Short name T100
Test name
Test status
Simulation time 245384140 ps
CPU time 1.11 seconds
Started Jan 07 12:56:20 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 215696 kb
Host smart-4f979199-4bda-4312-aad0-797ceed91359
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753848182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.3753848182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1978526377
Short name T78
Test name
Test status
Simulation time 26505821 ps
CPU time 1.56 seconds
Started Jan 07 12:55:34 PM PST 24
Finished Jan 07 12:57:06 PM PST 24
Peak memory 215476 kb
Host smart-dc913015-b882-4e69-9b46-4e878ef77eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978526377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1978526377 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1288455068
Short name T159
Test name
Test status
Simulation time 126711298 ps
CPU time 2.95 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 215448 kb
Host smart-1b9d1ce7-e293-4666-8322-a629240152e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288455068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.12884
55068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.473181799
Short name T632
Test name
Test status
Simulation time 31857828 ps
CPU time 0.77 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 205180 kb
Host smart-707db7e4-9b7d-4b6f-8b5f-fcf1491b8646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473181799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.473181799 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.2812580308
Short name T493
Test name
Test status
Simulation time 7920401507 ps
CPU time 53.12 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:05:02 PM PST 24
Peak memory 224924 kb
Host smart-73bebae7-750b-4dcb-859a-13fe68fd22d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812580308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2812580308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_burst_write.3518753828
Short name T809
Test name
Test status
Simulation time 17592141410 ps
CPU time 520.63 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:13:12 PM PST 24
Peak memory 231288 kb
Host smart-3ff33bfa-f4be-4f02-ae94-2bf19a2d3e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518753828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3518753828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.396821839
Short name T288
Test name
Test status
Simulation time 528532550 ps
CPU time 4.2 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 223700 kb
Host smart-698dae4c-dd4d-4401-a3e1-c5299ba039d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396821839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.396821839 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.902007913
Short name T652
Test name
Test status
Simulation time 3235187474 ps
CPU time 12.07 seconds
Started Jan 07 01:04:12 PM PST 24
Finished Jan 07 01:04:26 PM PST 24
Peak memory 223800 kb
Host smart-a3028038-e7ae-4acd-93af-0af3ae8f7b89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=902007913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.902007913 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2272193958
Short name T780
Test name
Test status
Simulation time 28395910145 ps
CPU time 178.51 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:06:53 PM PST 24
Peak memory 238064 kb
Host smart-3439ca80-fe5b-4201-a5f3-3780f82184e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272193958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2272193958 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3907704306
Short name T89
Test name
Test status
Simulation time 574208398 ps
CPU time 20.76 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:17 PM PST 24
Peak memory 235160 kb
Host smart-254aecfc-65d4-4349-9d13-35437d16a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907704306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3907704306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3052807194
Short name T66
Test name
Test status
Simulation time 785426613 ps
CPU time 2.74 seconds
Started Jan 07 01:04:05 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 207340 kb
Host smart-dda1c6af-9bad-4620-a5c7-0fce2ae054f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052807194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3052807194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.985545838
Short name T62
Test name
Test status
Simulation time 121624676 ps
CPU time 1.23 seconds
Started Jan 07 01:03:51 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 215700 kb
Host smart-031f1313-623a-4ad4-be5b-5bab266fa0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985545838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.985545838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.2411366194
Short name T590
Test name
Test status
Simulation time 98790930100 ps
CPU time 1992.9 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:37:34 PM PST 24
Peak memory 445652 kb
Host smart-14a4fbe5-4cbe-4faf-be71-02fb141231a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411366194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.2411366194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.2440291412
Short name T826
Test name
Test status
Simulation time 18849125569 ps
CPU time 31.19 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:04:48 PM PST 24
Peak memory 224248 kb
Host smart-ec103018-006f-4bf2-babc-d385ff2a7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440291412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2440291412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.4200959054
Short name T773
Test name
Test status
Simulation time 12251961549 ps
CPU time 241.01 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:08:29 PM PST 24
Peak memory 238148 kb
Host smart-ce796b9f-6da0-458e-825f-9e59c289542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200959054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.4200959054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_stress_all.1387338552
Short name T583
Test name
Test status
Simulation time 58427400135 ps
CPU time 1054.74 seconds
Started Jan 07 01:04:10 PM PST 24
Finished Jan 07 01:21:47 PM PST 24
Peak memory 373300 kb
Host smart-ee9ce4ae-4acd-4764-96ea-802af40a6a56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1387338552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1387338552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2879657893
Short name T367
Test name
Test status
Simulation time 307715920 ps
CPU time 3.76 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 208908 kb
Host smart-6833d850-2605-4d9d-8390-d11a3942e5b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879657893 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2879657893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1518632214
Short name T18
Test name
Test status
Simulation time 173539102 ps
CPU time 4.6 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 215672 kb
Host smart-202f7933-ad27-41bd-8ef3-4897d7a81d7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518632214 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1518632214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.603368131
Short name T204
Test name
Test status
Simulation time 100147078088 ps
CPU time 1821.74 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:34:21 PM PST 24
Peak memory 391948 kb
Host smart-23202415-f998-45ac-9869-a8d8adc3a234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=603368131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.603368131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.847019602
Short name T181
Test name
Test status
Simulation time 17986923255 ps
CPU time 1366.24 seconds
Started Jan 07 01:03:45 PM PST 24
Finished Jan 07 01:26:38 PM PST 24
Peak memory 367928 kb
Host smart-f98e7197-4e42-4b84-b953-6fa0456ba7b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=847019602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.847019602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2489090963
Short name T192
Test name
Test status
Simulation time 48468635478 ps
CPU time 1298.42 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:25:33 PM PST 24
Peak memory 332352 kb
Host smart-edc88eab-1649-4c3e-a625-b810bbcc5f94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2489090963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2489090963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1438949283
Short name T689
Test name
Test status
Simulation time 171637552854 ps
CPU time 4312.71 seconds
Started Jan 07 01:03:43 PM PST 24
Finished Jan 07 02:15:44 PM PST 24
Peak memory 649848 kb
Host smart-64384aae-b924-41be-9373-042c8e8ff98a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1438949283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1438949283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3954073343
Short name T618
Test name
Test status
Simulation time 86640868885 ps
CPU time 3328.75 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:59:21 PM PST 24
Peak memory 547056 kb
Host smart-fe6b9893-2114-473a-acfa-c3fc809f2817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3954073343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3954073343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2986486992
Short name T914
Test name
Test status
Simulation time 18283665 ps
CPU time 0.78 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 205204 kb
Host smart-912eab65-68ca-4eb6-8816-04c79cd207b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986486992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2986486992 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.931020658
Short name T290
Test name
Test status
Simulation time 22272398101 ps
CPU time 91.05 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 227284 kb
Host smart-a7fc27b7-433e-4c63-b08c-a586b23cc5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931020658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.931020658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3778496007
Short name T645
Test name
Test status
Simulation time 10599811795 ps
CPU time 422.53 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:11:13 PM PST 24
Peak memory 229312 kb
Host smart-44520cad-65cc-48f5-8496-407e54d9b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778496007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3778496007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.541588035
Short name T746
Test name
Test status
Simulation time 340477254 ps
CPU time 2.8 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 218728 kb
Host smart-089e5856-a1cb-45e1-92a3-216a1128ee1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=541588035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.541588035 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2501030097
Short name T223
Test name
Test status
Simulation time 5732888161 ps
CPU time 38.63 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:05:13 PM PST 24
Peak memory 223728 kb
Host smart-b907da87-0e84-4257-a9d4-be0e34136c12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2501030097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2501030097 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3624724540
Short name T448
Test name
Test status
Simulation time 16316707998 ps
CPU time 36.98 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:04:48 PM PST 24
Peak memory 223804 kb
Host smart-8dfed7e8-34c7-4e0f-958c-30ea99864a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624724540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3624724540 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.2517437545
Short name T594
Test name
Test status
Simulation time 2529266029 ps
CPU time 2.38 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 207376 kb
Host smart-ffe43de5-fe91-4b7a-b8a6-bc0376304e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517437545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2517437545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1125562250
Short name T519
Test name
Test status
Simulation time 422719509 ps
CPU time 9.91 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 223972 kb
Host smart-f0f0ca9c-4dd7-47cc-9578-fb57a7aa73a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125562250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1125562250 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.2144959473
Short name T216
Test name
Test status
Simulation time 18398696275 ps
CPU time 523.15 seconds
Started Jan 07 01:04:03 PM PST 24
Finished Jan 07 01:12:51 PM PST 24
Peak memory 269380 kb
Host smart-70ce31b3-64b6-40f0-a234-fc009bbed379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144959473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.2144959473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.513507074
Short name T26
Test name
Test status
Simulation time 514311154 ps
CPU time 2.5 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 217232 kb
Host smart-a684e412-bcbc-4664-ad98-cb3201e20d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513507074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.513507074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.921629680
Short name T470
Test name
Test status
Simulation time 31208022564 ps
CPU time 319.99 seconds
Started Jan 07 01:04:07 PM PST 24
Finished Jan 07 01:09:29 PM PST 24
Peak memory 247320 kb
Host smart-da5ec962-06c6-459e-9780-549f83b9ab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921629680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.921629680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3764958774
Short name T472
Test name
Test status
Simulation time 13716453163 ps
CPU time 35.3 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 221124 kb
Host smart-f9377a35-0b4a-45ef-931c-394a3376e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764958774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3764958774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1775494956
Short name T860
Test name
Test status
Simulation time 14793222229 ps
CPU time 222.67 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:08:13 PM PST 24
Peak memory 270808 kb
Host smart-6c1cba14-0e9d-4c27-8b1b-db6d139ed349
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1775494956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1775494956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.133818482
Short name T203
Test name
Test status
Simulation time 181044328 ps
CPU time 4.3 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:26 PM PST 24
Peak memory 215632 kb
Host smart-3fbac149-7e67-48e1-9cc1-bfbaceccf9ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133818482 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.133818482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.85905291
Short name T698
Test name
Test status
Simulation time 1063313390 ps
CPU time 5.01 seconds
Started Jan 07 01:04:39 PM PST 24
Finished Jan 07 01:04:47 PM PST 24
Peak memory 215712 kb
Host smart-7278568b-21fb-44e2-ad1f-e2ef5320c714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85905291 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.kmac_test_vectors_kmac_xof.85905291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2354634721
Short name T751
Test name
Test status
Simulation time 131388890077 ps
CPU time 1783.66 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:33:43 PM PST 24
Peak memory 374156 kb
Host smart-e487c13e-ab1b-468c-80ba-b435b9138190
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2354634721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2354634721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.3717956353
Short name T504
Test name
Test status
Simulation time 242341674023 ps
CPU time 1627.69 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:31:17 PM PST 24
Peak memory 370628 kb
Host smart-11875b0f-26d8-42ee-9413-58cbb5d5a9b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3717956353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3717956353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.504091862
Short name T321
Test name
Test status
Simulation time 73978431716 ps
CPU time 1375.58 seconds
Started Jan 07 01:04:02 PM PST 24
Finished Jan 07 01:27:03 PM PST 24
Peak memory 338000 kb
Host smart-1603d971-6bac-4d72-a275-52b9bda3882c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=504091862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.504091862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3938874319
Short name T541
Test name
Test status
Simulation time 136416018365 ps
CPU time 871.24 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:18:42 PM PST 24
Peak memory 295652 kb
Host smart-8e5c316f-b563-4cf7-9ec8-6c9411cdbd5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3938874319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3938874319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.2873862972
Short name T317
Test name
Test status
Simulation time 390109147409 ps
CPU time 4646.08 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 02:21:40 PM PST 24
Peak memory 648216 kb
Host smart-ea67a072-d93f-4604-a52f-360757b8c4f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2873862972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2873862972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2585343488
Short name T787
Test name
Test status
Simulation time 146991998912 ps
CPU time 3841.37 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 02:08:05 PM PST 24
Peak memory 562164 kb
Host smart-0b676a0c-e025-4076-9032-bd93d696911b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2585343488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2585343488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.1470965077
Short name T603
Test name
Test status
Simulation time 14256954472 ps
CPU time 200.05 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:07:57 PM PST 24
Peak memory 239844 kb
Host smart-9fa1646c-86f4-4b78-bae9-c095857956d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470965077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1470965077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3695795965
Short name T341
Test name
Test status
Simulation time 40253380075 ps
CPU time 355.89 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:10:52 PM PST 24
Peak memory 228196 kb
Host smart-d93b6efd-81a8-46c0-a09b-99de974b221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695795965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3695795965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2564655058
Short name T659
Test name
Test status
Simulation time 913610240 ps
CPU time 19.34 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 216604 kb
Host smart-45bcedfe-2227-496c-8842-c3163fabf84b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564655058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2564655058 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2610768951
Short name T499
Test name
Test status
Simulation time 361352787 ps
CPU time 25.6 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:05:03 PM PST 24
Peak memory 219792 kb
Host smart-ec6372d9-980b-45fb-9d67-27bd9ce89962
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610768951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2610768951 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_error.1774730561
Short name T810
Test name
Test status
Simulation time 12511710972 ps
CPU time 229.2 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:08:08 PM PST 24
Peak memory 245312 kb
Host smart-3aeacb96-1108-4d62-a93a-9e60da1f3951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774730561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1774730561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.689260129
Short name T259
Test name
Test status
Simulation time 945037887 ps
CPU time 5.41 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:40 PM PST 24
Peak memory 207232 kb
Host smart-5a9022fc-9cba-4fe0-a7f1-71efe7c832cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689260129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.689260129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3208429058
Short name T527
Test name
Test status
Simulation time 36354315 ps
CPU time 1.08 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 215504 kb
Host smart-a84ae906-f5af-4fe1-8599-4a8c8c4c8786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208429058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3208429058 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.4076977594
Short name T354
Test name
Test status
Simulation time 39190720697 ps
CPU time 839.45 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:18:37 PM PST 24
Peak memory 313016 kb
Host smart-96fb42c3-67d3-4caf-90d0-c54aebaecb2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076977594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.4076977594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_smoke.2306702217
Short name T735
Test name
Test status
Simulation time 2790867619 ps
CPU time 55.38 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:05:51 PM PST 24
Peak memory 217664 kb
Host smart-adb2b98d-265e-417d-894d-c4422d736113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306702217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2306702217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.3753475496
Short name T915
Test name
Test status
Simulation time 122217184248 ps
CPU time 2493.89 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:46:12 PM PST 24
Peak memory 476100 kb
Host smart-31d14c88-3d65-40d8-9a7b-ba1964bdb74d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3753475496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3753475496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_stress_all_with_rand_reset.4225265536
Short name T443
Test name
Test status
Simulation time 107811966585 ps
CPU time 2114.99 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:39:35 PM PST 24
Peak memory 366460 kb
Host smart-cf22555c-38f7-4c5c-b232-075787facd1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225265536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.4225265536 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.1601089017
Short name T878
Test name
Test status
Simulation time 178303911 ps
CPU time 4.4 seconds
Started Jan 07 01:04:51 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 215664 kb
Host smart-7664fa57-b831-4e67-a3f5-75518b7153d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601089017 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.1601089017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2262740132
Short name T219
Test name
Test status
Simulation time 1923595502 ps
CPU time 5.3 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:04:25 PM PST 24
Peak memory 215676 kb
Host smart-4568884b-c9a5-4e47-b7f5-58595b6d882a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262740132 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2262740132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.1850191054
Short name T471
Test name
Test status
Simulation time 98839571090 ps
CPU time 1537.03 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:30:31 PM PST 24
Peak memory 390688 kb
Host smart-49d773fa-7bdf-415e-b867-594d3f3d0e62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1850191054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.1850191054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2134930195
Short name T660
Test name
Test status
Simulation time 41293558851 ps
CPU time 1507.64 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:29:45 PM PST 24
Peak memory 388696 kb
Host smart-9e8fe7c0-9edd-48cd-9d4a-ff6d14cdf603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2134930195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2134930195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.3765224751
Short name T634
Test name
Test status
Simulation time 55713162137 ps
CPU time 1003.85 seconds
Started Jan 07 01:04:46 PM PST 24
Finished Jan 07 01:21:32 PM PST 24
Peak memory 329980 kb
Host smart-802709c1-83d0-4996-bf32-482819d7a217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3765224751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.3765224751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.3799500177
Short name T725
Test name
Test status
Simulation time 144150592782 ps
CPU time 3752.72 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 02:07:11 PM PST 24
Peak memory 553604 kb
Host smart-d1094544-be8b-4c27-84db-8d19c963c24c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3799500177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.3799500177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_app.136766657
Short name T552
Test name
Test status
Simulation time 13954785505 ps
CPU time 131.79 seconds
Started Jan 07 01:04:39 PM PST 24
Finished Jan 07 01:06:54 PM PST 24
Peak memory 234964 kb
Host smart-53f9bc03-ce4e-4992-876a-9e5e946b1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136766657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.136766657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2808592446
Short name T636
Test name
Test status
Simulation time 65312558005 ps
CPU time 727.18 seconds
Started Jan 07 01:04:36 PM PST 24
Finished Jan 07 01:16:47 PM PST 24
Peak memory 231640 kb
Host smart-30cf1569-7255-4adc-830b-0223127850f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808592446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2808592446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.2205079220
Short name T44
Test name
Test status
Simulation time 231159677 ps
CPU time 15.41 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 223976 kb
Host smart-cf554d0c-7187-4411-a52f-6618d9580bc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2205079220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2205079220 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.3992726844
Short name T673
Test name
Test status
Simulation time 681499910 ps
CPU time 13.61 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:04:59 PM PST 24
Peak memory 223624 kb
Host smart-7652258c-0344-4ad8-a220-acfdd1a36bdb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3992726844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3992726844 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.316525173
Short name T365
Test name
Test status
Simulation time 4070607845 ps
CPU time 158.58 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:07:20 PM PST 24
Peak memory 236500 kb
Host smart-0a8a8492-5f56-42dc-b54b-2ec4bdb0bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316525173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.316525173 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1771532155
Short name T91
Test name
Test status
Simulation time 14377580412 ps
CPU time 56.76 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:05:24 PM PST 24
Peak memory 237948 kb
Host smart-da1c6397-ede5-4a62-b3d4-ab1230ecd31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771532155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1771532155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1777801195
Short name T535
Test name
Test status
Simulation time 42753198 ps
CPU time 1.21 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:04:33 PM PST 24
Peak memory 215536 kb
Host smart-135085b6-5a72-4525-a1af-11dfe8663831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777801195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1777801195 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1822553148
Short name T835
Test name
Test status
Simulation time 147200140240 ps
CPU time 1557.25 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:30:18 PM PST 24
Peak memory 356764 kb
Host smart-3c1b74ca-ff32-4b9a-b4f0-f29835cc7d6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822553148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1822553148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1737839206
Short name T72
Test name
Test status
Simulation time 2913122533 ps
CPU time 107.81 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:06:29 PM PST 24
Peak memory 228920 kb
Host smart-a526fd12-d7e7-4902-96d0-f54161976899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737839206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1737839206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.3128658185
Short name T595
Test name
Test status
Simulation time 259733509 ps
CPU time 6.24 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:46 PM PST 24
Peak memory 218708 kb
Host smart-209f48db-ca4c-4d28-a241-6b80c87c944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128658185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3128658185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2366322132
Short name T686
Test name
Test status
Simulation time 32263231568 ps
CPU time 1245.47 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:25:12 PM PST 24
Peak memory 362172 kb
Host smart-dc734c77-9b66-4158-8971-44ee9fbbf766
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2366322132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2366322132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2621524193
Short name T268
Test name
Test status
Simulation time 128701540 ps
CPU time 4 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:04:43 PM PST 24
Peak memory 215712 kb
Host smart-19a04495-02d9-456b-a293-1b93a96a148c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621524193 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2621524193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1654154563
Short name T302
Test name
Test status
Simulation time 208529219 ps
CPU time 4.57 seconds
Started Jan 07 01:04:48 PM PST 24
Finished Jan 07 01:04:55 PM PST 24
Peak memory 215596 kb
Host smart-078b9d39-3ec2-4d1b-b96d-99b163308428
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654154563 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1654154563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.486719540
Short name T682
Test name
Test status
Simulation time 261152306098 ps
CPU time 1761.76 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:33:58 PM PST 24
Peak memory 390388 kb
Host smart-ba7d4a4e-7100-4fc2-b156-31a6ab36cf09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=486719540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.486719540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.2136403324
Short name T613
Test name
Test status
Simulation time 33847962611 ps
CPU time 963.68 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:20:25 PM PST 24
Peak memory 295476 kb
Host smart-72f03b34-c7df-4c28-894a-7fa7f7b32af6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2136403324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2136403324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.4182515838
Short name T483
Test name
Test status
Simulation time 189878920715 ps
CPU time 3929.17 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 02:10:15 PM PST 24
Peak memory 568196 kb
Host smart-35ba8f00-39bf-45c1-a3b8-86bfa2a2dd6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4182515838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.4182515838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1195901497
Short name T882
Test name
Test status
Simulation time 53192957 ps
CPU time 0.8 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:01 PM PST 24
Peak memory 205084 kb
Host smart-093c0085-a929-4e81-9be2-3a69bcda5eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195901497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1195901497 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3140531242
Short name T141
Test name
Test status
Simulation time 2329407826 ps
CPU time 49.65 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:05:45 PM PST 24
Peak memory 223876 kb
Host smart-3ad84e6f-6b85-4375-884d-dfacc6315378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140531242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3140531242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1953717229
Short name T359
Test name
Test status
Simulation time 2450640704 ps
CPU time 37.85 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:05:35 PM PST 24
Peak memory 218928 kb
Host smart-c1c94bc8-625b-41f5-8b43-a0a05537f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953717229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1953717229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.972224539
Short name T468
Test name
Test status
Simulation time 786190979 ps
CPU time 21.37 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 223744 kb
Host smart-144a4c12-8b06-4943-a8b4-79c55f192ad1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972224539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.972224539 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2713062576
Short name T814
Test name
Test status
Simulation time 2030989182 ps
CPU time 6.46 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 223652 kb
Host smart-44bb160a-58d5-40b8-a199-580fccc7f7ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2713062576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2713062576 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3108990782
Short name T52
Test name
Test status
Simulation time 34614106574 ps
CPU time 177.84 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:07:35 PM PST 24
Peak memory 235808 kb
Host smart-ffae2e66-5ec9-40fe-bcb1-20c1aa6afb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108990782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3108990782 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.116419290
Short name T48
Test name
Test status
Simulation time 947168537 ps
CPU time 4.09 seconds
Started Jan 07 01:04:39 PM PST 24
Finished Jan 07 01:04:46 PM PST 24
Peak memory 207140 kb
Host smart-4ff3b7b5-79bd-420e-913f-a8075dd1b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116419290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.116419290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.2214862771
Short name T730
Test name
Test status
Simulation time 255824820 ps
CPU time 1.17 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:04:37 PM PST 24
Peak memory 215616 kb
Host smart-e71f3fb6-40e9-426b-83b4-1020a739f9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214862771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2214862771 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3269803730
Short name T533
Test name
Test status
Simulation time 91657242124 ps
CPU time 1929.44 seconds
Started Jan 07 01:04:46 PM PST 24
Finished Jan 07 01:36:57 PM PST 24
Peak memory 436440 kb
Host smart-6409b94c-daed-43bd-8464-b677de9a3446
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269803730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3269803730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1818890390
Short name T559
Test name
Test status
Simulation time 2736369626 ps
CPU time 37.01 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:05:15 PM PST 24
Peak memory 223920 kb
Host smart-d3fc6430-7401-4adb-a334-b7ce86ac4fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818890390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1818890390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2245135178
Short name T14
Test name
Test status
Simulation time 412164553 ps
CPU time 20.62 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:04:32 PM PST 24
Peak memory 218972 kb
Host smart-178bdbdc-e363-4265-81c9-65f1ffc6b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245135178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2245135178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.2575114930
Short name T461
Test name
Test status
Simulation time 48749262035 ps
CPU time 1030.24 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:22:04 PM PST 24
Peak memory 339036 kb
Host smart-9ac743e2-d32e-4216-b796-54be5281d52e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2575114930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2575114930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.523163184
Short name T907
Test name
Test status
Simulation time 440634709 ps
CPU time 4.01 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 208524 kb
Host smart-1f7ec6d8-fa4e-4684-9e01-52562a5943fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523163184 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.523163184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.3184607012
Short name T501
Test name
Test status
Simulation time 44467922738 ps
CPU time 1517.11 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:29:49 PM PST 24
Peak memory 389000 kb
Host smart-d08066d2-18d3-41cc-a385-8a165bad6e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3184607012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.3184607012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1974657443
Short name T599
Test name
Test status
Simulation time 17631059206 ps
CPU time 1460.06 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:28:43 PM PST 24
Peak memory 370760 kb
Host smart-4d8a6806-d39c-47fd-8c1e-b0923efd9d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1974657443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1974657443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.3103402455
Short name T241
Test name
Test status
Simulation time 250970447589 ps
CPU time 1363.06 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:27:27 PM PST 24
Peak memory 331504 kb
Host smart-7cc8a7f5-05fd-4870-b034-a88c06877e15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3103402455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3103402455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.203680609
Short name T460
Test name
Test status
Simulation time 212510595933 ps
CPU time 3916.55 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 02:09:48 PM PST 24
Peak memory 652256 kb
Host smart-1b405ba6-1104-43b8-977d-5ec8f945773d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=203680609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.203680609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1158002733
Short name T921
Test name
Test status
Simulation time 188713328677 ps
CPU time 3971.37 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 02:10:41 PM PST 24
Peak memory 563264 kb
Host smart-fe99cd11-a0b2-46de-a1b2-87aadf922ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1158002733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1158002733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.1603418495
Short name T521
Test name
Test status
Simulation time 46452792 ps
CPU time 0.71 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:04:37 PM PST 24
Peak memory 205156 kb
Host smart-59e7b39b-8823-4b6d-9ffa-0a55291614ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603418495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1603418495 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.1792392198
Short name T748
Test name
Test status
Simulation time 671124274 ps
CPU time 17.7 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:48 PM PST 24
Peak memory 223820 kb
Host smart-7664d617-746e-484f-80b0-f183bf059957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792392198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1792392198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.4041766657
Short name T859
Test name
Test status
Simulation time 2016019043 ps
CPU time 45.1 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:05:20 PM PST 24
Peak memory 222232 kb
Host smart-e1d85592-655b-499f-8c18-fcd8fac09a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041766657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.4041766657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2877818475
Short name T918
Test name
Test status
Simulation time 581215726 ps
CPU time 3.62 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 215492 kb
Host smart-e981f326-795b-4446-95f0-4736ece6ff81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2877818475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2877818475 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.1216917034
Short name T743
Test name
Test status
Simulation time 5451136673 ps
CPU time 36.26 seconds
Started Jan 07 01:04:47 PM PST 24
Finished Jan 07 01:05:25 PM PST 24
Peak memory 223900 kb
Host smart-14d27313-5ddb-4dac-addc-270b12fd895c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1216917034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1216917034 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.3301808069
Short name T624
Test name
Test status
Simulation time 66531807998 ps
CPU time 288.94 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 01:09:10 PM PST 24
Peak memory 245104 kb
Host smart-cfadc614-16cc-4ddd-9650-6761f95dbbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301808069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3301808069 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.795819901
Short name T585
Test name
Test status
Simulation time 13771222048 ps
CPU time 338.85 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:10:13 PM PST 24
Peak memory 256720 kb
Host smart-d3c22195-a910-4a35-bc59-37885ae7fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795819901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.795819901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.2775857544
Short name T578
Test name
Test status
Simulation time 1019461190 ps
CPU time 3.02 seconds
Started Jan 07 01:04:49 PM PST 24
Finished Jan 07 01:04:53 PM PST 24
Peak memory 207304 kb
Host smart-cf5437d8-766a-41c3-b8cf-de2176b724c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775857544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2775857544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3647046816
Short name T280
Test name
Test status
Simulation time 59052233 ps
CPU time 1.12 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 217180 kb
Host smart-107c9aaf-713f-4505-8d7a-9cee67ccd218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647046816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3647046816 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3908130558
Short name T671
Test name
Test status
Simulation time 2248328914 ps
CPU time 135.23 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:06:38 PM PST 24
Peak memory 229844 kb
Host smart-773824c8-1946-4757-aa6d-98e1191f6c9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908130558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3908130558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3819838675
Short name T488
Test name
Test status
Simulation time 3315102457 ps
CPU time 253.83 seconds
Started Jan 07 01:04:21 PM PST 24
Finished Jan 07 01:08:38 PM PST 24
Peak memory 242596 kb
Host smart-37e10276-7c9b-4d7e-bae4-0fa38ade2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819838675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3819838675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.942727608
Short name T76
Test name
Test status
Simulation time 1588679404 ps
CPU time 5.31 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 216852 kb
Host smart-cea5b06a-4ef0-4d30-8e7e-d3352dadcbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942727608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.942727608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.106264362
Short name T207
Test name
Test status
Simulation time 4649050145 ps
CPU time 67.23 seconds
Started Jan 07 01:04:52 PM PST 24
Finished Jan 07 01:06:00 PM PST 24
Peak memory 226124 kb
Host smart-db4587ca-049d-4b45-a177-e257e30e85d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=106264362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.106264362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.2528039305
Short name T391
Test name
Test status
Simulation time 158080995518 ps
CPU time 695.7 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 281792 kb
Host smart-d985a64b-316e-4e78-b6cf-eb01ee7d521a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528039305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.2528039305 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1327863588
Short name T712
Test name
Test status
Simulation time 248786260 ps
CPU time 3.83 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:26 PM PST 24
Peak memory 208504 kb
Host smart-37a47266-ac55-4db2-8840-c52d7c6bc5c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327863588 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1327863588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2957771082
Short name T690
Test name
Test status
Simulation time 702211079 ps
CPU time 5 seconds
Started Jan 07 01:04:47 PM PST 24
Finished Jan 07 01:04:53 PM PST 24
Peak memory 215600 kb
Host smart-97ec39be-ddb3-49db-86d0-a0d732498390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957771082 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2957771082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1172562590
Short name T640
Test name
Test status
Simulation time 293384505774 ps
CPU time 1932.21 seconds
Started Jan 07 01:04:46 PM PST 24
Finished Jan 07 01:37:00 PM PST 24
Peak memory 371748 kb
Host smart-b5913b7b-6c88-4780-9949-0e1e8209674a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1172562590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1172562590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.729732746
Short name T766
Test name
Test status
Simulation time 98423717102 ps
CPU time 1452.72 seconds
Started Jan 07 01:04:50 PM PST 24
Finished Jan 07 01:29:04 PM PST 24
Peak memory 348140 kb
Host smart-d320508a-b26d-49d0-a647-0d13990c696a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=729732746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.729732746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.2893360962
Short name T276
Test name
Test status
Simulation time 32825878297 ps
CPU time 848.74 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:18:39 PM PST 24
Peak memory 290144 kb
Host smart-db3de2e2-ef74-4562-8fdd-958a874ade0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2893360962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2893360962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3505121399
Short name T285
Test name
Test status
Simulation time 151556029025 ps
CPU time 3981.74 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 02:11:05 PM PST 24
Peak memory 562552 kb
Host smart-e8462626-74de-4063-b999-daa6f6fea745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3505121399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3505121399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.3918373575
Short name T305
Test name
Test status
Simulation time 19516660 ps
CPU time 0.87 seconds
Started Jan 07 01:04:42 PM PST 24
Finished Jan 07 01:04:45 PM PST 24
Peak memory 205100 kb
Host smart-fcd6f8ef-ff9e-4912-ba56-cf586c75953f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918373575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3918373575 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3846170063
Short name T522
Test name
Test status
Simulation time 8999724353 ps
CPU time 158.91 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:08:40 PM PST 24
Peak memory 235232 kb
Host smart-b896a8fe-f665-47b6-9de2-c684958c79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846170063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3846170063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.1880676590
Short name T328
Test name
Test status
Simulation time 46057327995 ps
CPU time 345.06 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:10:24 PM PST 24
Peak memory 228848 kb
Host smart-ff9a36d9-fd5d-4129-baa0-35fe8893eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880676590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1880676590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.944837699
Short name T430
Test name
Test status
Simulation time 396464713 ps
CPU time 13.09 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 222168 kb
Host smart-fedd3714-aa74-4d98-91aa-45a340a27d40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=944837699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.944837699 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_error.1693541692
Short name T768
Test name
Test status
Simulation time 13822098305 ps
CPU time 360.1 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:10:41 PM PST 24
Peak memory 252492 kb
Host smart-f72adb17-7b98-43be-b2c6-3514cc3c3fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693541692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1693541692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1884176310
Short name T792
Test name
Test status
Simulation time 1534712201 ps
CPU time 4.03 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:05:01 PM PST 24
Peak memory 207216 kb
Host smart-ab7b26be-64f4-4c89-86e2-9783f6b5bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884176310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1884176310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1242663851
Short name T9
Test name
Test status
Simulation time 48901737 ps
CPU time 1.11 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 215608 kb
Host smart-5083317a-9e88-40ab-b371-85c449070647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242663851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1242663851 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3937324797
Short name T666
Test name
Test status
Simulation time 122393897424 ps
CPU time 2030.44 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:38:34 PM PST 24
Peak memory 468260 kb
Host smart-dd95450a-40a1-40fc-a3bb-90bbdc513e37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937324797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3937324797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.912399965
Short name T723
Test name
Test status
Simulation time 1320971261 ps
CPU time 90.38 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:06:25 PM PST 24
Peak memory 228428 kb
Host smart-648a9096-d0da-40ec-ab0f-8162d30aa050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912399965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.912399965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.924914389
Short name T738
Test name
Test status
Simulation time 24808378117 ps
CPU time 42.07 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:05:09 PM PST 24
Peak memory 220388 kb
Host smart-df70bad1-0f5e-4e3c-8e36-6586b7f44966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924914389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.924914389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.2183062172
Short name T630
Test name
Test status
Simulation time 18185756464 ps
CPU time 272.77 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:09:06 PM PST 24
Peak memory 273364 kb
Host smart-9fd326a9-833f-45f8-b52a-4b27e28b77e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2183062172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2183062172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_stress_all_with_rand_reset.1264383016
Short name T830
Test name
Test status
Simulation time 55798787660 ps
CPU time 1103 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:22:57 PM PST 24
Peak memory 314252 kb
Host smart-08a97f76-6871-4999-a9ef-c8dd98661774
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264383016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.1264383016 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.3428843143
Short name T318
Test name
Test status
Simulation time 218068584 ps
CPU time 3.83 seconds
Started Jan 07 01:04:37 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 215620 kb
Host smart-4840563d-ce07-4ea3-9e87-e7837c0cc76e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428843143 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.3428843143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.4211823603
Short name T379
Test name
Test status
Simulation time 97690937714 ps
CPU time 1895.38 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:36:30 PM PST 24
Peak memory 379152 kb
Host smart-1eab110c-ed34-4d43-aaa0-49c4ebd0b2bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4211823603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.4211823603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3015230282
Short name T351
Test name
Test status
Simulation time 116657464857 ps
CPU time 1426.55 seconds
Started Jan 07 01:04:48 PM PST 24
Finished Jan 07 01:28:37 PM PST 24
Peak memory 343096 kb
Host smart-43c46e09-3b75-494f-9393-a19c68671771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3015230282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3015230282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2419595926
Short name T369
Test name
Test status
Simulation time 182255437799 ps
CPU time 892 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:19:35 PM PST 24
Peak memory 292896 kb
Host smart-301146dc-c142-47d8-add3-ec3709d6543a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2419595926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2419595926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.3337644185
Short name T734
Test name
Test status
Simulation time 1431495070482 ps
CPU time 4570.36 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 02:20:38 PM PST 24
Peak memory 649108 kb
Host smart-0f47cd8d-e78e-41c9-bbc0-30113419cf72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3337644185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3337644185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.874035872
Short name T240
Test name
Test status
Simulation time 142315255495 ps
CPU time 3659.52 seconds
Started Jan 07 01:04:51 PM PST 24
Finished Jan 07 02:05:52 PM PST 24
Peak memory 543424 kb
Host smart-7decfc3d-94ce-4f8c-afda-7247b5ba23e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=874035872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.874035872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.714081260
Short name T357
Test name
Test status
Simulation time 17371447 ps
CPU time 0.79 seconds
Started Jan 07 01:04:42 PM PST 24
Finished Jan 07 01:04:45 PM PST 24
Peak memory 205116 kb
Host smart-4a251ac0-b9a2-490f-be93-a3bc90ce88bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714081260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.714081260 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3504958937
Short name T917
Test name
Test status
Simulation time 14897167967 ps
CPU time 160.6 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:07:13 PM PST 24
Peak memory 237384 kb
Host smart-52dea7c0-7c26-416a-b120-2a4adf3468db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504958937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3504958937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1116278338
Short name T51
Test name
Test status
Simulation time 80054851248 ps
CPU time 470.06 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:12:17 PM PST 24
Peak memory 227976 kb
Host smart-68ba9ec1-a252-45dd-92b6-471f4f04b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116278338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1116278338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2757680126
Short name T404
Test name
Test status
Simulation time 205618059 ps
CPU time 13.97 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:04:51 PM PST 24
Peak memory 223692 kb
Host smart-39348c9f-e30b-43ce-a111-fbebf615084e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757680126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2757680126 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2635994828
Short name T477
Test name
Test status
Simulation time 816699659 ps
CPU time 13.97 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 01:04:43 PM PST 24
Peak memory 222932 kb
Host smart-4c68ea9d-52ae-43cd-98ae-12837a95bcbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2635994828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2635994828 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.216437119
Short name T701
Test name
Test status
Simulation time 6870843838 ps
CPU time 153.69 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 234536 kb
Host smart-c9c15ac3-ed82-474e-a847-ce47e31f40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216437119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.216437119 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.1071714856
Short name T147
Test name
Test status
Simulation time 4049334628 ps
CPU time 287.46 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:09:20 PM PST 24
Peak memory 256760 kb
Host smart-36b74d86-55b1-40e3-a9ce-b1ea2e19c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071714856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1071714856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.97585297
Short name T906
Test name
Test status
Simulation time 5877751945 ps
CPU time 22.34 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 227816 kb
Host smart-711f997d-8b52-45dc-b58d-536072fb3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97585297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.97585297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_sideload.3166387398
Short name T785
Test name
Test status
Simulation time 42559760149 ps
CPU time 288.69 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:09:24 PM PST 24
Peak memory 243888 kb
Host smart-cc8526c6-499a-4cb5-88df-2f92797c970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166387398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3166387398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2606804413
Short name T879
Test name
Test status
Simulation time 33542207702 ps
CPU time 54.04 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:05:28 PM PST 24
Peak memory 216836 kb
Host smart-98bdc2fa-c6a3-4d49-81bc-a963a215acd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606804413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2606804413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all_with_rand_reset.753392753
Short name T75
Test name
Test status
Simulation time 63575338203 ps
CPU time 924.15 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:20:05 PM PST 24
Peak memory 281692 kb
Host smart-0312b132-2f19-452a-99e1-11ce44936ffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753392753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.753392753 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.384761876
Short name T737
Test name
Test status
Simulation time 82880231 ps
CPU time 3.86 seconds
Started Jan 07 01:04:49 PM PST 24
Finished Jan 07 01:04:54 PM PST 24
Peak memory 215724 kb
Host smart-b4977c75-e741-47bb-9e60-822655834854
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384761876 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.kmac_test_vectors_kmac.384761876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1500765672
Short name T774
Test name
Test status
Simulation time 974807372 ps
CPU time 5.25 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 215596 kb
Host smart-f2111eb0-4dfc-495e-b278-7cda82c5e873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500765672 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1500765672 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.1577680436
Short name T608
Test name
Test status
Simulation time 72062468269 ps
CPU time 1394.26 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:27:42 PM PST 24
Peak memory 339064 kb
Host smart-0c2522ab-9262-4083-ac7b-41027383dcdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1577680436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1577680436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.101470463
Short name T233
Test name
Test status
Simulation time 51354268388 ps
CPU time 969.65 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:20:55 PM PST 24
Peak memory 296720 kb
Host smart-dc10588c-e8f8-46e5-9219-f74ad0b07234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101470463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.101470463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.4255235828
Short name T668
Test name
Test status
Simulation time 145434450692 ps
CPU time 3991.04 seconds
Started Jan 07 01:04:49 PM PST 24
Finished Jan 07 02:11:22 PM PST 24
Peak memory 561984 kb
Host smart-0e3c6a0c-3990-48c3-8f5e-373d4ffecc0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4255235828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.4255235828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2479823430
Short name T469
Test name
Test status
Simulation time 25478860 ps
CPU time 0.77 seconds
Started Jan 07 01:04:45 PM PST 24
Finished Jan 07 01:04:48 PM PST 24
Peak memory 205132 kb
Host smart-08795a31-0815-4d3b-8f2b-cde84b6629ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479823430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2479823430 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3282282136
Short name T408
Test name
Test status
Simulation time 3292235186 ps
CPU time 78.71 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:05:58 PM PST 24
Peak memory 226804 kb
Host smart-5c272712-75b9-4a73-a9c6-7ad951aebdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282282136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3282282136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.1708213183
Short name T663
Test name
Test status
Simulation time 19204217098 ps
CPU time 472.59 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:12:34 PM PST 24
Peak memory 229132 kb
Host smart-e3645161-0f73-45db-9d7f-b07da61702db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708213183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1708213183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.4293559957
Short name T876
Test name
Test status
Simulation time 331497452 ps
CPU time 6.27 seconds
Started Jan 07 01:04:44 PM PST 24
Finished Jan 07 01:04:53 PM PST 24
Peak memory 223744 kb
Host smart-06e528fa-abf9-4f07-b063-58cfdb9a93f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293559957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.4293559957 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.1333032295
Short name T475
Test name
Test status
Simulation time 4013150259 ps
CPU time 63.73 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 224840 kb
Host smart-252083fc-97df-4cda-9c25-af1bd0fe290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333032295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1333032295 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_key_error.3500752221
Short name T67
Test name
Test status
Simulation time 634945773 ps
CPU time 2.07 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 207392 kb
Host smart-3aea2df5-1632-4bb3-9345-75eb9a5affa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500752221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3500752221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.51640637
Short name T648
Test name
Test status
Simulation time 191410052925 ps
CPU time 1038.42 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:22:00 PM PST 24
Peak memory 307776 kb
Host smart-c1ee6103-3fc5-48ad-9214-39a17c7ad4bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51640637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and
_output.51640637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1441921898
Short name T910
Test name
Test status
Simulation time 14597760485 ps
CPU time 196.97 seconds
Started Jan 07 01:04:45 PM PST 24
Finished Jan 07 01:08:04 PM PST 24
Peak memory 237396 kb
Host smart-f5bebe6a-848e-430f-982a-01e76ec1d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441921898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1441921898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.28303536
Short name T329
Test name
Test status
Simulation time 980738344 ps
CPU time 48.29 seconds
Started Jan 07 01:04:45 PM PST 24
Finished Jan 07 01:05:35 PM PST 24
Peak memory 218660 kb
Host smart-539a289e-d548-48b9-a98c-04eae9ff394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28303536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.28303536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all_with_rand_reset.3883172639
Short name T126
Test name
Test status
Simulation time 70726499500 ps
CPU time 641.88 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:15:23 PM PST 24
Peak memory 272204 kb
Host smart-c1bc6912-76a4-49aa-8f8f-69911535992c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883172639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.3883172639 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.2868788414
Short name T913
Test name
Test status
Simulation time 115692020 ps
CPU time 3.75 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:04:42 PM PST 24
Peak memory 215688 kb
Host smart-265739de-140b-4fa8-ac24-c2d1f940d4c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868788414 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.2868788414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.21673195
Short name T572
Test name
Test status
Simulation time 537621291 ps
CPU time 4.3 seconds
Started Jan 07 01:04:48 PM PST 24
Finished Jan 07 01:04:54 PM PST 24
Peak memory 215756 kb
Host smart-d7cf80f0-549f-4467-a10f-f06a9e80e29d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673195 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.kmac_test_vectors_kmac_xof.21673195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.552107706
Short name T528
Test name
Test status
Simulation time 17417332259 ps
CPU time 1341.75 seconds
Started Jan 07 01:04:44 PM PST 24
Finished Jan 07 01:27:08 PM PST 24
Peak memory 366980 kb
Host smart-6a013862-46c0-4b12-9e4e-b727bd5f04dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=552107706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.552107706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1954323473
Short name T706
Test name
Test status
Simulation time 241322140620 ps
CPU time 1419.82 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:28:12 PM PST 24
Peak memory 333684 kb
Host smart-a8b16a91-c32f-4e55-9cc5-75472bb9636c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1954323473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1954323473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.3291494462
Short name T733
Test name
Test status
Simulation time 9416593558 ps
CPU time 782.85 seconds
Started Jan 07 01:04:50 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 292644 kb
Host smart-b94853ec-c89c-42ca-9727-ac2d40c042cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3291494462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3291494462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1095732889
Short name T759
Test name
Test status
Simulation time 181660188425 ps
CPU time 3228.26 seconds
Started Jan 07 01:04:52 PM PST 24
Finished Jan 07 01:58:42 PM PST 24
Peak memory 566520 kb
Host smart-bdacd80c-c477-42a0-9f42-04bb76428a10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1095732889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1095732889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1118669484
Short name T458
Test name
Test status
Simulation time 525582056 ps
CPU time 13.06 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:04:50 PM PST 24
Peak memory 223732 kb
Host smart-21f535ba-413c-4fc3-a3ce-f0425c732120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118669484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1118669484 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3852468785
Short name T566
Test name
Test status
Simulation time 335026399 ps
CPU time 3.33 seconds
Started Jan 07 01:04:50 PM PST 24
Finished Jan 07 01:04:55 PM PST 24
Peak memory 220240 kb
Host smart-f8c50e1e-c147-45e4-9d6f-decef1bb5f7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3852468785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3852468785 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_error.530835724
Short name T750
Test name
Test status
Simulation time 1289180298 ps
CPU time 94.56 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:06:16 PM PST 24
Peak memory 240208 kb
Host smart-c5f4907c-d207-4dc6-9de1-a55b6801f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530835724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.530835724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2147312398
Short name T441
Test name
Test status
Simulation time 150654746 ps
CPU time 1.23 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:04:33 PM PST 24
Peak memory 215624 kb
Host smart-ea9f3cfb-a79e-43a8-9f11-53a9379eb68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147312398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2147312398 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.343487681
Short name T487
Test name
Test status
Simulation time 18577505602 ps
CPU time 1596.2 seconds
Started Jan 07 01:04:25 PM PST 24
Finished Jan 07 01:31:04 PM PST 24
Peak memory 396948 kb
Host smart-b5c99278-f419-4fb9-9e68-34470aae37f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343487681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an
d_output.343487681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3772750303
Short name T386
Test name
Test status
Simulation time 22835369555 ps
CPU time 151.89 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:07:02 PM PST 24
Peak memory 234048 kb
Host smart-f3b0c32e-4128-4ff1-b58c-d4104081ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772750303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3772750303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.1245495642
Short name T633
Test name
Test status
Simulation time 827251825 ps
CPU time 4.3 seconds
Started Jan 07 01:04:51 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 215700 kb
Host smart-1dc5d25c-2054-4113-99be-4d0d236dfe7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245495642 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.1245495642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2354102280
Short name T631
Test name
Test status
Simulation time 70969952 ps
CPU time 3.73 seconds
Started Jan 07 01:04:45 PM PST 24
Finished Jan 07 01:04:51 PM PST 24
Peak memory 215672 kb
Host smart-ab085f58-86f8-4405-b394-dc01d8a77c67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354102280 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2354102280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.392970958
Short name T891
Test name
Test status
Simulation time 535225643248 ps
CPU time 1998.8 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:38:01 PM PST 24
Peak memory 387968 kb
Host smart-4a1fa31d-6e80-4523-a6ba-3d5e241199fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=392970958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.392970958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.1682297162
Short name T537
Test name
Test status
Simulation time 62072513568 ps
CPU time 1777.03 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:34:20 PM PST 24
Peak memory 376176 kb
Host smart-fff02fbb-780c-4a4a-aeb9-ca878535ffdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1682297162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.1682297162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.57453358
Short name T247
Test name
Test status
Simulation time 92271443852 ps
CPU time 1249.13 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:25:28 PM PST 24
Peak memory 330144 kb
Host smart-da49f4fd-3731-4374-a4dc-6c8cf1c0b64c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57453358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.57453358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.625815421
Short name T278
Test name
Test status
Simulation time 137830020027 ps
CPU time 859.27 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:18:53 PM PST 24
Peak memory 288964 kb
Host smart-679a683d-4d39-4151-a173-72f07cb8d51a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=625815421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.625815421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.2479766715
Short name T872
Test name
Test status
Simulation time 244405498153 ps
CPU time 4119.75 seconds
Started Jan 07 01:04:47 PM PST 24
Finished Jan 07 02:13:29 PM PST 24
Peak memory 659888 kb
Host smart-02efa89b-6a27-4440-a689-6e9f291a91c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2479766715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2479766715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3713781269
Short name T227
Test name
Test status
Simulation time 52983422951 ps
CPU time 3221.38 seconds
Started Jan 07 01:04:39 PM PST 24
Finished Jan 07 01:58:24 PM PST 24
Peak memory 553036 kb
Host smart-cd3e344a-8090-4416-ad1a-b1c1f40c90ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3713781269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3713781269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3404781851
Short name T767
Test name
Test status
Simulation time 12630014 ps
CPU time 0.75 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 205192 kb
Host smart-17438e3b-f8d8-481e-b045-eaf375569752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404781851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3404781851 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.730797116
Short name T348
Test name
Test status
Simulation time 64034038391 ps
CPU time 276.05 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:10:55 PM PST 24
Peak memory 245608 kb
Host smart-8c872122-ecf7-4805-89bf-b745e4d83f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730797116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.730797116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3705800170
Short name T658
Test name
Test status
Simulation time 11117583914 ps
CPU time 323.41 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:10:03 PM PST 24
Peak memory 228216 kb
Host smart-0d71eabf-2753-4789-8ed0-09abc0f226b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705800170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3705800170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.2856819712
Short name T609
Test name
Test status
Simulation time 2224733439 ps
CPU time 18.69 seconds
Started Jan 07 01:04:48 PM PST 24
Finished Jan 07 01:05:08 PM PST 24
Peak memory 215620 kb
Host smart-b4e04fc8-7d40-43b3-ba3a-bb98000c8bed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2856819712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2856819712 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1767574942
Short name T816
Test name
Test status
Simulation time 855640566 ps
CPU time 31.17 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:31 PM PST 24
Peak memory 223540 kb
Host smart-87969f08-f442-45b9-9eec-53586350ea48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767574942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1767574942 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_error.918674036
Short name T801
Test name
Test status
Simulation time 46436371298 ps
CPU time 202.18 seconds
Started Jan 07 01:04:59 PM PST 24
Finished Jan 07 01:08:23 PM PST 24
Peak memory 255816 kb
Host smart-05f12d45-00f2-4bbb-b084-8e0c35930632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918674036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.918674036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2419270406
Short name T803
Test name
Test status
Simulation time 2649291030 ps
CPU time 4.51 seconds
Started Jan 07 01:04:50 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 207428 kb
Host smart-d91d0d40-5ff7-4f6c-92dd-ed4a50621e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419270406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2419270406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.4189464312
Short name T573
Test name
Test status
Simulation time 4339859501 ps
CPU time 8.44 seconds
Started Jan 07 01:05:00 PM PST 24
Finished Jan 07 01:05:10 PM PST 24
Peak memory 222104 kb
Host smart-1a4ef187-b69e-4248-8654-1c4aff6789ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189464312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4189464312 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2573442764
Short name T392
Test name
Test status
Simulation time 278620547610 ps
CPU time 1608.63 seconds
Started Jan 07 01:04:39 PM PST 24
Finished Jan 07 01:31:30 PM PST 24
Peak memory 368820 kb
Host smart-d53394d6-0435-439f-8df5-16c5a168e591
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573442764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2573442764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3378650576
Short name T832
Test name
Test status
Simulation time 1946592127 ps
CPU time 141.94 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:06:57 PM PST 24
Peak memory 232076 kb
Host smart-2c2cf673-7c7e-47d2-9236-9e683fe4ae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378650576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3378650576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3531238642
Short name T753
Test name
Test status
Simulation time 1684756052 ps
CPU time 18.24 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:04:59 PM PST 24
Peak memory 218380 kb
Host smart-46d7030d-741c-4d0d-9ccf-ab0c510b3de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531238642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3531238642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.1114070437
Short name T344
Test name
Test status
Simulation time 77648021899 ps
CPU time 510.54 seconds
Started Jan 07 01:04:59 PM PST 24
Finished Jan 07 01:13:31 PM PST 24
Peak memory 300480 kb
Host smart-b1be0380-b1f9-4c98-b605-4b0609d0a503
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1114070437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1114070437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_stress_all_with_rand_reset.3314101495
Short name T165
Test name
Test status
Simulation time 25962688096 ps
CPU time 1003.81 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:21:47 PM PST 24
Peak memory 322636 kb
Host smart-8582cac1-53b8-4cf9-8cd3-3e6f73a35452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314101495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.3314101495 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.392954711
Short name T287
Test name
Test status
Simulation time 257769135 ps
CPU time 3.59 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:43 PM PST 24
Peak memory 215676 kb
Host smart-969b091c-3883-40b0-8756-01d601e40396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392954711 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.392954711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.183438998
Short name T214
Test name
Test status
Simulation time 36418945453 ps
CPU time 1468.41 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:29:28 PM PST 24
Peak memory 371504 kb
Host smart-0ce5ce6f-4152-44a8-99d2-8a2b8e8067a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=183438998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.183438998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2967144800
Short name T412
Test name
Test status
Simulation time 35315115874 ps
CPU time 1419.92 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:28:25 PM PST 24
Peak memory 372432 kb
Host smart-4c15f032-1647-4357-834c-21a27fa4362c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2967144800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2967144800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3946982490
Short name T221
Test name
Test status
Simulation time 320076529027 ps
CPU time 1317.59 seconds
Started Jan 07 01:04:42 PM PST 24
Finished Jan 07 01:26:42 PM PST 24
Peak memory 340912 kb
Host smart-6a4b0c44-32ae-45f0-89fa-6dbcf9d38e9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3946982490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3946982490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.3202240180
Short name T322
Test name
Test status
Simulation time 65626758134 ps
CPU time 893.91 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:19:28 PM PST 24
Peak memory 292120 kb
Host smart-cd123bb3-4c5b-4187-96ad-a3bd64a050d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3202240180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3202240180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.1173065340
Short name T363
Test name
Test status
Simulation time 342737070813 ps
CPU time 4614.88 seconds
Started Jan 07 01:04:36 PM PST 24
Finished Jan 07 02:21:35 PM PST 24
Peak memory 647360 kb
Host smart-40a091a5-b176-411d-8b4c-80a430266b5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1173065340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1173065340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.2884656352
Short name T849
Test name
Test status
Simulation time 86731224071 ps
CPU time 3527.38 seconds
Started Jan 07 01:04:50 PM PST 24
Finished Jan 07 02:03:39 PM PST 24
Peak memory 562840 kb
Host smart-6b611cc6-7509-47b8-86db-fd647f1df879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2884656352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2884656352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.2476825580
Short name T266
Test name
Test status
Simulation time 2588360081 ps
CPU time 18.48 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:18 PM PST 24
Peak memory 218120 kb
Host smart-7f5c83d9-6339-48c3-8a71-f1c0ed7a5ceb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476825580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2476825580 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_error.1453005492
Short name T758
Test name
Test status
Simulation time 165345971780 ps
CPU time 287.53 seconds
Started Jan 07 01:05:08 PM PST 24
Finished Jan 07 01:09:57 PM PST 24
Peak memory 256708 kb
Host smart-0fab9ddc-a764-4eb1-9869-4e5921861dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453005492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1453005492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2079010562
Short name T24
Test name
Test status
Simulation time 465493284 ps
CPU time 2.85 seconds
Started Jan 07 01:04:45 PM PST 24
Finished Jan 07 01:04:50 PM PST 24
Peak memory 206924 kb
Host smart-f3be6dc5-3320-4d9b-abcc-e8ada1f92c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079010562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2079010562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_sideload.2429529370
Short name T346
Test name
Test status
Simulation time 15415689266 ps
CPU time 77.37 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 224840 kb
Host smart-eda7e801-8852-46c6-b4fd-eb034fb6feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429529370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2429529370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3904904590
Short name T361
Test name
Test status
Simulation time 698955240 ps
CPU time 15.24 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:05:18 PM PST 24
Peak memory 218228 kb
Host smart-7f4da45d-aae0-4335-bb1a-affce144fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904904590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3904904590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1290526412
Short name T349
Test name
Test status
Simulation time 86150585832 ps
CPU time 568.19 seconds
Started Jan 07 01:05:04 PM PST 24
Finished Jan 07 01:14:34 PM PST 24
Peak memory 314304 kb
Host smart-4e40d8da-4bd5-407b-82f8-98755cc07cbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1290526412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1290526412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2841132618
Short name T563
Test name
Test status
Simulation time 134741376 ps
CPU time 3.95 seconds
Started Jan 07 01:04:59 PM PST 24
Finished Jan 07 01:05:05 PM PST 24
Peak memory 209148 kb
Host smart-e77ec693-fe45-4ef1-a029-44592b2d4f44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841132618 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2841132618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2301978368
Short name T388
Test name
Test status
Simulation time 195287107260 ps
CPU time 1895.88 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:36:33 PM PST 24
Peak memory 386900 kb
Host smart-557364c3-375c-4f0b-9e2c-ba7c614fbde9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2301978368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2301978368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3208097553
Short name T672
Test name
Test status
Simulation time 35684720926 ps
CPU time 1405.72 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 01:28:33 PM PST 24
Peak memory 368720 kb
Host smart-3088da80-a0c2-493b-9004-9b798e707842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3208097553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3208097553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3655426044
Short name T604
Test name
Test status
Simulation time 72851618457 ps
CPU time 1470.47 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:29:27 PM PST 24
Peak memory 335852 kb
Host smart-2de309e7-e690-435b-b3f7-522aacca2486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3655426044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3655426044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2731488874
Short name T776
Test name
Test status
Simulation time 42169476307 ps
CPU time 779.93 seconds
Started Jan 07 01:04:56 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 298652 kb
Host smart-24d63c40-bbb1-48f7-8dd1-11595737f64d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2731488874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2731488874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1621597785
Short name T420
Test name
Test status
Simulation time 187850054232 ps
CPU time 3950.5 seconds
Started Jan 07 01:05:00 PM PST 24
Finished Jan 07 02:10:53 PM PST 24
Peak memory 647120 kb
Host smart-5579d56c-7975-47c8-bf17-c0b0d3958568
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1621597785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1621597785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1316413915
Short name T257
Test name
Test status
Simulation time 291703136561 ps
CPU time 3825.36 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 02:08:50 PM PST 24
Peak memory 547280 kb
Host smart-34546344-318d-4b2e-b612-8908ff1711ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1316413915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1316413915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.789915746
Short name T494
Test name
Test status
Simulation time 28672766 ps
CPU time 0.71 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 205168 kb
Host smart-a84cf98a-ee2c-4ca1-9299-5e51cee696f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789915746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.789915746 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.3647257867
Short name T823
Test name
Test status
Simulation time 48466327052 ps
CPU time 200.25 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:07:13 PM PST 24
Peak memory 237532 kb
Host smart-75d8c348-e159-4612-b40d-80c89abd67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647257867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3647257867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2265026173
Short name T102
Test name
Test status
Simulation time 4441007886 ps
CPU time 67.06 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:05:06 PM PST 24
Peak memory 224788 kb
Host smart-5fe8370f-c819-41c6-8894-e1d35671f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265026173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2265026173 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2730339714
Short name T507
Test name
Test status
Simulation time 28226049038 ps
CPU time 574.28 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:13:26 PM PST 24
Peak memory 231560 kb
Host smart-54bf56e6-2851-4769-8596-2e9c04e1f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730339714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2730339714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2004975979
Short name T289
Test name
Test status
Simulation time 1305036883 ps
CPU time 23.75 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:21 PM PST 24
Peak memory 217232 kb
Host smart-1442b787-8f38-4e4c-89e7-fb8fae0a52a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2004975979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2004975979 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.3178476309
Short name T373
Test name
Test status
Simulation time 236256760 ps
CPU time 16.57 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:04:13 PM PST 24
Peak memory 223764 kb
Host smart-3c3f7767-8ab2-4319-86ed-ef1cb4d2b632
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178476309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3178476309 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3062126968
Short name T538
Test name
Test status
Simulation time 11889327118 ps
CPU time 58.41 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:04:58 PM PST 24
Peak memory 215652 kb
Host smart-2dbbcd28-2a50-4edb-8bfa-f555d24cfdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062126968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3062126968 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3713724178
Short name T333
Test name
Test status
Simulation time 298100439 ps
CPU time 7.14 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 220516 kb
Host smart-1faf996a-a9e5-4cd0-93ba-96b0840a9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713724178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3713724178 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_key_error.2307408612
Short name T756
Test name
Test status
Simulation time 552711843 ps
CPU time 1.36 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 206692 kb
Host smart-8e9978a9-e873-4adb-8744-e530b1a746d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307408612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2307408612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1457658006
Short name T731
Test name
Test status
Simulation time 183963993 ps
CPU time 1.25 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 215624 kb
Host smart-d8a11eb1-4a09-4c18-9d33-f133bd9f7543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457658006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1457658006 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_mubi.256858302
Short name T505
Test name
Test status
Simulation time 4469364049 ps
CPU time 53.71 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:56 PM PST 24
Peak memory 225196 kb
Host smart-df9d4322-85c2-4e54-965e-45eb70a3fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256858302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.256858302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1907164936
Short name T68
Test name
Test status
Simulation time 5618200327 ps
CPU time 35.49 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:45 PM PST 24
Peak memory 250172 kb
Host smart-653fe197-8362-4ead-8711-354cec4e00cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907164936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1907164936 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1937500178
Short name T568
Test name
Test status
Simulation time 14578676241 ps
CPU time 285.24 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:08:41 PM PST 24
Peak memory 243692 kb
Host smart-5a14a821-d9ea-4bf1-b19c-5149a70ba885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937500178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1937500178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.668420729
Short name T779
Test name
Test status
Simulation time 322514828 ps
CPU time 7.22 seconds
Started Jan 07 01:04:14 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 219128 kb
Host smart-390077e7-1c7f-4a8b-984f-6826f091c06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668420729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.668420729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2341914559
Short name T887
Test name
Test status
Simulation time 14763882345 ps
CPU time 336.37 seconds
Started Jan 07 01:04:01 PM PST 24
Finished Jan 07 01:09:42 PM PST 24
Peak memory 289784 kb
Host smart-401a1e01-5ebf-43c1-821f-649a00da87d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2341914559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2341914559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.520173222
Short name T842
Test name
Test status
Simulation time 124122495 ps
CPU time 3.89 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 215708 kb
Host smart-87b6f893-11e8-4232-94a6-ac3917bf738c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520173222 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.520173222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3361924698
Short name T286
Test name
Test status
Simulation time 173075117 ps
CPU time 4.8 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 208956 kb
Host smart-04efecd9-7d5b-43a6-9bc3-1dc56777bf01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361924698 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3361924698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2046790069
Short name T834
Test name
Test status
Simulation time 207236790151 ps
CPU time 1768.47 seconds
Started Jan 07 01:03:46 PM PST 24
Finished Jan 07 01:33:21 PM PST 24
Peak memory 399712 kb
Host smart-d270e910-3d09-49e3-b5c0-9e69d799244d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2046790069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2046790069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3482587469
Short name T337
Test name
Test status
Simulation time 63137335835 ps
CPU time 1591.08 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:30:21 PM PST 24
Peak memory 370888 kb
Host smart-9ad7dc16-9418-4a28-bf22-28e90afe148f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3482587469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3482587469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.120136628
Short name T175
Test name
Test status
Simulation time 10066453263 ps
CPU time 787.83 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:17:02 PM PST 24
Peak memory 292008 kb
Host smart-1984586d-86ed-4987-80e8-db030b6813b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=120136628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.120136628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1710974989
Short name T653
Test name
Test status
Simulation time 215598627245 ps
CPU time 4097.83 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 02:12:18 PM PST 24
Peak memory 669216 kb
Host smart-e1e47bfe-0d70-4ce5-b04e-97e431d17aa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1710974989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1710974989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_alert_test.4203031866
Short name T888
Test name
Test status
Simulation time 21571461 ps
CPU time 0.84 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:04:54 PM PST 24
Peak memory 205184 kb
Host smart-dad4428e-b1de-46e2-b6da-bf849b88c475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203031866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4203031866 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.4164514768
Short name T201
Test name
Test status
Simulation time 31262153247 ps
CPU time 174.25 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:07:50 PM PST 24
Peak memory 235676 kb
Host smart-e977d49a-a7f4-4c88-b3aa-62789409afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164514768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.4164514768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2309445123
Short name T867
Test name
Test status
Simulation time 53026699129 ps
CPU time 217.05 seconds
Started Jan 07 01:04:59 PM PST 24
Finished Jan 07 01:08:38 PM PST 24
Peak memory 238628 kb
Host smart-048eb886-c72e-4700-b2f6-95e21f8c5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309445123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2309445123 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1182618871
Short name T356
Test name
Test status
Simulation time 1005631975 ps
CPU time 5.59 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:04:59 PM PST 24
Peak memory 221636 kb
Host smart-737c1f19-90f6-4c1f-962d-042dade00bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182618871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1182618871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.1568611659
Short name T695
Test name
Test status
Simulation time 2064639722 ps
CPU time 2.8 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 207092 kb
Host smart-69857dae-fbd8-4fae-81bb-88d7b13d4e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568611659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1568611659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.513591017
Short name T489
Test name
Test status
Simulation time 806698590 ps
CPU time 10.11 seconds
Started Jan 07 01:04:56 PM PST 24
Finished Jan 07 01:05:07 PM PST 24
Peak memory 223972 kb
Host smart-3dcdcb20-28bb-4612-b994-cec9ab0af16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513591017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.513591017 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_sideload.1302009316
Short name T436
Test name
Test status
Simulation time 23309729934 ps
CPU time 231.95 seconds
Started Jan 07 01:04:52 PM PST 24
Finished Jan 07 01:08:45 PM PST 24
Peak memory 237432 kb
Host smart-82578fd0-cdc7-4639-81b3-6f65d6880653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302009316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1302009316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.383985002
Short name T827
Test name
Test status
Simulation time 2738115404 ps
CPU time 43.05 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:43 PM PST 24
Peak memory 218652 kb
Host smart-d3dd809b-6946-483c-a2f6-0d839d604893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383985002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.383985002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.1618199900
Short name T415
Test name
Test status
Simulation time 242822574 ps
CPU time 4.89 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:04 PM PST 24
Peak memory 215764 kb
Host smart-5453010a-53d7-4ae9-802e-1bb79c001693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618199900 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.1618199900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1102327515
Short name T224
Test name
Test status
Simulation time 94044855810 ps
CPU time 1855.16 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:36:00 PM PST 24
Peak memory 372368 kb
Host smart-92e2c443-86bd-4d1c-ad83-535d2253b8cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1102327515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1102327515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.4200219871
Short name T498
Test name
Test status
Simulation time 13801923614 ps
CPU time 1111.77 seconds
Started Jan 07 01:05:01 PM PST 24
Finished Jan 07 01:23:34 PM PST 24
Peak memory 338004 kb
Host smart-2958867b-8302-4e36-b435-3e3e3df27307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4200219871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.4200219871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1686185664
Short name T295
Test name
Test status
Simulation time 35399495499 ps
CPU time 776.84 seconds
Started Jan 07 01:04:57 PM PST 24
Finished Jan 07 01:17:55 PM PST 24
Peak memory 295176 kb
Host smart-d80ed194-262d-4fa0-b1a1-2cb15c030009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1686185664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1686185664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.239565911
Short name T279
Test name
Test status
Simulation time 171097521466 ps
CPU time 4611.12 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 02:21:46 PM PST 24
Peak memory 644780 kb
Host smart-1d8ce377-82ce-4388-9ae0-027afeef563d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=239565911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.239565911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2763272390
Short name T254
Test name
Test status
Simulation time 182250417738 ps
CPU time 3390.57 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 02:01:27 PM PST 24
Peak memory 570672 kb
Host smart-7c8bb76e-ae2e-408b-b02a-b4bb081fc588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2763272390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2763272390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1486403335
Short name T407
Test name
Test status
Simulation time 32354985 ps
CPU time 0.78 seconds
Started Jan 07 01:05:07 PM PST 24
Finished Jan 07 01:05:09 PM PST 24
Peak memory 205224 kb
Host smart-5f00f1fe-cbc4-49f9-91ca-72d5c4f27f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486403335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1486403335 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_burst_write.542560127
Short name T896
Test name
Test status
Simulation time 52620516797 ps
CPU time 353.99 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:10:48 PM PST 24
Peak memory 228268 kb
Host smart-b25d26fb-f216-4f5a-bb62-08e4f1c93198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542560127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.542560127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.122059613
Short name T838
Test name
Test status
Simulation time 3379536796 ps
CPU time 60.02 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 225372 kb
Host smart-ded0cbfb-48da-4e18-bb25-6567f2a77cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122059613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.122059613 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.1483473148
Short name T677
Test name
Test status
Simulation time 14963993037 ps
CPU time 384.12 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:11:24 PM PST 24
Peak memory 269740 kb
Host smart-4a2eb7bd-35a2-497a-a68d-011b3e591a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483473148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1483473148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3250892696
Short name T877
Test name
Test status
Simulation time 2826664489 ps
CPU time 5.06 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:05:08 PM PST 24
Peak memory 207400 kb
Host smart-aefadc33-3c79-4f77-ba2d-da79a0a94c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250892696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3250892696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1599854681
Short name T380
Test name
Test status
Simulation time 45348638 ps
CPU time 1.36 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 01:05:08 PM PST 24
Peak memory 220220 kb
Host smart-61a4ef4e-c361-4a75-bc07-f3ed9ef0f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599854681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1599854681 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_sideload.2906042680
Short name T502
Test name
Test status
Simulation time 16206314992 ps
CPU time 276.22 seconds
Started Jan 07 01:04:56 PM PST 24
Finished Jan 07 01:09:33 PM PST 24
Peak memory 246436 kb
Host smart-db580b5d-da51-4ae5-81ce-715829cb0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906042680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2906042680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_stress_all_with_rand_reset.961382687
Short name T561
Test name
Test status
Simulation time 66067631893 ps
CPU time 969.09 seconds
Started Jan 07 01:05:04 PM PST 24
Finished Jan 07 01:21:15 PM PST 24
Peak memory 272932 kb
Host smart-f4a57667-64e7-4e03-bb79-c5c312af1769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961382687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.961382687 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.412940408
Short name T637
Test name
Test status
Simulation time 332804596 ps
CPU time 4.73 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:05:03 PM PST 24
Peak memory 209116 kb
Host smart-e61cf7d9-2848-4883-92b8-d4d6dbc2086a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412940408 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_test_vectors_kmac.412940408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3348665928
Short name T292
Test name
Test status
Simulation time 257675943 ps
CPU time 4.15 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 215532 kb
Host smart-9e51af07-9b91-4b66-8323-2b56474a0a8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348665928 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3348665928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.4227197152
Short name T256
Test name
Test status
Simulation time 67007404369 ps
CPU time 1516.43 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:30:12 PM PST 24
Peak memory 390724 kb
Host smart-a7cdd020-cb94-4549-80b3-530be539f53c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4227197152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.4227197152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3396711017
Short name T717
Test name
Test status
Simulation time 18050060931 ps
CPU time 1486.42 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:29:46 PM PST 24
Peak memory 386968 kb
Host smart-b33ea50f-bcb8-47a1-95e2-961ead258647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3396711017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3396711017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.1999353759
Short name T817
Test name
Test status
Simulation time 14414648771 ps
CPU time 1126.89 seconds
Started Jan 07 01:04:57 PM PST 24
Finished Jan 07 01:23:46 PM PST 24
Peak memory 338536 kb
Host smart-44f68a0f-e366-4671-a499-b2d443e4e523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1999353759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.1999353759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3338407027
Short name T249
Test name
Test status
Simulation time 42363080856 ps
CPU time 851.44 seconds
Started Jan 07 01:04:57 PM PST 24
Finished Jan 07 01:19:10 PM PST 24
Peak memory 294068 kb
Host smart-2d06cfef-f050-48f3-b860-121d82c98551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3338407027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3338407027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.1922966544
Short name T138
Test name
Test status
Simulation time 759123201812 ps
CPU time 3978.94 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 02:11:15 PM PST 24
Peak memory 568364 kb
Host smart-e5b2cecf-4780-484f-a324-1eae98427d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1922966544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1922966544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2400696490
Short name T429
Test name
Test status
Simulation time 62154292 ps
CPU time 0.74 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:06:01 PM PST 24
Peak memory 205116 kb
Host smart-bbc32c16-c873-454c-9cd2-8888eac9eb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400696490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2400696490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2585728022
Short name T536
Test name
Test status
Simulation time 1703793474 ps
CPU time 83.53 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:07:18 PM PST 24
Peak memory 229260 kb
Host smart-fef1a094-6a2b-4ad0-a842-8a87a1b63e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585728022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2585728022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.126605042
Short name T450
Test name
Test status
Simulation time 20304988849 ps
CPU time 389.61 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:12:06 PM PST 24
Peak memory 228932 kb
Host smart-cfa35b9d-da6d-42c3-a861-2f243aa7f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126605042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.126605042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.593852618
Short name T786
Test name
Test status
Simulation time 12387664147 ps
CPU time 262.04 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:10:08 PM PST 24
Peak memory 241636 kb
Host smart-0e2f1304-7188-4c0b-9c53-0ea3323b4bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593852618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.593852618 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3940660981
Short name T92
Test name
Test status
Simulation time 2162728543 ps
CPU time 127.25 seconds
Started Jan 07 01:05:37 PM PST 24
Finished Jan 07 01:07:45 PM PST 24
Peak memory 248504 kb
Host smart-28f4a291-d488-4bce-8ba7-48e915d93da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940660981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3940660981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.55058283
Short name T798
Test name
Test status
Simulation time 517820484 ps
CPU time 3.21 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 207188 kb
Host smart-fc1ffdbe-dec2-446f-bc66-c76d527fa7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55058283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.55058283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1653981514
Short name T434
Test name
Test status
Simulation time 294302196149 ps
CPU time 2186.63 seconds
Started Jan 07 01:05:12 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 474412 kb
Host smart-99730db9-63b4-4920-9440-60e30f2fa95f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653981514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1653981514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_smoke.774787659
Short name T696
Test name
Test status
Simulation time 28887557056 ps
CPU time 54.43 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:05:59 PM PST 24
Peak memory 218984 kb
Host smart-4c757a71-ed65-4522-8952-3b819986d7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774787659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.774787659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3155859135
Short name T621
Test name
Test status
Simulation time 70907355585 ps
CPU time 222.19 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 239296 kb
Host smart-344f407a-44bd-4a3a-9778-c34e82481290
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3155859135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3155859135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_stress_all_with_rand_reset.3927379221
Short name T347
Test name
Test status
Simulation time 159609834891 ps
CPU time 892.43 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:20:59 PM PST 24
Peak memory 302440 kb
Host smart-182589e8-9e9a-49a9-88a1-aa39337bc979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927379221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all_with_rand_reset.3927379221 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.2756685393
Short name T410
Test name
Test status
Simulation time 859498265 ps
CPU time 4.71 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:04 PM PST 24
Peak memory 215748 kb
Host smart-a8bf21e6-faec-4ac2-a37f-6447261b4786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756685393 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.2756685393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1401373465
Short name T186
Test name
Test status
Simulation time 68731563 ps
CPU time 3.96 seconds
Started Jan 07 01:05:25 PM PST 24
Finished Jan 07 01:05:30 PM PST 24
Peak memory 215824 kb
Host smart-ab162ba2-ae34-47e4-b96d-37bafbe2b476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401373465 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1401373465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.3892882482
Short name T310
Test name
Test status
Simulation time 19210453693 ps
CPU time 1522 seconds
Started Jan 07 01:05:38 PM PST 24
Finished Jan 07 01:31:01 PM PST 24
Peak memory 391864 kb
Host smart-3086f0b9-811d-4382-a9ce-fb97d55d83d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3892882482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3892882482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2416082152
Short name T722
Test name
Test status
Simulation time 63150233 ps
CPU time 0.82 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:05:05 PM PST 24
Peak memory 205144 kb
Host smart-1d7c27e7-efc1-443a-8d45-a61e133c3c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416082152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2416082152 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1076042223
Short name T382
Test name
Test status
Simulation time 47399245241 ps
CPU time 271.53 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:09:25 PM PST 24
Peak memory 245704 kb
Host smart-80298379-354d-4ef2-ba69-e23e050aec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076042223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1076042223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2253880702
Short name T582
Test name
Test status
Simulation time 27383259858 ps
CPU time 191.48 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:08:08 PM PST 24
Peak memory 240800 kb
Host smart-7afec736-8635-46ad-b2d3-023c559bdec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253880702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2253880702 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.758496199
Short name T399
Test name
Test status
Simulation time 74883447360 ps
CPU time 266.84 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:09:30 PM PST 24
Peak memory 251580 kb
Host smart-453be788-8069-42a1-b132-6cd9804a4749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758496199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.758496199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3281327682
Short name T427
Test name
Test status
Simulation time 37300805 ps
CPU time 1.28 seconds
Started Jan 07 01:05:02 PM PST 24
Finished Jan 07 01:05:05 PM PST 24
Peak memory 220932 kb
Host smart-cb38567a-a872-4803-aa67-c1d4d3b48e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281327682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3281327682 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3914286311
Short name T398
Test name
Test status
Simulation time 126707779921 ps
CPU time 1477.58 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:30:14 PM PST 24
Peak memory 357588 kb
Host smart-95845a23-6237-41bc-8816-c7e6bf800c41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914286311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3914286311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3792590649
Short name T606
Test name
Test status
Simulation time 2738141241 ps
CPU time 188.84 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:09:02 PM PST 24
Peak memory 235984 kb
Host smart-bf763c59-fe9e-4ce2-8964-4d47cf18cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792590649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3792590649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.2333883311
Short name T525
Test name
Test status
Simulation time 2530583355 ps
CPU time 16.6 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 223868 kb
Host smart-ca749883-77d8-4f8d-8348-80463e57720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333883311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2333883311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.2133006462
Short name T371
Test name
Test status
Simulation time 99751541060 ps
CPU time 561.5 seconds
Started Jan 07 01:04:57 PM PST 24
Finished Jan 07 01:14:20 PM PST 24
Peak memory 301656 kb
Host smart-c56cb6da-22d4-400c-8a3c-752b265e7502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2133006462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2133006462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_stress_all_with_rand_reset.174707092
Short name T425
Test name
Test status
Simulation time 95221574919 ps
CPU time 1226.26 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:25:23 PM PST 24
Peak memory 287996 kb
Host smart-435803f8-8cbb-40f2-9a18-0434328e87ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174707092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.174707092 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3433031373
Short name T491
Test name
Test status
Simulation time 241975372 ps
CPU time 4.57 seconds
Started Jan 07 01:05:01 PM PST 24
Finished Jan 07 01:05:07 PM PST 24
Peak memory 215708 kb
Host smart-af30c13e-6c5d-4bd4-b955-8e7108e35fc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433031373 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3433031373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2994781153
Short name T598
Test name
Test status
Simulation time 19058718891 ps
CPU time 1590.58 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:32:31 PM PST 24
Peak memory 396820 kb
Host smart-1df3626a-e160-4b2a-997d-c72d4e1b0b26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2994781153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2994781153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.1319868495
Short name T616
Test name
Test status
Simulation time 481881639259 ps
CPU time 1971.34 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:38:45 PM PST 24
Peak memory 374168 kb
Host smart-1876a20b-9f2f-4899-993c-b8224dca4a69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1319868495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.1319868495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2435173712
Short name T209
Test name
Test status
Simulation time 65411596291 ps
CPU time 1195.08 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:26:04 PM PST 24
Peak memory 332104 kb
Host smart-4eea682e-b6e0-4372-9588-4422a8347c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2435173712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2435173712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.141124448
Short name T615
Test name
Test status
Simulation time 138776095747 ps
CPU time 869.02 seconds
Started Jan 07 01:04:52 PM PST 24
Finished Jan 07 01:19:22 PM PST 24
Peak memory 298788 kb
Host smart-6317bf7b-cf40-42d2-9f7e-ca6c17fb5cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=141124448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.141124448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2778068988
Short name T202
Test name
Test status
Simulation time 216553840842 ps
CPU time 3796.23 seconds
Started Jan 07 01:05:00 PM PST 24
Finished Jan 07 02:08:18 PM PST 24
Peak memory 628976 kb
Host smart-310b5638-a7f5-4764-96f7-5a9ca2c5ad4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2778068988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2778068988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.4176021765
Short name T560
Test name
Test status
Simulation time 1566879768809 ps
CPU time 4323.2 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 02:17:57 PM PST 24
Peak memory 571684 kb
Host smart-35a0dfc8-6222-45cf-b936-4628897a7602
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4176021765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.4176021765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_app.2806208331
Short name T649
Test name
Test status
Simulation time 3655774206 ps
CPU time 70.38 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:06:22 PM PST 24
Peak memory 224904 kb
Host smart-ca6ca754-b21e-4dba-b1cc-9799f1c15840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806208331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2806208331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.2460108736
Short name T277
Test name
Test status
Simulation time 15259603472 ps
CPU time 469.7 seconds
Started Jan 07 01:04:52 PM PST 24
Finished Jan 07 01:12:43 PM PST 24
Peak memory 230360 kb
Host smart-afeddd0a-a774-436e-a39a-e80fb98334c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460108736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2460108736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3651314428
Short name T506
Test name
Test status
Simulation time 40765488770 ps
CPU time 314.57 seconds
Started Jan 07 01:05:09 PM PST 24
Finished Jan 07 01:10:24 PM PST 24
Peak memory 246572 kb
Host smart-4260690d-e721-402e-a5d5-a78a94fc77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651314428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3651314428 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3785645294
Short name T148
Test name
Test status
Simulation time 10139540981 ps
CPU time 47.84 seconds
Started Jan 07 01:05:11 PM PST 24
Finished Jan 07 01:06:00 PM PST 24
Peak memory 232140 kb
Host smart-713838c3-b809-4fa9-8439-a803012998ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785645294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3785645294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.4121366702
Short name T715
Test name
Test status
Simulation time 392784743 ps
CPU time 1.33 seconds
Started Jan 07 01:04:57 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 207048 kb
Host smart-b6e9d18a-cbe3-49f6-bf0e-91c56a2970e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121366702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4121366702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2114616332
Short name T881
Test name
Test status
Simulation time 48947805 ps
CPU time 1.08 seconds
Started Jan 07 01:05:07 PM PST 24
Finished Jan 07 01:05:08 PM PST 24
Peak memory 215700 kb
Host smart-4f51b40a-0021-4a28-9a26-350da4d90f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114616332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2114616332 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.1365330623
Short name T444
Test name
Test status
Simulation time 123078922117 ps
CPU time 2135.2 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:40:32 PM PST 24
Peak memory 466668 kb
Host smart-0a47ad58-f23d-470f-8126-e03aa4bed771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365330623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.1365330623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.1715303085
Short name T319
Test name
Test status
Simulation time 49965666999 ps
CPU time 323.29 seconds
Started Jan 07 01:05:01 PM PST 24
Finished Jan 07 01:10:26 PM PST 24
Peak memory 248160 kb
Host smart-8b66c66a-9f51-4427-bda2-ea3fc0fad1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715303085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1715303085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2336521650
Short name T194
Test name
Test status
Simulation time 1867571426 ps
CPU time 39.89 seconds
Started Jan 07 01:05:05 PM PST 24
Finished Jan 07 01:05:46 PM PST 24
Peak memory 218996 kb
Host smart-f2d4046e-9989-445b-99b7-218255da97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336521650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2336521650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2742463783
Short name T703
Test name
Test status
Simulation time 37710150738 ps
CPU time 770.89 seconds
Started Jan 07 01:05:07 PM PST 24
Finished Jan 07 01:17:58 PM PST 24
Peak memory 330696 kb
Host smart-5a5ca22b-5625-47e5-a06b-99d1b4f5f463
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2742463783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2742463783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.2814277586
Short name T622
Test name
Test status
Simulation time 277002858 ps
CPU time 3.93 seconds
Started Jan 07 01:05:04 PM PST 24
Finished Jan 07 01:05:09 PM PST 24
Peak memory 215684 kb
Host smart-19c878b9-e264-4dc0-a672-bc9fd341ff40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814277586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.2814277586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.136020708
Short name T231
Test name
Test status
Simulation time 68790294 ps
CPU time 4.03 seconds
Started Jan 07 01:05:05 PM PST 24
Finished Jan 07 01:05:10 PM PST 24
Peak memory 215572 kb
Host smart-b9225c6e-d07f-441c-8fa5-2dc74bd353e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136020708 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.136020708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2181940823
Short name T293
Test name
Test status
Simulation time 95975007182 ps
CPU time 1916.29 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:36:53 PM PST 24
Peak memory 387052 kb
Host smart-617dd1a0-bebc-4305-beaa-c2158d9754cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2181940823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2181940823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.707929422
Short name T172
Test name
Test status
Simulation time 34506144001 ps
CPU time 906.93 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:20:12 PM PST 24
Peak memory 297228 kb
Host smart-f4f04fda-3409-4401-8740-2991ae26868c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=707929422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.707929422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3223087928
Short name T639
Test name
Test status
Simulation time 2474447562660 ps
CPU time 4637.68 seconds
Started Jan 07 01:05:11 PM PST 24
Finished Jan 07 02:22:30 PM PST 24
Peak memory 657408 kb
Host smart-973fe6ae-7650-4734-8687-cdde5f302a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3223087928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3223087928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.887148849
Short name T387
Test name
Test status
Simulation time 172615612086 ps
CPU time 3384.54 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 02:01:24 PM PST 24
Peak memory 558564 kb
Host smart-f16c59b4-42e9-4051-8d1d-1cee255602d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=887148849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.887148849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3751593566
Short name T303
Test name
Test status
Simulation time 77497398 ps
CPU time 0.72 seconds
Started Jan 07 01:04:56 PM PST 24
Finished Jan 07 01:04:58 PM PST 24
Peak memory 205168 kb
Host smart-68a08a3b-0f0f-4fc0-99c2-7c99bc208463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751593566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3751593566 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.543580017
Short name T862
Test name
Test status
Simulation time 1050027899 ps
CPU time 23.1 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 218432 kb
Host smart-7d5e939c-98a8-4374-83d9-e675fa35c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543580017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.543580017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.356950556
Short name T234
Test name
Test status
Simulation time 137845458681 ps
CPU time 826.1 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:19:48 PM PST 24
Peak memory 231224 kb
Host smart-a7d80695-6d66-4c53-80a3-ca147681c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356950556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.356950556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1609505972
Short name T473
Test name
Test status
Simulation time 46593504490 ps
CPU time 191.34 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:09:06 PM PST 24
Peak memory 237092 kb
Host smart-2ee717d3-1653-4837-9b1e-605ef326053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609505972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1609505972 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.2903160767
Short name T409
Test name
Test status
Simulation time 1561081276 ps
CPU time 105.64 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 240168 kb
Host smart-2d740262-4b2d-4f46-bedf-2d91965d1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903160767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2903160767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2464753819
Short name T692
Test name
Test status
Simulation time 790132181 ps
CPU time 4.68 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:08 PM PST 24
Peak memory 207396 kb
Host smart-71d66ad9-b701-4bf2-b84b-b4f0f0129d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464753819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2464753819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2667886991
Short name T463
Test name
Test status
Simulation time 2883131175 ps
CPU time 17.39 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:06:17 PM PST 24
Peak memory 232044 kb
Host smart-c9fc4a1e-ff75-4c73-9627-9484c94eccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667886991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2667886991 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_smoke.445499629
Short name T588
Test name
Test status
Simulation time 1857478051 ps
CPU time 26.2 seconds
Started Jan 07 01:05:16 PM PST 24
Finished Jan 07 01:05:43 PM PST 24
Peak memory 222180 kb
Host smart-0b1bbc06-292f-4d45-917a-b245d97db134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445499629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.445499629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.3776147106
Short name T769
Test name
Test status
Simulation time 69116096 ps
CPU time 3.97 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:05:44 PM PST 24
Peak memory 208536 kb
Host smart-c17e9fbe-8c9e-44cd-b817-765d2e512c59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776147106 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.3776147106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.514235933
Short name T900
Test name
Test status
Simulation time 341026369 ps
CPU time 4.78 seconds
Started Jan 07 01:05:38 PM PST 24
Finished Jan 07 01:05:43 PM PST 24
Peak memory 215700 kb
Host smart-650125fb-3ee4-42fd-8b41-7fab2804910c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514235933 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.514235933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.140507041
Short name T179
Test name
Test status
Simulation time 163050915259 ps
CPU time 1726.02 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:34:33 PM PST 24
Peak memory 387376 kb
Host smart-75fecebc-b890-4c43-aabf-fd87e9e07642
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=140507041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.140507041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2838570205
Short name T77
Test name
Test status
Simulation time 188680454264 ps
CPU time 1837.44 seconds
Started Jan 07 01:05:33 PM PST 24
Finished Jan 07 01:36:11 PM PST 24
Peak memory 377424 kb
Host smart-a5931562-7ee7-4e12-8be6-9f7d2ea600f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2838570205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2838570205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3414947335
Short name T848
Test name
Test status
Simulation time 152507087968 ps
CPU time 1451.15 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:29:36 PM PST 24
Peak memory 340064 kb
Host smart-84744b95-5443-4a28-9524-9d94b7985c00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3414947335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3414947335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.2421078925
Short name T655
Test name
Test status
Simulation time 74642221459 ps
CPU time 792.82 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:18:58 PM PST 24
Peak memory 298524 kb
Host smart-382f563d-934f-4de8-9364-35ef19abdd37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2421078925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2421078925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.697392614
Short name T210
Test name
Test status
Simulation time 393739855217 ps
CPU time 5055.59 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 02:29:59 PM PST 24
Peak memory 647264 kb
Host smart-bf95807e-d179-49ee-9e44-a2ab899f33c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=697392614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.697392614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.863320873
Short name T69
Test name
Test status
Simulation time 146109319876 ps
CPU time 3959.46 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 02:12:00 PM PST 24
Peak memory 567672 kb
Host smart-bec1e267-6c7d-4137-9761-e02eec26b5df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=863320873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.863320873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1578954936
Short name T343
Test name
Test status
Simulation time 29281761 ps
CPU time 0.78 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:05:12 PM PST 24
Peak memory 205180 kb
Host smart-8ecac607-9ff5-4d5f-b7fc-d42877b09fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578954936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1578954936 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.151827344
Short name T565
Test name
Test status
Simulation time 4132230107 ps
CPU time 92.4 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:06:37 PM PST 24
Peak memory 229776 kb
Host smart-7c0c2332-f8d4-46fa-8efe-16c6683bb62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151827344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.151827344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.3141401556
Short name T549
Test name
Test status
Simulation time 139733127125 ps
CPU time 789.42 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:18:04 PM PST 24
Peak memory 232300 kb
Host smart-8f85c767-5d63-400d-b1a8-267e9f3f8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141401556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3141401556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3518439293
Short name T260
Test name
Test status
Simulation time 18156793871 ps
CPU time 74.11 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:06:19 PM PST 24
Peak memory 225764 kb
Host smart-f3602ec8-c148-4c63-aff5-b29af43b50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518439293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3518439293 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.980608567
Short name T406
Test name
Test status
Simulation time 943897007 ps
CPU time 18.6 seconds
Started Jan 07 01:05:21 PM PST 24
Finished Jan 07 01:05:41 PM PST 24
Peak memory 234704 kb
Host smart-3932d219-f1ff-4a1f-a77c-d3193cfb9f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980608567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.980608567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3291951074
Short name T651
Test name
Test status
Simulation time 18200920253 ps
CPU time 725.72 seconds
Started Jan 07 01:04:53 PM PST 24
Finished Jan 07 01:16:59 PM PST 24
Peak memory 304852 kb
Host smart-eb5dd31a-dc3b-41c1-8723-7785a86354ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291951074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3291951074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.1100905720
Short name T195
Test name
Test status
Simulation time 5157599423 ps
CPU time 303.86 seconds
Started Jan 07 01:04:58 PM PST 24
Finished Jan 07 01:10:03 PM PST 24
Peak memory 248032 kb
Host smart-1769a57e-d4c4-4301-aec1-33e59bfae4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100905720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1100905720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_stress_all.401995763
Short name T824
Test name
Test status
Simulation time 6521234762 ps
CPU time 120.03 seconds
Started Jan 07 01:05:31 PM PST 24
Finished Jan 07 01:07:31 PM PST 24
Peak memory 250824 kb
Host smart-34ce4281-b5c2-4be9-8ce6-daa3c06bdb0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=401995763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.401995763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_stress_all_with_rand_reset.383561338
Short name T897
Test name
Test status
Simulation time 51713819286 ps
CPU time 1343.19 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 01:27:30 PM PST 24
Peak memory 347104 kb
Host smart-f2cea98f-f922-4b97-b475-89d42079114e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383561338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.383561338 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2529231683
Short name T763
Test name
Test status
Simulation time 81984276 ps
CPU time 3.9 seconds
Started Jan 07 01:05:09 PM PST 24
Finished Jan 07 01:05:14 PM PST 24
Peak memory 215744 kb
Host smart-660be58a-9e20-4734-878e-900b1447c525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529231683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2529231683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3495330913
Short name T579
Test name
Test status
Simulation time 74544804 ps
CPU time 4.17 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 215696 kb
Host smart-32a0cec3-c9be-406b-a956-613f1b175681
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495330913 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3495330913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.3357697127
Short name T184
Test name
Test status
Simulation time 102255312361 ps
CPU time 1833.49 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:35:31 PM PST 24
Peak memory 396360 kb
Host smart-ee128906-0a96-4e3c-a8f7-051abbc6b9c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3357697127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3357697127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.533701464
Short name T764
Test name
Test status
Simulation time 237916927035 ps
CPU time 1639.87 seconds
Started Jan 07 01:05:00 PM PST 24
Finished Jan 07 01:32:22 PM PST 24
Peak memory 364528 kb
Host smart-c4f57caa-fe47-444e-9316-b2abe4410afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=533701464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.533701464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.4220438759
Short name T514
Test name
Test status
Simulation time 55001297223 ps
CPU time 1141.23 seconds
Started Jan 07 01:05:04 PM PST 24
Finished Jan 07 01:24:07 PM PST 24
Peak memory 336592 kb
Host smart-425c3a2f-f3e9-42e0-8268-b03a9e17984e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4220438759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.4220438759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.1997364438
Short name T755
Test name
Test status
Simulation time 1017134267155 ps
CPU time 4219.62 seconds
Started Jan 07 01:04:54 PM PST 24
Finished Jan 07 02:15:15 PM PST 24
Peak memory 649392 kb
Host smart-83a5a3c9-ac6d-436e-a7f4-6d41defd4bfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1997364438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1997364438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.2653557391
Short name T680
Test name
Test status
Simulation time 189728689628 ps
CPU time 3940.16 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 02:10:48 PM PST 24
Peak memory 567068 kb
Host smart-bdf15f19-68f3-49a6-a431-9b6193892567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2653557391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2653557391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.29137001
Short name T802
Test name
Test status
Simulation time 15954668 ps
CPU time 0.84 seconds
Started Jan 07 01:05:16 PM PST 24
Finished Jan 07 01:05:18 PM PST 24
Peak memory 205036 kb
Host smart-a8f9d836-560c-49f7-a93d-fe0f4f4e8336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.29137001 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.1744907747
Short name T654
Test name
Test status
Simulation time 11285399873 ps
CPU time 202.5 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:08:59 PM PST 24
Peak memory 238672 kb
Host smart-dec2d7ee-c61b-4543-bdce-3ee631a7d9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744907747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1744907747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2246775857
Short name T421
Test name
Test status
Simulation time 94009902127 ps
CPU time 383.31 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:11:43 PM PST 24
Peak memory 229576 kb
Host smart-315127da-b2c3-4e42-92d2-6846e3735c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246775857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2246775857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.959858166
Short name T532
Test name
Test status
Simulation time 3200396248 ps
CPU time 56.5 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 224372 kb
Host smart-14d02c51-767c-4e97-a951-b88b0f5a84a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959858166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.959858166 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2497773803
Short name T299
Test name
Test status
Simulation time 389145654 ps
CPU time 8.25 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:06:00 PM PST 24
Peak memory 220560 kb
Host smart-6d7fce46-4d2e-4a1d-912f-d5aa188dc033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497773803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2497773803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.2376355353
Short name T783
Test name
Test status
Simulation time 1968905871 ps
CPU time 3.53 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:05:40 PM PST 24
Peak memory 207292 kb
Host smart-33455259-2079-4dd2-af93-1dc235fe0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376355353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2376355353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1467167388
Short name T644
Test name
Test status
Simulation time 799722980 ps
CPU time 16.31 seconds
Started Jan 07 01:05:21 PM PST 24
Finished Jan 07 01:05:39 PM PST 24
Peak memory 226360 kb
Host smart-c8898819-8d22-4310-8a5e-dd270b892056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467167388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1467167388 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.3259326430
Short name T716
Test name
Test status
Simulation time 12828086870 ps
CPU time 998.85 seconds
Started Jan 07 01:05:27 PM PST 24
Finished Jan 07 01:22:07 PM PST 24
Peak memory 331648 kb
Host smart-df0060e3-909b-441a-a036-25d4b381356d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259326430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.3259326430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.2839714936
Short name T713
Test name
Test status
Simulation time 915820159 ps
CPU time 58.96 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:06:43 PM PST 24
Peak memory 225124 kb
Host smart-ffb114e0-d691-461e-91b9-288532887b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839714936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2839714936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2473958324
Short name T316
Test name
Test status
Simulation time 1988518616 ps
CPU time 31.26 seconds
Started Jan 07 01:05:15 PM PST 24
Finished Jan 07 01:05:47 PM PST 24
Peak memory 218120 kb
Host smart-deee74e2-9745-42a3-8bed-95d31e666371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473958324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2473958324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.4028461079
Short name T813
Test name
Test status
Simulation time 1710460181 ps
CPU time 96.98 seconds
Started Jan 07 01:05:08 PM PST 24
Finished Jan 07 01:06:46 PM PST 24
Peak memory 240324 kb
Host smart-e60fd916-bfe1-467a-a53a-9a51171c7e73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4028461079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.4028461079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1497131144
Short name T336
Test name
Test status
Simulation time 260482356 ps
CPU time 5.1 seconds
Started Jan 07 01:05:05 PM PST 24
Finished Jan 07 01:05:11 PM PST 24
Peak memory 208760 kb
Host smart-72c1e62a-d805-40a6-95c6-c6e055bcb4dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497131144 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1497131144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.1546609335
Short name T314
Test name
Test status
Simulation time 222858632 ps
CPU time 4.6 seconds
Started Jan 07 01:05:08 PM PST 24
Finished Jan 07 01:05:14 PM PST 24
Peak memory 215632 kb
Host smart-374a112c-7c48-4df1-9a82-f2cf06829954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546609335 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.1546609335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3977300861
Short name T197
Test name
Test status
Simulation time 95219338240 ps
CPU time 1802.68 seconds
Started Jan 07 01:04:59 PM PST 24
Finished Jan 07 01:35:04 PM PST 24
Peak memory 374076 kb
Host smart-d1f31a13-cc0f-43ec-9e28-d446393c6cf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3977300861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3977300861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1075899535
Short name T922
Test name
Test status
Simulation time 143609587944 ps
CPU time 1334.34 seconds
Started Jan 07 01:05:13 PM PST 24
Finished Jan 07 01:27:29 PM PST 24
Peak memory 330160 kb
Host smart-09f08835-3b21-499e-8266-1bcfe783100e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1075899535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1075899535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.387944039
Short name T182
Test name
Test status
Simulation time 64965461365 ps
CPU time 867.1 seconds
Started Jan 07 01:05:05 PM PST 24
Finished Jan 07 01:19:33 PM PST 24
Peak memory 293628 kb
Host smart-b97ad694-522b-4e3e-a381-e9f6419604c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=387944039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.387944039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.423575407
Short name T667
Test name
Test status
Simulation time 745312610283 ps
CPU time 4357.66 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 02:18:36 PM PST 24
Peak memory 559340 kb
Host smart-925f0546-b1e2-40f7-9c68-e79b1a92fcee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=423575407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.423575407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.667620824
Short name T32
Test name
Test status
Simulation time 97568061 ps
CPU time 0.74 seconds
Started Jan 07 01:05:32 PM PST 24
Finished Jan 07 01:05:34 PM PST 24
Peak memory 205224 kb
Host smart-b7753a43-835a-4649-b929-fda61ed43794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667620824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.667620824 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.2022159591
Short name T567
Test name
Test status
Simulation time 559675843 ps
CPU time 22.24 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:05:41 PM PST 24
Peak memory 223888 kb
Host smart-1a7fee68-5e27-4730-810a-81a8786fdc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022159591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2022159591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.3698426005
Short name T820
Test name
Test status
Simulation time 3315804270 ps
CPU time 96.15 seconds
Started Jan 07 01:05:35 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 221864 kb
Host smart-7971b7ac-19ec-40b7-a9cf-c0fda15c4741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698426005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3698426005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_error.932118331
Short name T679
Test name
Test status
Simulation time 65597987546 ps
CPU time 311.37 seconds
Started Jan 07 01:05:26 PM PST 24
Finished Jan 07 01:10:38 PM PST 24
Peak memory 255764 kb
Host smart-36668a82-4bb5-42db-a013-7235de1dc201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932118331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.932118331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.3934252305
Short name T23
Test name
Test status
Simulation time 1567883813 ps
CPU time 4.52 seconds
Started Jan 07 01:05:09 PM PST 24
Finished Jan 07 01:05:15 PM PST 24
Peak memory 207308 kb
Host smart-36c55723-2d29-4c70-b3e9-460b0dd48ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934252305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3934252305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.4183804192
Short name T524
Test name
Test status
Simulation time 107939912861 ps
CPU time 510.99 seconds
Started Jan 07 01:05:19 PM PST 24
Finished Jan 07 01:13:51 PM PST 24
Peak memory 263884 kb
Host smart-7ca6e3bc-3916-4fcc-90a1-f2abbaea05dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183804192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.4183804192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1650934433
Short name T864
Test name
Test status
Simulation time 69906029742 ps
CPU time 339.06 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:10:50 PM PST 24
Peak memory 246436 kb
Host smart-bf0f3d42-d888-4146-b04f-30b88cb500ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650934433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1650934433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3211657097
Short name T829
Test name
Test status
Simulation time 940574688 ps
CPU time 45.95 seconds
Started Jan 07 01:05:11 PM PST 24
Finished Jan 07 01:05:58 PM PST 24
Peak memory 218824 kb
Host smart-f1847312-6276-4bef-b47c-46b3b04ba375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211657097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3211657097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.3553125967
Short name T912
Test name
Test status
Simulation time 255970737 ps
CPU time 5.09 seconds
Started Jan 07 01:05:16 PM PST 24
Finished Jan 07 01:05:22 PM PST 24
Peak memory 208916 kb
Host smart-14aa968c-2044-4d8f-9d44-9122457e4015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553125967 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.3553125967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3909783462
Short name T556
Test name
Test status
Simulation time 727183899 ps
CPU time 4.38 seconds
Started Jan 07 01:05:08 PM PST 24
Finished Jan 07 01:05:14 PM PST 24
Peak memory 215644 kb
Host smart-55cfef9e-44f0-4b9f-96e2-66ec0967e6c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909783462 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3909783462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.1569649029
Short name T710
Test name
Test status
Simulation time 65736115437 ps
CPU time 1722.25 seconds
Started Jan 07 01:05:35 PM PST 24
Finished Jan 07 01:34:18 PM PST 24
Peak memory 392432 kb
Host smart-c4a289f2-4bc7-4655-b097-d2d5a52d5b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1569649029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1569649029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1107375559
Short name T447
Test name
Test status
Simulation time 67027187249 ps
CPU time 880.68 seconds
Started Jan 07 01:05:09 PM PST 24
Finished Jan 07 01:19:51 PM PST 24
Peak memory 292088 kb
Host smart-2a073b74-123d-40b5-bb43-d0902010cbcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1107375559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1107375559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.4186530312
Short name T744
Test name
Test status
Simulation time 203675360291 ps
CPU time 4117.36 seconds
Started Jan 07 01:05:12 PM PST 24
Finished Jan 07 02:13:51 PM PST 24
Peak memory 651912 kb
Host smart-15db45a0-b9b7-4075-9ee1-bf1e60e137c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4186530312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.4186530312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.879622677
Short name T334
Test name
Test status
Simulation time 204298793809 ps
CPU time 3216.62 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:58:48 PM PST 24
Peak memory 553720 kb
Host smart-c5e68277-ac1a-42e6-9d57-f07fdc086865
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=879622677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.879622677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.519563884
Short name T736
Test name
Test status
Simulation time 57272803 ps
CPU time 0.77 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:05:48 PM PST 24
Peak memory 205212 kb
Host smart-0e028c7e-a3a7-47c2-97d5-b726b6570afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519563884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.519563884 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1414939749
Short name T771
Test name
Test status
Simulation time 5179655826 ps
CPU time 94.61 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:07:17 PM PST 24
Peak memory 228336 kb
Host smart-b53f9eba-5140-4fb8-b2e4-77b2ad4c8c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414939749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1414939749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3066537125
Short name T226
Test name
Test status
Simulation time 80460884921 ps
CPU time 408.74 seconds
Started Jan 07 01:05:07 PM PST 24
Finished Jan 07 01:11:56 PM PST 24
Peak memory 228228 kb
Host smart-f467fdbe-0c59-4151-9ad8-650cc5e1eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066537125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3066537125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2650693094
Short name T15
Test name
Test status
Simulation time 1705493434 ps
CPU time 24.16 seconds
Started Jan 07 01:05:32 PM PST 24
Finished Jan 07 01:05:56 PM PST 24
Peak memory 220012 kb
Host smart-4e957e39-1da8-4039-ae54-b27b2195c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650693094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2650693094 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.4248591904
Short name T29
Test name
Test status
Simulation time 4748957039 ps
CPU time 70.48 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:06:59 PM PST 24
Peak memory 240208 kb
Host smart-a318ee39-93f4-4efe-b546-3180d8dc6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248591904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.4248591904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3930818444
Short name T495
Test name
Test status
Simulation time 88723179328 ps
CPU time 1508.8 seconds
Started Jan 07 01:05:00 PM PST 24
Finished Jan 07 01:30:11 PM PST 24
Peak memory 386492 kb
Host smart-a86ef9b1-b2d8-4bc4-9ac6-209581f7f8ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930818444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3930818444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.2675769910
Short name T784
Test name
Test status
Simulation time 40570538312 ps
CPU time 302.65 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:10:22 PM PST 24
Peak memory 245288 kb
Host smart-792b2eb7-62e7-4306-af5c-c9e75709bb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675769910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2675769910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1165274225
Short name T782
Test name
Test status
Simulation time 1684073889 ps
CPU time 4.48 seconds
Started Jan 07 01:05:33 PM PST 24
Finished Jan 07 01:05:38 PM PST 24
Peak memory 219056 kb
Host smart-b664625b-5f77-4682-848e-fe44f1b8ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165274225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1165274225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.946378150
Short name T462
Test name
Test status
Simulation time 31648139355 ps
CPU time 299.88 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:10:41 PM PST 24
Peak memory 282584 kb
Host smart-049da14f-05a7-4065-b8e1-808b6aa16871
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=946378150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.946378150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_stress_all_with_rand_reset.2165797344
Short name T381
Test name
Test status
Simulation time 266869453307 ps
CPU time 2210.81 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:42:37 PM PST 24
Peak memory 404548 kb
Host smart-1372f8c8-4765-42a1-9132-1aa23e249685
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165797344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.2165797344 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.599392051
Short name T424
Test name
Test status
Simulation time 389069768 ps
CPU time 3.62 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:56 PM PST 24
Peak memory 215708 kb
Host smart-7c561e87-b2aa-4bea-a492-f90d8fcd8a1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599392051 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.599392051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.4088031502
Short name T853
Test name
Test status
Simulation time 710271447 ps
CPU time 4.04 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:05:24 PM PST 24
Peak memory 215624 kb
Host smart-0ae30ced-6a65-454a-adaa-c3e880b67683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088031502 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.4088031502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3736466071
Short name T685
Test name
Test status
Simulation time 434981351834 ps
CPU time 1961.53 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:38:35 PM PST 24
Peak memory 378924 kb
Host smart-27657cca-5c28-4545-8269-9e72bc94d932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3736466071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3736466071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1998146218
Short name T898
Test name
Test status
Simulation time 128199449252 ps
CPU time 1445.58 seconds
Started Jan 07 01:05:15 PM PST 24
Finished Jan 07 01:29:21 PM PST 24
Peak memory 377520 kb
Host smart-078f093e-bb17-47f5-b6ba-420693b58c61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1998146218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1998146218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3446665029
Short name T263
Test name
Test status
Simulation time 56900372433 ps
CPU time 1135.97 seconds
Started Jan 07 01:05:14 PM PST 24
Finished Jan 07 01:24:11 PM PST 24
Peak memory 335300 kb
Host smart-b57c87d0-953e-4602-a3e0-1f0b75548bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3446665029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3446665029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.98110015
Short name T490
Test name
Test status
Simulation time 127455960781 ps
CPU time 962 seconds
Started Jan 07 01:05:07 PM PST 24
Finished Jan 07 01:21:11 PM PST 24
Peak memory 298020 kb
Host smart-7595cc00-43a1-491b-8273-8dcd4122996b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=98110015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.98110015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.3231790236
Short name T401
Test name
Test status
Simulation time 682778051859 ps
CPU time 4541.11 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 02:21:23 PM PST 24
Peak memory 643248 kb
Host smart-f6ddf3f9-a4ab-473e-86c4-fc7d50470e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3231790236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3231790236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3215458221
Short name T754
Test name
Test status
Simulation time 44430937439 ps
CPU time 3263.97 seconds
Started Jan 07 01:05:34 PM PST 24
Finished Jan 07 01:59:59 PM PST 24
Peak memory 549396 kb
Host smart-72dac64e-0478-4497-81ab-91412d48813f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3215458221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3215458221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_app.4232298667
Short name T449
Test name
Test status
Simulation time 1775297011 ps
CPU time 19.36 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 224916 kb
Host smart-79a114f2-7909-4639-8fc0-f8bdeb502197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232298667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.4232298667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2186715428
Short name T903
Test name
Test status
Simulation time 4706414755 ps
CPU time 109.8 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 01:05:58 PM PST 24
Peak memory 222588 kb
Host smart-ad1c212f-ce42-44ae-940e-86545b81cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186715428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2186715428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.1593110369
Short name T53
Test name
Test status
Simulation time 31514370809 ps
CPU time 291.18 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:09:31 PM PST 24
Peak memory 246708 kb
Host smart-c1176a43-6db9-427f-8d02-d86f638d78ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593110369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1593110369 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3433547486
Short name T510
Test name
Test status
Simulation time 53519525 ps
CPU time 1.33 seconds
Started Jan 07 01:04:25 PM PST 24
Finished Jan 07 01:04:29 PM PST 24
Peak memory 216656 kb
Host smart-9dc06459-a431-46ad-8173-a50fa2098c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433547486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3433547486 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2699237945
Short name T243
Test name
Test status
Simulation time 47362926692 ps
CPU time 294.54 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:09:04 PM PST 24
Peak memory 244604 kb
Host smart-8e55ec0b-f0c7-4d3c-a599-73c1018f9d68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699237945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2699237945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1324154169
Short name T27
Test name
Test status
Simulation time 9849442865 ps
CPU time 238.42 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:08:40 PM PST 24
Peak memory 242016 kb
Host smart-05254f5d-48c0-402b-8d5f-361b49a6638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324154169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1324154169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1319234694
Short name T11
Test name
Test status
Simulation time 9263032732 ps
CPU time 48.1 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:05:28 PM PST 24
Peak memory 248676 kb
Host smart-1b98413e-a244-4966-bcf2-1d102c15db84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319234694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1319234694 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.340214127
Short name T852
Test name
Test status
Simulation time 4071788857 ps
CPU time 74.61 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:05:26 PM PST 24
Peak memory 226484 kb
Host smart-e2239d62-e7a6-47fb-a03c-d0fa44bef8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340214127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.340214127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2794677373
Short name T678
Test name
Test status
Simulation time 7659428842 ps
CPU time 39.65 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:05:24 PM PST 24
Peak memory 232320 kb
Host smart-b2c21fa4-1c55-438f-bcc8-92b66a0b03df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2794677373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2794677373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3565645311
Short name T610
Test name
Test status
Simulation time 67518563016 ps
CPU time 1593.79 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:31:17 PM PST 24
Peak memory 347888 kb
Host smart-ac321b7a-4f0b-4677-ba08-f0d64c1415c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565645311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3565645311 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1787623788
Short name T315
Test name
Test status
Simulation time 245004726 ps
CPU time 4.58 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 208760 kb
Host smart-c1b70b21-a41d-4f36-8711-711fe2b36e25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787623788 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1787623788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.229346472
Short name T562
Test name
Test status
Simulation time 130183326 ps
CPU time 3.97 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:27 PM PST 24
Peak memory 215672 kb
Host smart-9677a803-d5fc-49a6-aff6-73a7dbc39cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229346472 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.kmac_test_vectors_kmac_xof.229346472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2789704424
Short name T670
Test name
Test status
Simulation time 346515925038 ps
CPU time 1880.17 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:35:25 PM PST 24
Peak memory 379168 kb
Host smart-f133bf80-84e3-4b5c-bf7f-024d674058ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2789704424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2789704424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1659514515
Short name T761
Test name
Test status
Simulation time 18944150174 ps
CPU time 1508.8 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:29:11 PM PST 24
Peak memory 390428 kb
Host smart-a8ef9d3b-078c-4c2a-95d3-e9b86ec2bda6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1659514515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1659514515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.4129248834
Short name T188
Test name
Test status
Simulation time 70589258190 ps
CPU time 1395.83 seconds
Started Jan 07 01:04:12 PM PST 24
Finished Jan 07 01:27:30 PM PST 24
Peak memory 333064 kb
Host smart-0331d270-7205-42f3-836d-32c7d88e2855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4129248834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.4129248834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1524914024
Short name T338
Test name
Test status
Simulation time 33927595960 ps
CPU time 747.13 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:16:49 PM PST 24
Peak memory 294484 kb
Host smart-05951e46-3629-4344-9f0b-91f91f35168b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1524914024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1524914024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3183329965
Short name T777
Test name
Test status
Simulation time 211376084152 ps
CPU time 4037.54 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 02:11:40 PM PST 24
Peak memory 647284 kb
Host smart-73a46d45-fd70-4981-81f7-1359cb5f3b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3183329965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3183329965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.3687167502
Short name T167
Test name
Test status
Simulation time 75435566482 ps
CPU time 3293.09 seconds
Started Jan 07 01:04:20 PM PST 24
Finished Jan 07 01:59:17 PM PST 24
Peak memory 556376 kb
Host smart-d8100327-18d8-4db2-bc70-a1a345861731
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3687167502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3687167502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3507993306
Short name T239
Test name
Test status
Simulation time 66353906 ps
CPU time 0.81 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 205232 kb
Host smart-e13093e4-df66-4c5f-b4f5-9d395fdd814d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507993306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3507993306 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.4015482385
Short name T765
Test name
Test status
Simulation time 7471291603 ps
CPU time 178.49 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:09:09 PM PST 24
Peak memory 237040 kb
Host smart-09081e64-c2a0-481e-b68a-45ec807d4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015482385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.4015482385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.863542496
Short name T836
Test name
Test status
Simulation time 4496078204 ps
CPU time 33.3 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:06:23 PM PST 24
Peak memory 223952 kb
Host smart-813e0bab-c6ac-452d-b0a0-b932987ac34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863542496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.863542496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_key_error.2948392712
Short name T21
Test name
Test status
Simulation time 1900403537 ps
CPU time 3.01 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:06:16 PM PST 24
Peak memory 207332 kb
Host smart-98cfc26e-b41f-402f-8bf8-c51641d76c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948392712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2948392712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.2252063342
Short name T394
Test name
Test status
Simulation time 5909844984 ps
CPU time 243.57 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:09:54 PM PST 24
Peak memory 244128 kb
Host smart-6b1d6f58-6ae7-424f-8e65-1714dc05119f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252063342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.2252063342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.4268720882
Short name T262
Test name
Test status
Simulation time 30526058091 ps
CPU time 191.96 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:09:14 PM PST 24
Peak memory 237984 kb
Host smart-a840b553-b54c-49ec-9f1b-a7683ab84d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268720882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.4268720882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.1270359904
Short name T833
Test name
Test status
Simulation time 13435486601 ps
CPU time 33.07 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:06:24 PM PST 24
Peak memory 216156 kb
Host smart-5d40c358-6916-46b9-b9ac-ff33d7c476fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270359904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1270359904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.546872160
Short name T440
Test name
Test status
Simulation time 20964779009 ps
CPU time 1505.59 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:31:18 PM PST 24
Peak memory 403848 kb
Host smart-49290bf3-68e1-47f7-b126-e47bba91ba33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=546872160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.546872160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_stress_all_with_rand_reset.1805366499
Short name T128
Test name
Test status
Simulation time 97562183163 ps
CPU time 1210.43 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:26:19 PM PST 24
Peak memory 305388 kb
Host smart-e222c380-8635-455e-a265-cd9880fa53c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805366499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.1805366499 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.324980447
Short name T843
Test name
Test status
Simulation time 18964988806 ps
CPU time 1388.46 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:29:15 PM PST 24
Peak memory 371604 kb
Host smart-5a8f93c1-ac79-4b6c-9542-817639798d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=324980447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.324980447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.749567366
Short name T170
Test name
Test status
Simulation time 92684588307 ps
CPU time 1203.15 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:25:50 PM PST 24
Peak memory 339560 kb
Host smart-f44fe5ed-78be-4411-a2ee-f78c4b256d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=749567366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.749567366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.4143646180
Short name T250
Test name
Test status
Simulation time 190954495963 ps
CPU time 993.18 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:22:39 PM PST 24
Peak memory 290568 kb
Host smart-88635182-1eae-4a68-b4b9-b6d92ac993e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4143646180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.4143646180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1160614253
Short name T162
Test name
Test status
Simulation time 51953206156 ps
CPU time 3974.89 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 02:12:14 PM PST 24
Peak memory 640680 kb
Host smart-df4c5712-1821-423c-9113-a44b7a89e674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1160614253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1160614253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.3394413510
Short name T208
Test name
Test status
Simulation time 44018424296 ps
CPU time 3392.61 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 02:02:20 PM PST 24
Peak memory 567564 kb
Host smart-a5915116-0b58-48ae-a5e9-0911f73eead8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3394413510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3394413510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1185158903
Short name T497
Test name
Test status
Simulation time 54730802 ps
CPU time 0.76 seconds
Started Jan 07 01:05:11 PM PST 24
Finished Jan 07 01:05:13 PM PST 24
Peak memory 205160 kb
Host smart-bc54fd5e-43b4-485c-9a61-94f90b7adb51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185158903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1185158903 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_error.725665908
Short name T146
Test name
Test status
Simulation time 5327507418 ps
CPU time 93.74 seconds
Started Jan 07 01:05:11 PM PST 24
Finished Jan 07 01:06:46 PM PST 24
Peak memory 248460 kb
Host smart-01f1f30a-f86d-43d3-8d23-94b1f9e33a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725665908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.725665908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.3543719709
Short name T866
Test name
Test status
Simulation time 1111455888 ps
CPU time 3.01 seconds
Started Jan 07 01:05:13 PM PST 24
Finished Jan 07 01:05:17 PM PST 24
Peak memory 207148 kb
Host smart-e2c35a73-f50b-4cab-baa3-5c2052ecdef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543719709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3543719709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2743384908
Short name T657
Test name
Test status
Simulation time 275037067 ps
CPU time 1.19 seconds
Started Jan 07 01:05:03 PM PST 24
Finished Jan 07 01:05:06 PM PST 24
Peak memory 215616 kb
Host smart-d8416d4f-24c1-4ae0-81d4-30e7bc44b300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743384908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2743384908 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.2835541906
Short name T571
Test name
Test status
Simulation time 275083696796 ps
CPU time 2008.17 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:39:36 PM PST 24
Peak memory 418756 kb
Host smart-8782b5b8-df32-4a46-96fa-2dae6df54ea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835541906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.2835541906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1860892405
Short name T916
Test name
Test status
Simulation time 79903707911 ps
CPU time 377.62 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:12:09 PM PST 24
Peak memory 249624 kb
Host smart-991a0fdb-a64e-4eea-a1af-9bbf87679161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860892405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1860892405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3252017637
Short name T592
Test name
Test status
Simulation time 3535310608 ps
CPU time 54.59 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:07:06 PM PST 24
Peak memory 223864 kb
Host smart-c2df1047-b346-47c9-93fc-3a941de438a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252017637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3252017637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.2144720416
Short name T284
Test name
Test status
Simulation time 43566144830 ps
CPU time 253.56 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 01:09:20 PM PST 24
Peak memory 262600 kb
Host smart-f02aa723-e426-4ea8-95d1-46ab624d9783
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2144720416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2144720416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2152279814
Short name T529
Test name
Test status
Simulation time 598866102 ps
CPU time 4.03 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:06:25 PM PST 24
Peak memory 215692 kb
Host smart-0ba2d14b-8e79-4486-b50e-de8181e22c9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152279814 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2152279814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.252780445
Short name T360
Test name
Test status
Simulation time 984273265 ps
CPU time 4.69 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:04 PM PST 24
Peak memory 215680 kb
Host smart-7c102804-5848-42ec-9ce8-290f666e52b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252780445 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.kmac_test_vectors_kmac_xof.252780445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.2549531763
Short name T414
Test name
Test status
Simulation time 108611328182 ps
CPU time 1876.22 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:37:31 PM PST 24
Peak memory 397936 kb
Host smart-65404480-b70d-4980-9821-a7e61c67271c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2549531763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.2549531763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.650988080
Short name T177
Test name
Test status
Simulation time 380499141179 ps
CPU time 1755.91 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:35:10 PM PST 24
Peak memory 372784 kb
Host smart-3d58df72-da66-405c-903d-39adbbe70f08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=650988080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.650988080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.3516038289
Short name T662
Test name
Test status
Simulation time 55869973387 ps
CPU time 1114.08 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:24:40 PM PST 24
Peak memory 330560 kb
Host smart-619595f0-df20-41a5-9013-75d8e1fd6721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3516038289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3516038289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.3752845228
Short name T480
Test name
Test status
Simulation time 19193710929 ps
CPU time 767.69 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:18:39 PM PST 24
Peak memory 296660 kb
Host smart-d7caff80-d94f-4a4e-8816-68e94717788b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3752845228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.3752845228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.4245095382
Short name T607
Test name
Test status
Simulation time 179185080352 ps
CPU time 4544.52 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 02:21:51 PM PST 24
Peak memory 649516 kb
Host smart-0d8118a7-1092-45f0-b9bf-a963378b4eda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4245095382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.4245095382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3526231354
Short name T403
Test name
Test status
Simulation time 45461700577 ps
CPU time 3389.01 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 02:02:38 PM PST 24
Peak memory 567760 kb
Host smart-2a1420f4-61ea-4318-9039-77712b7b2eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3526231354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3526231354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1427558723
Short name T272
Test name
Test status
Simulation time 12655761 ps
CPU time 0.77 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:05:48 PM PST 24
Peak memory 205144 kb
Host smart-b4e8ae27-90e5-426a-8cfd-f2294e77a740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427558723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1427558723 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.1517682555
Short name T739
Test name
Test status
Simulation time 54771425411 ps
CPU time 200.78 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:09:30 PM PST 24
Peak memory 237044 kb
Host smart-015df507-64fa-4872-9768-d932c015d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517682555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1517682555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.2090599430
Short name T846
Test name
Test status
Simulation time 4725725228 ps
CPU time 100.32 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:07:22 PM PST 24
Peak memory 221700 kb
Host smart-b1164871-1497-4a54-a7d6-c5211eedf366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090599430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2090599430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2430337270
Short name T248
Test name
Test status
Simulation time 8891651929 ps
CPU time 196.91 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:08:59 PM PST 24
Peak memory 240436 kb
Host smart-8f80cda6-7c3b-4689-8b06-a69f417a5d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430337270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2430337270 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.99079021
Short name T580
Test name
Test status
Simulation time 3796574480 ps
CPU time 38.46 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:06:26 PM PST 24
Peak memory 232188 kb
Host smart-9d377f57-580e-4c8d-88a5-d2c21b727e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99079021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.99079021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.3402819150
Short name T509
Test name
Test status
Simulation time 1772575398 ps
CPU time 4.03 seconds
Started Jan 07 01:05:48 PM PST 24
Finished Jan 07 01:05:53 PM PST 24
Peak memory 215472 kb
Host smart-559dda70-a0e7-40c3-8972-65102e7b177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402819150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3402819150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.3609106307
Short name T385
Test name
Test status
Simulation time 344230834908 ps
CPU time 1573.85 seconds
Started Jan 07 01:05:10 PM PST 24
Finished Jan 07 01:31:24 PM PST 24
Peak memory 356416 kb
Host smart-abc382e1-4c50-41e5-927f-2c0ff8c7d2ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609106307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.3609106307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3836060448
Short name T253
Test name
Test status
Simulation time 8537690577 ps
CPU time 42.38 seconds
Started Jan 07 01:05:38 PM PST 24
Finished Jan 07 01:06:21 PM PST 24
Peak memory 223712 kb
Host smart-d0c23a78-b64c-4ab0-a000-9b9cbe7478bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836060448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3836060448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1367083415
Short name T815
Test name
Test status
Simulation time 348044174 ps
CPU time 6.78 seconds
Started Jan 07 01:05:14 PM PST 24
Finished Jan 07 01:05:21 PM PST 24
Peak memory 218596 kb
Host smart-b4ca5e19-e443-46d5-91c0-1215249f1cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367083415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1367083415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.640441151
Short name T323
Test name
Test status
Simulation time 66637797827 ps
CPU time 449.79 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:13:15 PM PST 24
Peak memory 274016 kb
Host smart-ed10a4ad-1369-420c-9e91-be6a93a05f5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=640441151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.640441151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_stress_all_with_rand_reset.3224092067
Short name T372
Test name
Test status
Simulation time 11114382980 ps
CPU time 180.02 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:08:46 PM PST 24
Peak memory 254968 kb
Host smart-d731f241-0cfc-4435-93ae-be07ce6529cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224092067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all_with_rand_reset.3224092067 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2604265977
Short name T300
Test name
Test status
Simulation time 65517057 ps
CPU time 4.1 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:06 PM PST 24
Peak memory 215752 kb
Host smart-133dbb38-d845-4e5c-a43d-9a486b00e7e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604265977 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2604265977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.1421541552
Short name T13
Test name
Test status
Simulation time 66295436 ps
CPU time 3.76 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:56 PM PST 24
Peak memory 215716 kb
Host smart-a1a98dca-e887-43d1-af4f-6af9cf5efeb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421541552 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.1421541552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.1553860807
Short name T923
Test name
Test status
Simulation time 174675661924 ps
CPU time 1564.24 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:31:45 PM PST 24
Peak memory 399800 kb
Host smart-66cd8ba5-4ce3-4816-8b5b-0ff258f88f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1553860807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.1553860807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3770499763
Short name T353
Test name
Test status
Simulation time 47830244611 ps
CPU time 1301.3 seconds
Started Jan 07 01:05:30 PM PST 24
Finished Jan 07 01:27:12 PM PST 24
Peak memory 328932 kb
Host smart-857b1615-73a3-4889-87ba-b7da31a9539c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3770499763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3770499763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3128170659
Short name T752
Test name
Test status
Simulation time 194025424423 ps
CPU time 924.62 seconds
Started Jan 07 01:05:38 PM PST 24
Finished Jan 07 01:21:03 PM PST 24
Peak memory 292924 kb
Host smart-b39514fe-e7bd-4113-9eca-0790f4961407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3128170659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3128170659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3424780454
Short name T740
Test name
Test status
Simulation time 175193119130 ps
CPU time 4500.16 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 02:20:53 PM PST 24
Peak memory 648372 kb
Host smart-23c07436-2926-42eb-be45-deec89c3bfbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3424780454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3424780454 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1288464665
Short name T370
Test name
Test status
Simulation time 151415557995 ps
CPU time 3804.44 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 02:09:34 PM PST 24
Peak memory 560812 kb
Host smart-1d0d5229-31e1-446f-974c-b095ac0b15b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1288464665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1288464665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.1976838343
Short name T770
Test name
Test status
Simulation time 14421828 ps
CPU time 0.75 seconds
Started Jan 07 01:05:14 PM PST 24
Finished Jan 07 01:05:16 PM PST 24
Peak memory 205220 kb
Host smart-167689f7-4921-482c-9ff1-f517d09afcda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976838343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1976838343 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.983716
Short name T264
Test name
Test status
Simulation time 1583283438 ps
CPU time 19.01 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:17 PM PST 24
Peak memory 223932 kb
Host smart-83bba099-e65b-46da-9db2-3b6f4a8c835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.983716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1416702584
Short name T819
Test name
Test status
Simulation time 21663224347 ps
CPU time 350.25 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:11:43 PM PST 24
Peak memory 247016 kb
Host smart-ee7e29f1-0e66-41ce-8a83-251c8fc00b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416702584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1416702584 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.2017299441
Short name T30
Test name
Test status
Simulation time 2481902189 ps
CPU time 171.65 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:08:44 PM PST 24
Peak memory 249280 kb
Host smart-7b84da06-1aca-4b42-a494-6e20d53c38a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017299441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2017299441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.46112694
Short name T73
Test name
Test status
Simulation time 77558137595 ps
CPU time 645.32 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 291676 kb
Host smart-213fe770-e75b-40f0-8917-d0a597e287f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46112694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and
_output.46112694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1124482013
Short name T869
Test name
Test status
Simulation time 25065116702 ps
CPU time 231.92 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:09:52 PM PST 24
Peak memory 237612 kb
Host smart-7163dc17-5e30-4f2f-944c-4dbbe864776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124482013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1124482013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.3557299209
Short name T665
Test name
Test status
Simulation time 3220108588 ps
CPU time 17.19 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 219004 kb
Host smart-7c7b9efc-f47a-4352-ab9b-ac6b10e03a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557299209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3557299209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3969984060
Short name T926
Test name
Test status
Simulation time 29333798601 ps
CPU time 210.32 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:09:20 PM PST 24
Peak memory 252144 kb
Host smart-b9b48b16-e781-4376-a7ae-8d4cf5cbeb20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3969984060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3969984060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_stress_all_with_rand_reset.531147724
Short name T127
Test name
Test status
Simulation time 67916078047 ps
CPU time 826.72 seconds
Started Jan 07 01:06:01 PM PST 24
Finished Jan 07 01:19:51 PM PST 24
Peak memory 255160 kb
Host smart-2f422196-2456-437c-8b13-1574d30cf98e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531147724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.531147724 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.885714776
Short name T554
Test name
Test status
Simulation time 342711148 ps
CPU time 4.52 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:06:11 PM PST 24
Peak memory 208724 kb
Host smart-7ec28d07-e3b6-46bf-be89-f55d2b98bc90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885714776 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.885714776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3120840389
Short name T928
Test name
Test status
Simulation time 898698610 ps
CPU time 4.92 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 215684 kb
Host smart-abbac1a7-0be5-447a-ac2e-010766b42ece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120840389 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3120840389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.293927687
Short name T46
Test name
Test status
Simulation time 18071043275 ps
CPU time 1409.3 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:29:28 PM PST 24
Peak memory 365900 kb
Host smart-c5e9a2fd-f845-4057-ad65-8cf9a44b2ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=293927687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.293927687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.447345326
Short name T797
Test name
Test status
Simulation time 13452811161 ps
CPU time 1145.93 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:25:08 PM PST 24
Peak memory 331340 kb
Host smart-57855a9d-b7cf-4369-ae6a-fe5c89404627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=447345326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.447345326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1894972486
Short name T619
Test name
Test status
Simulation time 45262003047 ps
CPU time 3363.12 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 02:02:01 PM PST 24
Peak memory 565072 kb
Host smart-e5c97942-1fb8-4282-9d14-e70e0f8e3c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1894972486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1894972486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2173886391
Short name T225
Test name
Test status
Simulation time 62235919 ps
CPU time 0.78 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:05:42 PM PST 24
Peak memory 205204 kb
Host smart-e84d6216-7ee7-4cb2-8ae3-f40e1a21fed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173886391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2173886391 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3517542991
Short name T745
Test name
Test status
Simulation time 1061599424 ps
CPU time 35.77 seconds
Started Jan 07 01:05:47 PM PST 24
Finished Jan 07 01:06:24 PM PST 24
Peak memory 221588 kb
Host smart-4ec01cb0-fad3-4038-a798-edc6a9a82758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517542991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3517542991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2746129310
Short name T261
Test name
Test status
Simulation time 27203899107 ps
CPU time 237.57 seconds
Started Jan 07 01:05:35 PM PST 24
Finished Jan 07 01:09:33 PM PST 24
Peak memory 244316 kb
Host smart-3dccc4d8-e829-4c4a-9bf0-c1717795179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746129310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2746129310 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.3225649670
Short name T330
Test name
Test status
Simulation time 4359739257 ps
CPU time 107.99 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:07:34 PM PST 24
Peak memory 239828 kb
Host smart-db6e6422-b53b-4092-8c5a-38e69f6194e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225649670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3225649670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2141184143
Short name T539
Test name
Test status
Simulation time 311534024 ps
CPU time 2.06 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 206784 kb
Host smart-a0b90135-b106-4539-8fe3-31ab381bd921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141184143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2141184143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.441539102
Short name T822
Test name
Test status
Simulation time 123845626 ps
CPU time 1.32 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:05:38 PM PST 24
Peak memory 216616 kb
Host smart-83ea23e0-d8e4-4206-8c78-affbf0a927da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441539102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.441539102 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2276543130
Short name T605
Test name
Test status
Simulation time 18385998807 ps
CPU time 1661.41 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:33:28 PM PST 24
Peak memory 398636 kb
Host smart-253b4d40-4875-4408-bfc7-fdd6de869c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276543130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2276543130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3008808591
Short name T304
Test name
Test status
Simulation time 16641296575 ps
CPU time 306.6 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:10:48 PM PST 24
Peak memory 244264 kb
Host smart-5b60cdc4-01c6-4150-b03d-a2352cf08384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008808591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3008808591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.1316775093
Short name T474
Test name
Test status
Simulation time 11287910167 ps
CPU time 42.41 seconds
Started Jan 07 01:05:13 PM PST 24
Finished Jan 07 01:05:57 PM PST 24
Peak memory 217460 kb
Host smart-e28f38dd-1ce4-4616-a7c4-1173778376f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316775093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1316775093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.518490209
Short name T397
Test name
Test status
Simulation time 14991891455 ps
CPU time 267.19 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:10:23 PM PST 24
Peak memory 254224 kb
Host smart-65219c09-90a2-4c44-8c40-4499cdce7dee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=518490209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.518490209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1398627959
Short name T781
Test name
Test status
Simulation time 730058243 ps
CPU time 4.56 seconds
Started Jan 07 01:05:17 PM PST 24
Finished Jan 07 01:05:23 PM PST 24
Peak memory 215608 kb
Host smart-2e841e4d-6b1b-42bd-b929-f7ecadff42a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398627959 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1398627959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.1593620055
Short name T308
Test name
Test status
Simulation time 19675269892 ps
CPU time 1503.71 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:30:58 PM PST 24
Peak memory 389036 kb
Host smart-633fdeb9-1471-47cc-9381-14b68be44c59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1593620055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.1593620055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.193757333
Short name T171
Test name
Test status
Simulation time 17463125585 ps
CPU time 1430.78 seconds
Started Jan 07 01:05:06 PM PST 24
Finished Jan 07 01:28:58 PM PST 24
Peak memory 368404 kb
Host smart-311d0ca5-8074-464d-8fda-9590cca0273f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=193757333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.193757333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.1169002620
Short name T664
Test name
Test status
Simulation time 191028319410 ps
CPU time 1291.7 seconds
Started Jan 07 01:05:12 PM PST 24
Finished Jan 07 01:26:45 PM PST 24
Peak memory 328544 kb
Host smart-5dce9ac8-90d3-428f-afa5-119099936e5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1169002620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1169002620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.802847149
Short name T512
Test name
Test status
Simulation time 316097629065 ps
CPU time 3978.64 seconds
Started Jan 07 01:05:08 PM PST 24
Finished Jan 07 02:11:28 PM PST 24
Peak memory 561712 kb
Host smart-d80df4ba-c8e0-414f-a29e-12d6b7e9db4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=802847149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.802847149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1437554972
Short name T457
Test name
Test status
Simulation time 54538331 ps
CPU time 0.79 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:05:55 PM PST 24
Peak memory 205168 kb
Host smart-f97ba5fa-b2c5-4d1d-98c7-70fae4341ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437554972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1437554972 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.167848881
Short name T697
Test name
Test status
Simulation time 4239525612 ps
CPU time 85.66 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:07:11 PM PST 24
Peak memory 229808 kb
Host smart-85a59138-5dc2-42d1-8d57-ba7b7589d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167848881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.167848881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3416594344
Short name T122
Test name
Test status
Simulation time 15872761356 ps
CPU time 225.5 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:09:39 PM PST 24
Peak memory 233016 kb
Host smart-60b77197-6c6a-46fd-af9e-6d2ac5bdb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416594344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3416594344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1977175012
Short name T545
Test name
Test status
Simulation time 3401606157 ps
CPU time 53.39 seconds
Started Jan 07 01:05:47 PM PST 24
Finished Jan 07 01:06:42 PM PST 24
Peak memory 223992 kb
Host smart-5f38c9e7-bc00-4beb-836a-727fb2c7806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977175012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1977175012 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3473599098
Short name T454
Test name
Test status
Simulation time 52695690370 ps
CPU time 367.52 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:11:54 PM PST 24
Peak memory 256636 kb
Host smart-ee7d9cab-903f-450b-b8c2-fbe98c1126ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473599098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3473599098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2630037731
Short name T49
Test name
Test status
Simulation time 1689721318 ps
CPU time 4.77 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 207296 kb
Host smart-c9f97d96-79ee-419c-ac16-d62ddeaf2069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630037731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2630037731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2409047444
Short name T222
Test name
Test status
Simulation time 164458863 ps
CPU time 1.19 seconds
Started Jan 07 01:05:48 PM PST 24
Finished Jan 07 01:05:50 PM PST 24
Peak memory 215632 kb
Host smart-77e9c098-19c6-4ff2-9373-008048c754df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409047444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2409047444 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.51548392
Short name T570
Test name
Test status
Simulation time 69509838981 ps
CPU time 2339.07 seconds
Started Jan 07 01:05:37 PM PST 24
Finished Jan 07 01:44:37 PM PST 24
Peak memory 488376 kb
Host smart-ad417273-9801-413e-8c31-6510f7096262
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51548392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and
_output.51548392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.421832680
Short name T574
Test name
Test status
Simulation time 3740093300 ps
CPU time 130.07 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:08:03 PM PST 24
Peak memory 233640 kb
Host smart-47e94c17-7e58-4683-9ce6-307f92f7f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421832680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.421832680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.1614015024
Short name T467
Test name
Test status
Simulation time 2149698130 ps
CPU time 16.95 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:06:26 PM PST 24
Peak memory 221604 kb
Host smart-82dafac1-9651-4a4b-a148-7208b86d33ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614015024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1614015024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1751266586
Short name T789
Test name
Test status
Simulation time 21368972785 ps
CPU time 228.17 seconds
Started Jan 07 01:06:01 PM PST 24
Finished Jan 07 01:09:52 PM PST 24
Peak memory 271140 kb
Host smart-76ad1245-5f37-42c1-aa7a-f24e91a79551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1751266586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1751266586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_stress_all_with_rand_reset.284294074
Short name T511
Test name
Test status
Simulation time 329720285255 ps
CPU time 1055.22 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:23:33 PM PST 24
Peak memory 288828 kb
Host smart-180d8cbf-d7c1-4db2-8450-7e35ff7eb215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284294074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.284294074 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1568232461
Short name T4
Test name
Test status
Simulation time 411963602 ps
CPU time 3.98 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 215808 kb
Host smart-5e3bbc32-b54f-41a6-933a-a09d08609f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568232461 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1568232461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2077152418
Short name T732
Test name
Test status
Simulation time 245457086 ps
CPU time 3.84 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:02 PM PST 24
Peak memory 215736 kb
Host smart-e99cf204-6823-4371-8395-310f1a071878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077152418 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2077152418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.1162773978
Short name T418
Test name
Test status
Simulation time 263470707810 ps
CPU time 1684.48 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:34:05 PM PST 24
Peak memory 370840 kb
Host smart-430556de-522f-4fbf-a8e3-701fa950b6bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1162773978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1162773978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3980755791
Short name T901
Test name
Test status
Simulation time 123541472821 ps
CPU time 1195.59 seconds
Started Jan 07 01:06:01 PM PST 24
Finished Jan 07 01:26:00 PM PST 24
Peak memory 333628 kb
Host smart-d029ae3b-2fd1-4eae-8cb3-65e7e8eae3dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3980755791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3980755791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2961274220
Short name T714
Test name
Test status
Simulation time 465219136242 ps
CPU time 1064.24 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:23:57 PM PST 24
Peak memory 293004 kb
Host smart-060b8358-fef5-4db1-baee-0f710c9f4b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2961274220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2961274220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_alert_test.2983097939
Short name T54
Test name
Test status
Simulation time 36535664 ps
CPU time 0.77 seconds
Started Jan 07 01:05:13 PM PST 24
Finished Jan 07 01:05:15 PM PST 24
Peak memory 205124 kb
Host smart-c602f522-55f7-46f3-82d3-16cecc0284de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983097939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2983097939 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.1099496935
Short name T693
Test name
Test status
Simulation time 8561297060 ps
CPU time 192.09 seconds
Started Jan 07 01:05:25 PM PST 24
Finished Jan 07 01:08:38 PM PST 24
Peak memory 239840 kb
Host smart-6329e980-aab5-4340-be1c-07d2fa3c7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099496935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1099496935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.725220363
Short name T433
Test name
Test status
Simulation time 5545625723 ps
CPU time 151.32 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:08:42 PM PST 24
Peak memory 224316 kb
Host smart-dbf6caf4-0900-4c24-bb4d-3e6c460f30b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725220363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.725220363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2648954293
Short name T283
Test name
Test status
Simulation time 6470832569 ps
CPU time 159 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:08:33 PM PST 24
Peak memory 237516 kb
Host smart-a6c3528c-546b-4adc-8594-f8f8520995fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648954293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2648954293 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.1828739577
Short name T828
Test name
Test status
Simulation time 8090803718 ps
CPU time 123.74 seconds
Started Jan 07 01:05:31 PM PST 24
Finished Jan 07 01:07:35 PM PST 24
Peak memory 256748 kb
Host smart-2fd8ff73-4d62-4ca2-84ec-cb1a4da2e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828739577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1828739577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2456027655
Short name T627
Test name
Test status
Simulation time 1106293342 ps
CPU time 3.57 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 207344 kb
Host smart-6ea77658-b5ce-4ef8-b726-e4051215da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456027655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2456027655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.1446178429
Short name T526
Test name
Test status
Simulation time 66724965734 ps
CPU time 880.2 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:20:48 PM PST 24
Peak memory 311160 kb
Host smart-f24a11b9-3371-401e-920b-3f0c7996729d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446178429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.1446178429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.3266975961
Short name T857
Test name
Test status
Simulation time 143736325286 ps
CPU time 1760.49 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:35:07 PM PST 24
Peak memory 338384 kb
Host smart-1c69194b-e0ee-41b7-bba4-ec540d3640a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266975961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.3266975961 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.786049580
Short name T643
Test name
Test status
Simulation time 238308276 ps
CPU time 4.54 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 215608 kb
Host smart-c864676c-7b41-4b58-90c3-1c309b12e13e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786049580 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.kmac_test_vectors_kmac.786049580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.355064639
Short name T831
Test name
Test status
Simulation time 255335387 ps
CPU time 4.77 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:04 PM PST 24
Peak memory 215792 kb
Host smart-5ff9b549-557b-4003-9df8-f8fc7372bc57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355064639 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.355064639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.3302491588
Short name T647
Test name
Test status
Simulation time 1084693121498 ps
CPU time 1956.46 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:38:38 PM PST 24
Peak memory 393704 kb
Host smart-c39d12d5-3ab7-4cdc-afbb-a6bc2124b2de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3302491588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3302491588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.479975465
Short name T811
Test name
Test status
Simulation time 18752915776 ps
CPU time 1491.96 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:31:03 PM PST 24
Peak memory 379052 kb
Host smart-49cabb40-d978-473b-831f-8fd48a57e7cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=479975465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.479975465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.2247662827
Short name T523
Test name
Test status
Simulation time 13613215708 ps
CPU time 1020.11 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:22:55 PM PST 24
Peak memory 333296 kb
Host smart-da136479-0477-496e-9f99-793299804068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2247662827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2247662827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.3522039689
Short name T445
Test name
Test status
Simulation time 33125817733 ps
CPU time 795.13 seconds
Started Jan 07 01:05:17 PM PST 24
Finished Jan 07 01:18:34 PM PST 24
Peak memory 289940 kb
Host smart-a9433c2e-f651-4133-b9d5-e6fd6975a80e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3522039689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3522039689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.2878094422
Short name T839
Test name
Test status
Simulation time 747341671880 ps
CPU time 4806.82 seconds
Started Jan 07 01:05:33 PM PST 24
Finished Jan 07 02:25:41 PM PST 24
Peak memory 649760 kb
Host smart-bff58eba-0977-4ae8-9a36-a1203da17037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2878094422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2878094422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.3003017111
Short name T684
Test name
Test status
Simulation time 174345057128 ps
CPU time 3216.52 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:59:39 PM PST 24
Peak memory 567344 kb
Host smart-be963318-5de7-4a51-9a0e-31b4d49be9f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3003017111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3003017111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.115822065
Short name T275
Test name
Test status
Simulation time 35895106 ps
CPU time 0.75 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 205212 kb
Host smart-7379cfb5-0042-457a-825e-19e4cef7476c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115822065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.115822065 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.621974423
Short name T103
Test name
Test status
Simulation time 58206673181 ps
CPU time 172.3 seconds
Started Jan 07 01:05:33 PM PST 24
Finished Jan 07 01:08:26 PM PST 24
Peak memory 236688 kb
Host smart-379faaa2-7984-4284-8ac3-a5276ad8ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621974423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.621974423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.2621124442
Short name T355
Test name
Test status
Simulation time 13693840949 ps
CPU time 281.91 seconds
Started Jan 07 01:05:21 PM PST 24
Finished Jan 07 01:10:04 PM PST 24
Peak memory 227136 kb
Host smart-f2bdb853-6207-4b35-9ca5-81b502b1c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621124442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2621124442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_error.1401337200
Short name T145
Test name
Test status
Simulation time 3252350139 ps
CPU time 117.41 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:07:41 PM PST 24
Peak memory 240264 kb
Host smart-ce219493-5760-4946-b9df-8ac0d7fe1112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401337200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1401337200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.759848014
Short name T19
Test name
Test status
Simulation time 1087771698 ps
CPU time 5.65 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 207256 kb
Host smart-786004f9-5d66-4e15-a151-a8ca1ab50554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759848014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.759848014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.922087595
Short name T851
Test name
Test status
Simulation time 101047624 ps
CPU time 1.19 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 215540 kb
Host smart-68da292a-5756-40e6-8cf6-75d9814462b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922087595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.922087595 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.4109547477
Short name T50
Test name
Test status
Simulation time 108088441051 ps
CPU time 1962.3 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:38:39 PM PST 24
Peak memory 462028 kb
Host smart-8cfc8093-a3c2-4a55-bce6-bd196f1be665
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109547477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.4109547477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3583804732
Short name T297
Test name
Test status
Simulation time 24613710576 ps
CPU time 313 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:11:04 PM PST 24
Peak memory 245192 kb
Host smart-70438e42-1bec-479a-8c64-46a6cde501e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583804732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3583804732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3241356274
Short name T683
Test name
Test status
Simulation time 4147734381 ps
CPU time 62.32 seconds
Started Jan 07 01:05:47 PM PST 24
Finished Jan 07 01:06:51 PM PST 24
Peak memory 219284 kb
Host smart-e15ee104-6f31-48c8-b4c8-814d040fa5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241356274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3241356274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1912437635
Short name T513
Test name
Test status
Simulation time 13959538905 ps
CPU time 932.11 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:21:27 PM PST 24
Peak memory 352744 kb
Host smart-65a8ab7b-3feb-48db-8e1a-ee2ccef2f9f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1912437635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1912437635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1825311960
Short name T211
Test name
Test status
Simulation time 1653300725 ps
CPU time 4.91 seconds
Started Jan 07 01:05:20 PM PST 24
Finished Jan 07 01:05:27 PM PST 24
Peak memory 215768 kb
Host smart-de7ce3cd-c94a-46d7-965d-4b2bb65a8394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825311960 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1825311960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1305219839
Short name T569
Test name
Test status
Simulation time 64087972087 ps
CPU time 1770.45 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:35:20 PM PST 24
Peak memory 390720 kb
Host smart-37430025-1778-4e2a-84ce-8488ac1f8083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1305219839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1305219839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.3428558628
Short name T871
Test name
Test status
Simulation time 106785535158 ps
CPU time 4054.53 seconds
Started Jan 07 01:05:47 PM PST 24
Finished Jan 07 02:13:23 PM PST 24
Peak memory 657312 kb
Host smart-b49ec685-bbcd-4710-8695-0804019486bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3428558628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3428558628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.2526439414
Short name T543
Test name
Test status
Simulation time 1610591180432 ps
CPU time 4316.3 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 02:17:58 PM PST 24
Peak memory 560004 kb
Host smart-bb8fd7bc-05e1-4c5b-8736-171846b09380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2526439414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2526439414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3873130569
Short name T191
Test name
Test status
Simulation time 24273466 ps
CPU time 0.77 seconds
Started Jan 07 01:05:27 PM PST 24
Finished Jan 07 01:05:28 PM PST 24
Peak memory 205212 kb
Host smart-b5b5090f-3837-43d2-908e-d49625c943e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873130569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3873130569 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1220524100
Short name T200
Test name
Test status
Simulation time 159720734 ps
CPU time 3.62 seconds
Started Jan 07 01:05:34 PM PST 24
Finished Jan 07 01:05:38 PM PST 24
Peak memory 220044 kb
Host smart-bad8050a-a826-4141-945c-989b25ea8a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220524100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1220524100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.4290848085
Short name T623
Test name
Test status
Simulation time 2526515363 ps
CPU time 45.84 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:06:57 PM PST 24
Peak memory 220708 kb
Host smart-c30c1cb9-748c-4745-b5e0-5e66df4b6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290848085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.4290848085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_key_error.3937060510
Short name T65
Test name
Test status
Simulation time 474801537 ps
CPU time 2.9 seconds
Started Jan 07 01:05:18 PM PST 24
Finished Jan 07 01:05:22 PM PST 24
Peak memory 207288 kb
Host smart-4bac810b-fc57-4495-b692-74e90169adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937060510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3937060510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2774004466
Short name T428
Test name
Test status
Simulation time 200201794 ps
CPU time 1.29 seconds
Started Jan 07 01:05:14 PM PST 24
Finished Jan 07 01:05:16 PM PST 24
Peak memory 215680 kb
Host smart-f5c47378-7e7d-4a90-972f-111e4a10057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774004466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2774004466 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_smoke.4268366366
Short name T174
Test name
Test status
Simulation time 45551015 ps
CPU time 2.55 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 218916 kb
Host smart-272fd314-e467-42dc-b313-b2624e846cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268366366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.4268366366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1817816547
Short name T600
Test name
Test status
Simulation time 21476250747 ps
CPU time 468.22 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:13:30 PM PST 24
Peak memory 271504 kb
Host smart-459d029a-75da-439b-909c-803b4f6547d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1817816547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1817816547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_stress_all_with_rand_reset.1670436166
Short name T617
Test name
Test status
Simulation time 31723224154 ps
CPU time 417.69 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:12:40 PM PST 24
Peak memory 273376 kb
Host smart-3621eba2-2711-4a73-a37a-13845af68742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670436166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.1670436166 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.4032224299
Short name T307
Test name
Test status
Simulation time 2028117521 ps
CPU time 5.22 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:05:58 PM PST 24
Peak memory 209024 kb
Host smart-cb081768-8da5-46e2-b3bc-2d20f611eb30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032224299 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.4032224299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.675790607
Short name T726
Test name
Test status
Simulation time 76428376861 ps
CPU time 1448.01 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:29:54 PM PST 24
Peak memory 370980 kb
Host smart-a0dc478a-7b9e-4578-a0de-eea0f2473a59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=675790607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.675790607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3486967191
Short name T547
Test name
Test status
Simulation time 50975975605 ps
CPU time 1094.63 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:24:24 PM PST 24
Peak memory 336804 kb
Host smart-c1c1a77a-ba1a-467e-a6a9-3d962795c8a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3486967191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3486967191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.2215028117
Short name T700
Test name
Test status
Simulation time 165047578663 ps
CPU time 971.35 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:22:20 PM PST 24
Peak memory 291224 kb
Host smart-ff451961-403e-45d5-b63c-b1538cff84d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2215028117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2215028117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.1314939736
Short name T778
Test name
Test status
Simulation time 256649233737 ps
CPU time 4927.96 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 02:28:12 PM PST 24
Peak memory 649620 kb
Host smart-63147a3b-d3f1-466c-8929-877ba11877e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1314939736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.1314939736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.3807673934
Short name T847
Test name
Test status
Simulation time 596645857628 ps
CPU time 3722.04 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 02:08:00 PM PST 24
Peak memory 549464 kb
Host smart-3dabb69b-e86b-465d-9a9b-163eb33f972e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3807673934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3807673934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3452090245
Short name T874
Test name
Test status
Simulation time 34652414 ps
CPU time 0.73 seconds
Started Jan 07 01:06:02 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 205100 kb
Host smart-0ac5849c-a5f4-45df-8fc1-8a6db762dd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452090245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3452090245 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.950891296
Short name T362
Test name
Test status
Simulation time 3786269198 ps
CPU time 62.26 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:06:55 PM PST 24
Peak memory 226276 kb
Host smart-b414bd56-8337-42dc-8cf3-89ebf3d59358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950891296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.950891296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.4150271044
Short name T466
Test name
Test status
Simulation time 30520176353 ps
CPU time 288.16 seconds
Started Jan 07 01:05:38 PM PST 24
Finished Jan 07 01:10:33 PM PST 24
Peak memory 244580 kb
Host smart-aa15ff1e-8c5b-4da3-8d36-f89c4a781578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150271044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.4150271044 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_key_error.2152475013
Short name T791
Test name
Test status
Simulation time 3761064256 ps
CPU time 4.43 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:05:44 PM PST 24
Peak memory 207292 kb
Host smart-44617d0c-ab6c-46ea-a3e6-7f5f3cca8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152475013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2152475013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.986216158
Short name T366
Test name
Test status
Simulation time 43080167 ps
CPU time 1.18 seconds
Started Jan 07 01:05:12 PM PST 24
Finished Jan 07 01:05:14 PM PST 24
Peak memory 215680 kb
Host smart-2ffbc6a8-a212-4642-a6aa-5b3ba1632216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986216158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.986216158 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1423712654
Short name T602
Test name
Test status
Simulation time 6109650423 ps
CPU time 520.27 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:14:36 PM PST 24
Peak memory 277504 kb
Host smart-0f2cc7bf-4164-4b0e-9c53-047312bf8d5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423712654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1423712654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1922421498
Short name T775
Test name
Test status
Simulation time 48499345374 ps
CPU time 314.25 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:11:02 PM PST 24
Peak memory 245680 kb
Host smart-e5e1a0a9-c2a6-4203-8397-5440e9852b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922421498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1922421498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1425125631
Short name T741
Test name
Test status
Simulation time 270830122 ps
CPU time 7.46 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:05:50 PM PST 24
Peak memory 218980 kb
Host smart-9e3a9b0e-26ea-4a61-9ac0-87a4288f35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425125631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1425125631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.4246698855
Short name T500
Test name
Test status
Simulation time 50795295545 ps
CPU time 1055.29 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:23:32 PM PST 24
Peak memory 355220 kb
Host smart-2404f0cc-d4fc-425d-8191-c68f4a7bcda5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4246698855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.4246698855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.921594563
Short name T530
Test name
Test status
Simulation time 252207784 ps
CPU time 3.77 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:05:47 PM PST 24
Peak memory 215724 kb
Host smart-a4ef273a-1a50-49d2-afa9-9ffc7b3a1a4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921594563 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.921594563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3467361219
Short name T6
Test name
Test status
Simulation time 258543353 ps
CPU time 3.99 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 209048 kb
Host smart-88260938-b2ca-4bfa-94bc-dad3d318b4e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467361219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3467361219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.398965244
Short name T178
Test name
Test status
Simulation time 67578102170 ps
CPU time 1893.8 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:37:43 PM PST 24
Peak memory 391936 kb
Host smart-7d4b8640-93b3-40c9-a868-d219970d3530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=398965244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.398965244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.3281117681
Short name T557
Test name
Test status
Simulation time 74605266666 ps
CPU time 1386.73 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:28:50 PM PST 24
Peak memory 361304 kb
Host smart-ab92d42e-67b5-4194-93a4-606016805aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3281117681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.3281117681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3667440144
Short name T246
Test name
Test status
Simulation time 293575738577 ps
CPU time 1284.75 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:27:13 PM PST 24
Peak memory 323604 kb
Host smart-2e6dfe22-e1a0-4781-8c28-e3d433ffb47e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3667440144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3667440144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.1951960290
Short name T806
Test name
Test status
Simulation time 19066909820 ps
CPU time 763.76 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:18:32 PM PST 24
Peak memory 291224 kb
Host smart-43b2b615-c900-4a26-9d63-a1880d8f6559
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1951960290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1951960290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1165551166
Short name T137
Test name
Test status
Simulation time 43485624242 ps
CPU time 3239.98 seconds
Started Jan 07 01:05:26 PM PST 24
Finished Jan 07 01:59:27 PM PST 24
Peak memory 565068 kb
Host smart-898ee790-4cf8-4e71-9a8b-7f772c794412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1165551166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1165551166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_app.226527164
Short name T395
Test name
Test status
Simulation time 127243902945 ps
CPU time 129.83 seconds
Started Jan 07 01:04:01 PM PST 24
Finished Jan 07 01:06:15 PM PST 24
Peak memory 233364 kb
Host smart-f1b93a90-e99e-473a-a7a6-75d3af59b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226527164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.226527164 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.2744630403
Short name T893
Test name
Test status
Simulation time 21365869354 ps
CPU time 172.53 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:06:50 PM PST 24
Peak memory 237928 kb
Host smart-b87d1f45-ce3a-40aa-8961-8a2a49ca4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744630403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2744630403 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.528301836
Short name T825
Test name
Test status
Simulation time 15320864599 ps
CPU time 434.23 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:11:00 PM PST 24
Peak memory 229776 kb
Host smart-0d835955-d14a-4b7e-a7cb-6eb50c7fe400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528301836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.528301836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.985327343
Short name T909
Test name
Test status
Simulation time 485676304 ps
CPU time 17.41 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 222596 kb
Host smart-0c725951-956c-452c-9335-088f65346a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=985327343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.985327343 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.249339424
Short name T43
Test name
Test status
Simulation time 446090178 ps
CPU time 29.6 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:27 PM PST 24
Peak memory 223724 kb
Host smart-91cb89ce-4eee-47b6-b3f1-d9d1fbb8ebfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249339424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.249339424 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1240669011
Short name T855
Test name
Test status
Simulation time 1570800509 ps
CPU time 15.99 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:25 PM PST 24
Peak memory 215684 kb
Host smart-46465dc1-3a8a-472b-aa83-774e29d4f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240669011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1240669011 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_error.2973919513
Short name T553
Test name
Test status
Simulation time 3726990122 ps
CPU time 73.64 seconds
Started Jan 07 01:03:51 PM PST 24
Finished Jan 07 01:05:09 PM PST 24
Peak memory 240348 kb
Host smart-bb5812c6-3087-4403-aa0d-fb17fe3e6984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973919513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2973919513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.439194775
Short name T486
Test name
Test status
Simulation time 11256611313 ps
CPU time 311.93 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:09:09 PM PST 24
Peak memory 246936 kb
Host smart-1803bcc7-3294-4d6e-adf4-fecce625a2b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439194775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.439194775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3590572700
Short name T481
Test name
Test status
Simulation time 61411078884 ps
CPU time 164.41 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:06:54 PM PST 24
Peak memory 236640 kb
Host smart-1aad2629-c82e-4665-9463-67814bfa354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590572700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3590572700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2240674037
Short name T12
Test name
Test status
Simulation time 8497569895 ps
CPU time 29.53 seconds
Started Jan 07 01:04:01 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 242120 kb
Host smart-8c4f8cff-fe25-4ba1-a659-8d24f65f31aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240674037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2240674037 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.3567809716
Short name T724
Test name
Test status
Simulation time 1031614225 ps
CPU time 76.96 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:05:06 PM PST 24
Peak memory 226556 kb
Host smart-1e9654ec-42ec-468a-9a77-74430374a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567809716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3567809716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.3302006706
Short name T865
Test name
Test status
Simulation time 5454606591 ps
CPU time 50.98 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:04:39 PM PST 24
Peak memory 223820 kb
Host smart-8e44663c-87c3-4bd9-b8c7-ef13300bd657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302006706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3302006706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.294624220
Short name T757
Test name
Test status
Simulation time 47692365250 ps
CPU time 294.7 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 01:09:03 PM PST 24
Peak memory 235280 kb
Host smart-4930a7ff-596e-4fb4-b509-010fe926765c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=294624220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.294624220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.2802253176
Short name T656
Test name
Test status
Simulation time 22577152198 ps
CPU time 489.71 seconds
Started Jan 07 01:04:10 PM PST 24
Finished Jan 07 01:12:22 PM PST 24
Peak memory 269000 kb
Host smart-8d497c4f-282d-4ed4-8648-dc8cb6c59689
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802253176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.2802253176 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2565097264
Short name T236
Test name
Test status
Simulation time 130726141 ps
CPU time 4.02 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 208968 kb
Host smart-df934d72-b7eb-4aed-bf0b-9788cf07511a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565097264 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2565097264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3579886816
Short name T438
Test name
Test status
Simulation time 178554475 ps
CPU time 4.51 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 215752 kb
Host smart-fc4811a5-e419-4102-b21d-2a264e59615d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579886816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3579886816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2463957908
Short name T180
Test name
Test status
Simulation time 18725871793 ps
CPU time 1506.75 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:29:16 PM PST 24
Peak memory 389644 kb
Host smart-e34ea127-82f3-4c4e-8e37-b0dbc7b2d98a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2463957908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2463957908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.995723884
Short name T687
Test name
Test status
Simulation time 291823979180 ps
CPU time 1407.81 seconds
Started Jan 07 01:03:45 PM PST 24
Finished Jan 07 01:27:19 PM PST 24
Peak memory 332816 kb
Host smart-ab00ff08-57c3-424f-8000-3f8b346532f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=995723884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.995723884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3698596341
Short name T269
Test name
Test status
Simulation time 41029803051 ps
CPU time 752.76 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:16:22 PM PST 24
Peak memory 293396 kb
Host smart-1562a15b-afdd-4c57-bd34-cf7063d150b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3698596341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3698596341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.4258567543
Short name T402
Test name
Test status
Simulation time 172952036153 ps
CPU time 4573.08 seconds
Started Jan 07 01:03:46 PM PST 24
Finished Jan 07 02:20:06 PM PST 24
Peak memory 646108 kb
Host smart-1e452040-f259-45d7-aa51-7c046ec9f9da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4258567543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4258567543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.2169525684
Short name T642
Test name
Test status
Simulation time 174892183393 ps
CPU time 3358.95 seconds
Started Jan 07 01:03:41 PM PST 24
Finished Jan 07 01:59:49 PM PST 24
Peak memory 570584 kb
Host smart-aa4560dc-b32b-423f-99e9-efa2bbe71c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2169525684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2169525684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.1566862489
Short name T340
Test name
Test status
Simulation time 29334538 ps
CPU time 0.75 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:05:59 PM PST 24
Peak memory 205204 kb
Host smart-3aefc5ba-2c14-45f5-bbdc-e7f2ffc75b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566862489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1566862489 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.1760590741
Short name T140
Test name
Test status
Simulation time 56940787195 ps
CPU time 256.91 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:09:59 PM PST 24
Peak memory 243160 kb
Host smart-d8b9dfeb-55da-40d6-bd22-789eaa7c5bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760590741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1760590741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.96158896
Short name T858
Test name
Test status
Simulation time 83094755424 ps
CPU time 469.68 seconds
Started Jan 07 01:05:32 PM PST 24
Finished Jan 07 01:13:22 PM PST 24
Peak memory 228992 kb
Host smart-fd6af767-1c94-441e-9419-c253431b60eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96158896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.96158896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2392249858
Short name T788
Test name
Test status
Simulation time 15193000580 ps
CPU time 306.73 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:10:51 PM PST 24
Peak memory 245628 kb
Host smart-41f07afe-3bcd-4fc3-9abf-2e737cd330e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392249858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2392249858 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.954680328
Short name T635
Test name
Test status
Simulation time 12461828455 ps
CPU time 302.87 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:11:16 PM PST 24
Peak memory 256712 kb
Host smart-14b9945a-4a04-4ab8-ad4e-4c96f6165d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954680328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.954680328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.2703955079
Short name T324
Test name
Test status
Simulation time 20474966356 ps
CPU time 556.33 seconds
Started Jan 07 01:05:32 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 273316 kb
Host smart-4aa7ebf7-44a1-42c9-978e-2d6fd79d12ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703955079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.2703955079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1478551774
Short name T705
Test name
Test status
Simulation time 17083201831 ps
CPU time 295.65 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:10:58 PM PST 24
Peak memory 247364 kb
Host smart-f8f4907d-11c6-403e-a775-88c2fac568e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478551774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1478551774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.4272382031
Short name T139
Test name
Test status
Simulation time 2807298425 ps
CPU time 40.4 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:06:32 PM PST 24
Peak memory 217680 kb
Host smart-5e3f7069-2643-47a9-ae87-9ab656215e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272382031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.4272382031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1619684564
Short name T417
Test name
Test status
Simulation time 33100999776 ps
CPU time 207.04 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:09:21 PM PST 24
Peak memory 270492 kb
Host smart-b001238b-5e7d-4570-971e-f578e02b5a29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1619684564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1619684564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.3369067349
Short name T669
Test name
Test status
Simulation time 916496236 ps
CPU time 4.87 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 208592 kb
Host smart-b5efd171-90cd-4bb9-a66b-f9cda321ae72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369067349 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.3369067349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.934068574
Short name T205
Test name
Test status
Simulation time 82600509 ps
CPU time 4.34 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 209064 kb
Host smart-741bf6a0-686a-401c-902b-d83baae7b29d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934068574 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.934068574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.4209067620
Short name T273
Test name
Test status
Simulation time 67127947766 ps
CPU time 1777.58 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:35:24 PM PST 24
Peak memory 397068 kb
Host smart-1132c8af-544c-44aa-a87b-5e62fbdcb7c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4209067620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.4209067620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1639760148
Short name T812
Test name
Test status
Simulation time 120472406767 ps
CPU time 1703.98 seconds
Started Jan 07 01:05:16 PM PST 24
Finished Jan 07 01:33:41 PM PST 24
Peak memory 368944 kb
Host smart-e7aa6b07-75d7-40d0-9d9e-19de3c7953c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1639760148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1639760148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.2117743717
Short name T187
Test name
Test status
Simulation time 451664238922 ps
CPU time 1452.87 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:30:21 PM PST 24
Peak memory 325252 kb
Host smart-ec098fc6-f4ad-467e-8f74-5b86f69f6fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2117743717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2117743717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.3134902393
Short name T296
Test name
Test status
Simulation time 37440640247 ps
CPU time 788.51 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:18:54 PM PST 24
Peak memory 292008 kb
Host smart-b52caf5c-a613-40aa-b7c7-d71d25ad4e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3134902393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3134902393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.1234495794
Short name T587
Test name
Test status
Simulation time 171848532293 ps
CPU time 4612.83 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 02:22:51 PM PST 24
Peak memory 648180 kb
Host smart-7e908bfc-15ce-44b8-96b6-f7b8e003ad97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1234495794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1234495794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.1475228845
Short name T841
Test name
Test status
Simulation time 173608815785 ps
CPU time 3275.91 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 02:00:22 PM PST 24
Peak memory 566284 kb
Host smart-1a67db9f-bc19-45e7-9d37-22e79029696f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1475228845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1475228845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.3467757763
Short name T377
Test name
Test status
Simulation time 31056439 ps
CPU time 0.71 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 205128 kb
Host smart-b251f2b6-832e-4392-a502-387648776ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467757763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3467757763 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.1599620949
Short name T546
Test name
Test status
Simulation time 1490570530 ps
CPU time 72.05 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:07:13 PM PST 24
Peak memory 226808 kb
Host smart-157a2e87-da3d-494a-8596-08d91d0f5ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599620949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1599620949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.445918889
Short name T544
Test name
Test status
Simulation time 27301001835 ps
CPU time 154.63 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 222964 kb
Host smart-7f6d6348-bbe6-4c2c-a4e0-8bc294070672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445918889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.445918889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2485511133
Short name T465
Test name
Test status
Simulation time 47443302652 ps
CPU time 132.98 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:08:03 PM PST 24
Peak memory 233260 kb
Host smart-f59390d9-0806-4fa9-b6af-0a268ffe6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485511133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2485511133 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3555767076
Short name T459
Test name
Test status
Simulation time 1783894334 ps
CPU time 131.75 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:07:49 PM PST 24
Peak memory 248468 kb
Host smart-a97f36fd-b03c-427c-993a-611d07a2f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555767076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3555767076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.197168458
Short name T358
Test name
Test status
Simulation time 624079705 ps
CPU time 2.19 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:05:48 PM PST 24
Peak memory 207376 kb
Host smart-bcb9f69c-b4c9-44f9-b135-9aa65cf73b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197168458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.197168458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.2245334854
Short name T206
Test name
Test status
Simulation time 100670781 ps
CPU time 1.29 seconds
Started Jan 07 01:05:28 PM PST 24
Finished Jan 07 01:05:30 PM PST 24
Peak memory 215596 kb
Host smart-6ff2c941-4efb-4fa3-8a8d-13ff2a2c45dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245334854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2245334854 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.3395350839
Short name T396
Test name
Test status
Simulation time 7630670859 ps
CPU time 153.09 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:08:25 PM PST 24
Peak memory 240368 kb
Host smart-1a513ffb-d979-41cd-88b9-b7daee85b680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395350839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.3395350839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2289148263
Short name T383
Test name
Test status
Simulation time 10678503420 ps
CPU time 195 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:09:16 PM PST 24
Peak memory 238968 kb
Host smart-ff4d3831-ee2e-431e-b5dc-2bed11a75b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289148263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2289148263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1431105239
Short name T707
Test name
Test status
Simulation time 892939574 ps
CPU time 22.78 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:22 PM PST 24
Peak memory 217888 kb
Host smart-8ca0c6b9-2539-4ba6-a959-dd1e68cc30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431105239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1431105239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.2787222356
Short name T40
Test name
Test status
Simulation time 127580631726 ps
CPU time 890.18 seconds
Started Jan 07 01:05:35 PM PST 24
Finished Jan 07 01:20:26 PM PST 24
Peak memory 346972 kb
Host smart-60181dae-0822-4708-ab79-010e7157bd6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2787222356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2787222356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_stress_all_with_rand_reset.2200038623
Short name T144
Test name
Test status
Simulation time 196375473650 ps
CPU time 840.99 seconds
Started Jan 07 01:05:30 PM PST 24
Finished Jan 07 01:19:32 PM PST 24
Peak memory 288676 kb
Host smart-457f391e-7995-4532-8c6e-d8d9ba86ee47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200038623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.2200038623 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.3714330565
Short name T548
Test name
Test status
Simulation time 68722787 ps
CPU time 4.05 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:06:00 PM PST 24
Peak memory 215700 kb
Host smart-cb514409-cde4-49c7-8faa-a640b45888a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714330565 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.3714330565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3906502580
Short name T601
Test name
Test status
Simulation time 223138296 ps
CPU time 4.17 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:05:58 PM PST 24
Peak memory 215712 kb
Host smart-7fd7513d-a96b-46c9-ac10-c5ef70dda1b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906502580 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3906502580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.4288734354
Short name T708
Test name
Test status
Simulation time 77376306039 ps
CPU time 1469.49 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:30:25 PM PST 24
Peak memory 379152 kb
Host smart-abcc5041-72b9-453e-87b9-26e9e1259fe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4288734354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.4288734354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.1223017920
Short name T70
Test name
Test status
Simulation time 61633597149 ps
CPU time 1178.69 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:25:26 PM PST 24
Peak memory 333428 kb
Host smart-67e80e06-c1f0-4528-8325-0f5e6da4e37d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1223017920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1223017920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1850453611
Short name T584
Test name
Test status
Simulation time 235718415601 ps
CPU time 936.73 seconds
Started Jan 07 01:06:08 PM PST 24
Finished Jan 07 01:21:47 PM PST 24
Peak memory 297036 kb
Host smart-1d6d4393-8195-489f-8081-0f36f719db3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1850453611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1850453611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.1467463312
Short name T325
Test name
Test status
Simulation time 232085535957 ps
CPU time 4952.41 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 02:28:40 PM PST 24
Peak memory 660448 kb
Host smart-9c95e660-74cc-4f80-bbb3-99b881d249af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1467463312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1467463312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2974486916
Short name T861
Test name
Test status
Simulation time 471752734365 ps
CPU time 3731.81 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 02:08:05 PM PST 24
Peak memory 566608 kb
Host smart-aa9fa4e5-7f20-4a1c-a833-75ead8ea6669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2974486916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2974486916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3917566477
Short name T873
Test name
Test status
Simulation time 17170155 ps
CPU time 0.77 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 205212 kb
Host smart-cc25126e-fd3a-4b31-b48a-af0adf10de0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917566477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3917566477 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.1507955136
Short name T629
Test name
Test status
Simulation time 3118697348 ps
CPU time 111.92 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:07:45 PM PST 24
Peak memory 233564 kb
Host smart-6ed2daa1-f54d-4140-8141-a3b6cf092e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507955136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1507955136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.2396971420
Short name T681
Test name
Test status
Simulation time 84257870165 ps
CPU time 679.2 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:16:59 PM PST 24
Peak memory 231836 kb
Host smart-ccb44740-6dc2-46c7-a8b6-deb55d54b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396971420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2396971420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_error.1077170567
Short name T894
Test name
Test status
Simulation time 1818593143 ps
CPU time 17.93 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:17 PM PST 24
Peak memory 223828 kb
Host smart-dd2dba62-86b2-45c6-9ee1-d3d67bbc0505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077170567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1077170567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3011084741
Short name T368
Test name
Test status
Simulation time 239627616 ps
CPU time 3.38 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 221200 kb
Host smart-c77bc741-cb97-4756-9b2f-358664e693dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011084741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3011084741 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3442842915
Short name T821
Test name
Test status
Simulation time 41532405111 ps
CPU time 909.86 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:20:50 PM PST 24
Peak memory 301384 kb
Host smart-c4e86486-2885-4af3-a8f5-036a310522b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442842915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3442842915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3900485262
Short name T799
Test name
Test status
Simulation time 2685837740 ps
CPU time 53.77 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:06:39 PM PST 24
Peak memory 223840 kb
Host smart-c6cfa492-68b1-467e-956f-19cc82180512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900485262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3900485262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1068701145
Short name T166
Test name
Test status
Simulation time 841791590 ps
CPU time 38.58 seconds
Started Jan 07 01:05:31 PM PST 24
Finished Jan 07 01:06:10 PM PST 24
Peak memory 218604 kb
Host smart-9125f712-5fe9-4342-a3dc-e828502f81dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068701145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1068701145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1771989046
Short name T435
Test name
Test status
Simulation time 86043047403 ps
CPU time 1113.06 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:24:24 PM PST 24
Peak memory 400316 kb
Host smart-7c35177b-5def-4aef-82f6-f17720f3def1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1771989046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1771989046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_stress_all_with_rand_reset.3512923354
Short name T720
Test name
Test status
Simulation time 215983224687 ps
CPU time 895.58 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:20:54 PM PST 24
Peak memory 283516 kb
Host smart-b64386c7-7f7b-4b60-857e-42f9a7e6f340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512923354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all_with_rand_reset.3512923354 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.558803960
Short name T265
Test name
Test status
Simulation time 343344611 ps
CPU time 4.33 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:55 PM PST 24
Peak memory 208892 kb
Host smart-044fef51-2c15-4283-99f7-d6bac5f35219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558803960 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.558803960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1493121857
Short name T282
Test name
Test status
Simulation time 233317380 ps
CPU time 4.68 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 209196 kb
Host smart-2f934233-0da7-4aff-8048-ff3a23a6ed0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493121857 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1493121857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1176074275
Short name T390
Test name
Test status
Simulation time 435418118399 ps
CPU time 1918.53 seconds
Started Jan 07 01:05:35 PM PST 24
Finished Jan 07 01:37:35 PM PST 24
Peak memory 386760 kb
Host smart-c5773cd8-2c3b-4b59-aaa6-97ace3fe2e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1176074275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1176074275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.660158284
Short name T419
Test name
Test status
Simulation time 62284035357 ps
CPU time 1661.22 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:33:18 PM PST 24
Peak memory 373288 kb
Host smart-cf37ae4a-8bab-4e20-a01e-b297a45537c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=660158284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.660158284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2323784765
Short name T719
Test name
Test status
Simulation time 537953202403 ps
CPU time 1396.71 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:29:04 PM PST 24
Peak memory 333504 kb
Host smart-53851c98-799c-44e7-85cb-f2bff7a23bae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2323784765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2323784765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.2519576196
Short name T729
Test name
Test status
Simulation time 50518210131 ps
CPU time 941.56 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:21:33 PM PST 24
Peak memory 293712 kb
Host smart-ec2c39b7-ca15-4177-8504-854deef2a19d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2519576196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.2519576196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.21327316
Short name T455
Test name
Test status
Simulation time 718423450876 ps
CPU time 4624.23 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 02:23:16 PM PST 24
Peak memory 653088 kb
Host smart-ebe674e2-a14e-4847-ab00-37360fef2fa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=21327316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.21327316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.4194844449
Short name T198
Test name
Test status
Simulation time 221319523309 ps
CPU time 4158.95 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 02:14:56 PM PST 24
Peak memory 553820 kb
Host smart-dc5fc5f1-ba34-4d77-b0b2-7ce79629b955
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4194844449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.4194844449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.4032437746
Short name T793
Test name
Test status
Simulation time 14010200 ps
CPU time 0.73 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 205136 kb
Host smart-d21208aa-fb84-4836-97b3-81a0c9316795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032437746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.4032437746 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.4253275303
Short name T28
Test name
Test status
Simulation time 16211250656 ps
CPU time 165.9 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:08:49 PM PST 24
Peak memory 238432 kb
Host smart-8da4cdd0-1d56-4fb1-93d3-2a9b306aab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253275303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4253275303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3501470560
Short name T164
Test name
Test status
Simulation time 9156165483 ps
CPU time 736.83 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:18:04 PM PST 24
Peak memory 231736 kb
Host smart-f983b146-9807-4e4e-91a7-abc372e32354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501470560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3501470560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1811456068
Short name T711
Test name
Test status
Simulation time 30127642404 ps
CPU time 266.24 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:10:39 PM PST 24
Peak memory 243204 kb
Host smart-ba03bd49-663f-4552-a775-cbb33c021ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811456068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1811456068 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1600029213
Short name T884
Test name
Test status
Simulation time 55322843841 ps
CPU time 205.05 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:09:11 PM PST 24
Peak memory 248416 kb
Host smart-efac6f10-d4bc-4cd7-ac7b-e7f2db5c42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600029213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1600029213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2457068576
Short name T212
Test name
Test status
Simulation time 93483810 ps
CPU time 1.26 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:05:54 PM PST 24
Peak memory 215740 kb
Host smart-8d79d670-7860-4ee2-8e28-96de1a295b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457068576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2457068576 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.32563768
Short name T220
Test name
Test status
Simulation time 14672639310 ps
CPU time 276.17 seconds
Started Jan 07 01:05:39 PM PST 24
Finished Jan 07 01:10:16 PM PST 24
Peak memory 247848 kb
Host smart-efa18460-d477-4d99-9487-c0aac2ee1bc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and
_output.32563768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.106781161
Short name T597
Test name
Test status
Simulation time 60632548514 ps
CPU time 199.57 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:09:07 PM PST 24
Peak memory 236832 kb
Host smart-add474cf-26c4-40b1-8bbc-afd244eaab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106781161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.106781161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_stress_all.100714486
Short name T374
Test name
Test status
Simulation time 4527283019 ps
CPU time 251.82 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:10:07 PM PST 24
Peak memory 281300 kb
Host smart-d8390c13-c6ad-46d2-87f6-5ca16b2c057b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=100714486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.100714486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_stress_all_with_rand_reset.1834697072
Short name T37
Test name
Test status
Simulation time 76709126405 ps
CPU time 1405.89 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:29:16 PM PST 24
Peak memory 314424 kb
Host smart-c810be19-c612-4495-a667-4a02ae574908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834697072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.1834697072 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1776002878
Short name T844
Test name
Test status
Simulation time 975063709 ps
CPU time 4.76 seconds
Started Jan 07 01:05:36 PM PST 24
Finished Jan 07 01:05:42 PM PST 24
Peak memory 215824 kb
Host smart-be3da8b0-9169-442c-a89f-2e5701dd5f2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776002878 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1776002878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3594080315
Short name T416
Test name
Test status
Simulation time 96188128348 ps
CPU time 1825.89 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:36:20 PM PST 24
Peak memory 400096 kb
Host smart-fa369d8c-b4df-4f61-bfa7-44556e4b49d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3594080315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3594080315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.1151036432
Short name T795
Test name
Test status
Simulation time 60333225892 ps
CPU time 1621.32 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:32:43 PM PST 24
Peak memory 369712 kb
Host smart-78168cd5-758e-4d18-b6ed-5c625e11bf58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1151036432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.1151036432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1050976671
Short name T485
Test name
Test status
Simulation time 34035647201 ps
CPU time 856.39 seconds
Started Jan 07 01:05:48 PM PST 24
Finished Jan 07 01:20:05 PM PST 24
Peak memory 297016 kb
Host smart-5d290df4-0648-4dc9-890f-fa4b9a59e83c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1050976671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1050976671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.2047657775
Short name T564
Test name
Test status
Simulation time 50734417752 ps
CPU time 3940.96 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 02:11:27 PM PST 24
Peak memory 647232 kb
Host smart-79591494-81ce-4df0-afc4-2e4f8fc7c557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2047657775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.2047657775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3309862426
Short name T625
Test name
Test status
Simulation time 90178659684 ps
CPU time 3207.16 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:59:09 PM PST 24
Peak memory 562672 kb
Host smart-450ddb69-65ea-4b21-8afb-98d46a7020f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3309862426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3309862426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3056361153
Short name T423
Test name
Test status
Simulation time 15058253 ps
CPU time 0.79 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 205060 kb
Host smart-6100a14c-3faf-4067-9ac9-d9ef2edc26ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056361153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3056361153 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1834234081
Short name T271
Test name
Test status
Simulation time 1899549833 ps
CPU time 90.5 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:07:24 PM PST 24
Peak memory 230688 kb
Host smart-a22bc367-563d-46a8-97f9-aaebae25925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834234081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1834234081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1960611356
Short name T807
Test name
Test status
Simulation time 24276076869 ps
CPU time 183.2 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:08:59 PM PST 24
Peak memory 224228 kb
Host smart-c509364b-6b70-4e98-9335-ee4ce4b35942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960611356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1960611356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.4188853428
Short name T411
Test name
Test status
Simulation time 14914162982 ps
CPU time 150.03 seconds
Started Jan 07 01:06:02 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 233640 kb
Host smart-6e637616-d58a-4501-be54-d507c07ab1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188853428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.4188853428 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.955534709
Short name T405
Test name
Test status
Simulation time 3934529519 ps
CPU time 290.37 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:11:05 PM PST 24
Peak memory 256556 kb
Host smart-0e2899e2-0f98-4df0-a526-76e71a31d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955534709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.955534709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.706479352
Short name T593
Test name
Test status
Simulation time 872141651 ps
CPU time 4.83 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:06:23 PM PST 24
Peak memory 215492 kb
Host smart-34183998-6ef7-47a1-85ad-77c63ab34a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706479352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.706479352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_sideload.2385378869
Short name T840
Test name
Test status
Simulation time 8099760805 ps
CPU time 51.95 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:06:38 PM PST 24
Peak memory 223852 kb
Host smart-ab19e61b-d113-4be4-8966-dfcad40ed87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385378869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2385378869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2697002293
Short name T808
Test name
Test status
Simulation time 2149454847 ps
CPU time 43.53 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:06:38 PM PST 24
Peak memory 218648 kb
Host smart-d149d535-1e05-453c-92a4-a32b4b2aec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697002293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2697002293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2845614739
Short name T804
Test name
Test status
Simulation time 16086389486 ps
CPU time 1246.94 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:26:56 PM PST 24
Peak memory 371192 kb
Host smart-090be845-f4e6-4291-853c-9bca00f28d95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2845614739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2845614739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.3059708542
Short name T911
Test name
Test status
Simulation time 180543351 ps
CPU time 4.37 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 215592 kb
Host smart-bccd4e39-0d45-47fe-b84b-f1272ef39caa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059708542 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.3059708542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.1905359191
Short name T17
Test name
Test status
Simulation time 40216885995 ps
CPU time 1522.65 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:31:30 PM PST 24
Peak memory 388548 kb
Host smart-7becaf31-c95a-4e10-babd-430e01588918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1905359191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.1905359191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1147231044
Short name T228
Test name
Test status
Simulation time 10012352590 ps
CPU time 743.31 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:18:24 PM PST 24
Peak memory 300844 kb
Host smart-a1440294-c807-4022-a964-13d0198c60f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1147231044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1147231044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.3431821424
Short name T895
Test name
Test status
Simulation time 96968028885 ps
CPU time 3787.43 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 02:08:53 PM PST 24
Peak memory 641008 kb
Host smart-b3c61b58-b7e5-491d-bf07-d3cd26468ed0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3431821424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3431821424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.536039168
Short name T199
Test name
Test status
Simulation time 182312911871 ps
CPU time 3391.88 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 02:02:40 PM PST 24
Peak memory 570188 kb
Host smart-c8b4efbf-44c7-4ff0-b4dc-889c1b50e3b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=536039168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.536039168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.779805491
Short name T255
Test name
Test status
Simulation time 22218373 ps
CPU time 0.74 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:05:45 PM PST 24
Peak memory 205056 kb
Host smart-4e4d5b6e-f356-470c-821b-66ca2867fb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779805491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.779805491 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3650072175
Short name T794
Test name
Test status
Simulation time 12006236790 ps
CPU time 339.94 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:11:40 PM PST 24
Peak memory 228312 kb
Host smart-25cd4644-599d-4845-9ea5-69a09de02c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650072175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3650072175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.2203081675
Short name T688
Test name
Test status
Simulation time 20643560849 ps
CPU time 184.74 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:08:55 PM PST 24
Peak memory 236984 kb
Host smart-430f5a79-bdbe-4b48-ad00-0523121ccd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203081675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2203081675 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_key_error.2912676341
Short name T20
Test name
Test status
Simulation time 2018945987 ps
CPU time 4.47 seconds
Started Jan 07 01:05:46 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 207088 kb
Host smart-365f6546-9ccf-425e-914d-9eebc1d32f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912676341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2912676341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.2157323188
Short name T185
Test name
Test status
Simulation time 56840986 ps
CPU time 1.3 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:05:54 PM PST 24
Peak memory 216736 kb
Host smart-c42b09b8-8f8a-47dd-8c30-b02b223f5d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157323188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2157323188 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.1192306239
Short name T718
Test name
Test status
Simulation time 73616670024 ps
CPU time 1648.99 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:33:32 PM PST 24
Peak memory 386928 kb
Host smart-67ab8441-454b-411f-a91e-2c50d5847d1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192306239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.1192306239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1102578375
Short name T902
Test name
Test status
Simulation time 26175203078 ps
CPU time 341.87 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:11:55 PM PST 24
Peak memory 245368 kb
Host smart-8a81ab6d-c0fe-42e7-819e-6609e5c501ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102578375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1102578375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.4179750786
Short name T503
Test name
Test status
Simulation time 4894714070 ps
CPU time 38.76 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:41 PM PST 24
Peak memory 218592 kb
Host smart-4545db0c-2666-457a-bb56-ed33a5369893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179750786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4179750786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all_with_rand_reset.1216696007
Short name T129
Test name
Test status
Simulation time 24496581745 ps
CPU time 231.65 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:09:36 PM PST 24
Peak memory 264980 kb
Host smart-8c399ddb-4cdf-4cc0-b7f9-69d1fe74b581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216696007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.1216696007 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.2687164069
Short name T237
Test name
Test status
Simulation time 244478469 ps
CPU time 3.87 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 215676 kb
Host smart-1f9d7ba0-7a58-46db-8b21-d69d9bb52a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687164069 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.2687164069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2423605462
Short name T378
Test name
Test status
Simulation time 74114378247 ps
CPU time 1384.41 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:29:03 PM PST 24
Peak memory 378748 kb
Host smart-29a9c2ed-e90d-4f96-a042-2890e5aea889
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2423605462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2423605462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.4086050131
Short name T721
Test name
Test status
Simulation time 111345501652 ps
CPU time 1448.64 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:30:19 PM PST 24
Peak memory 375348 kb
Host smart-fe563b4a-dcc2-4542-b969-c257d79b937e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4086050131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.4086050131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2283757115
Short name T422
Test name
Test status
Simulation time 64464855913 ps
CPU time 1340.79 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:28:34 PM PST 24
Peak memory 339056 kb
Host smart-8277662b-e96b-421f-b010-c6f1ca9e4355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2283757115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2283757115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.4179612000
Short name T612
Test name
Test status
Simulation time 9673129013 ps
CPU time 779.86 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:19:15 PM PST 24
Peak memory 298192 kb
Host smart-57eb6a8c-50bc-43c1-b03e-95248ec4d462
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4179612000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.4179612000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.862781564
Short name T163
Test name
Test status
Simulation time 100760430170 ps
CPU time 4040.87 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 02:13:23 PM PST 24
Peak memory 640392 kb
Host smart-44c1098b-121c-4bc8-93ab-1bc0981e493d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=862781564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.862781564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.3118863923
Short name T189
Test name
Test status
Simulation time 155642122508 ps
CPU time 3762.7 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 02:08:37 PM PST 24
Peak memory 574652 kb
Host smart-c3b8adca-d7cd-4943-b39b-a4f2dd437618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3118863923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3118863923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_burst_write.4172311358
Short name T611
Test name
Test status
Simulation time 2553971160 ps
CPU time 181.98 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:08:45 PM PST 24
Peak memory 223660 kb
Host smart-650adbaf-403c-4e8d-952a-be82c89787b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172311358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.4172311358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_error.1818464294
Short name T728
Test name
Test status
Simulation time 3316182857 ps
CPU time 88.37 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 237332 kb
Host smart-02e2ebcd-a6bf-4e01-9573-12f223c59460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818464294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1818464294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.931868303
Short name T875
Test name
Test status
Simulation time 1796146012 ps
CPU time 4.84 seconds
Started Jan 07 01:05:41 PM PST 24
Finished Jan 07 01:05:48 PM PST 24
Peak memory 207336 kb
Host smart-619d9c8f-a058-4d59-b139-30dda2b348c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931868303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.931868303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3066591199
Short name T747
Test name
Test status
Simulation time 130988448722 ps
CPU time 2730.94 seconds
Started Jan 07 01:05:42 PM PST 24
Finished Jan 07 01:51:15 PM PST 24
Peak memory 474560 kb
Host smart-333e3418-b624-4748-9c13-6df493d72f6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066591199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3066591199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.3540410914
Short name T320
Test name
Test status
Simulation time 3705731352 ps
CPU time 102.56 seconds
Started Jan 07 01:05:51 PM PST 24
Finished Jan 07 01:07:36 PM PST 24
Peak memory 235520 kb
Host smart-f548f8c6-a71a-4273-99d7-aabe56e02013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540410914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3540410914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3455248953
Short name T484
Test name
Test status
Simulation time 20737831997 ps
CPU time 503.28 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:14:31 PM PST 24
Peak memory 298080 kb
Host smart-e4bf5254-d639-427f-8b37-859e06acc417
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3455248953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3455248953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_stress_all_with_rand_reset.2830085568
Short name T704
Test name
Test status
Simulation time 162205288967 ps
CPU time 3102.53 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:57:49 PM PST 24
Peak memory 453416 kb
Host smart-f16bb139-1830-4503-bc67-0a504143b2d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830085568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all_with_rand_reset.2830085568 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2150002845
Short name T508
Test name
Test status
Simulation time 946753873 ps
CPU time 4.54 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:06 PM PST 24
Peak memory 215628 kb
Host smart-f01ed94a-b5d4-4fc5-a04e-dcaf39ac9589
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150002845 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2150002845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.2960174073
Short name T74
Test name
Test status
Simulation time 389337980689 ps
CPU time 1878.32 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:37:24 PM PST 24
Peak memory 399196 kb
Host smart-8ffc70a7-7902-4351-810e-089269b9a406
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2960174073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.2960174073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.2238717296
Short name T674
Test name
Test status
Simulation time 177539421694 ps
CPU time 1510.66 seconds
Started Jan 07 01:05:40 PM PST 24
Finished Jan 07 01:30:52 PM PST 24
Peak memory 374116 kb
Host smart-1233478a-2596-4bb2-b86d-3f622f32a53e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2238717296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.2238717296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.422582604
Short name T190
Test name
Test status
Simulation time 48105358295 ps
CPU time 1263.05 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:27:02 PM PST 24
Peak memory 335824 kb
Host smart-83e6c347-d98b-414f-83e4-e77cbea7b6b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=422582604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.422582604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.3479575205
Short name T575
Test name
Test status
Simulation time 116387208336 ps
CPU time 800.52 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:19:27 PM PST 24
Peak memory 291028 kb
Host smart-386d6d8c-07e9-4f95-9dff-fa9b728f5111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3479575205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.3479575205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_app.317206403
Short name T274
Test name
Test status
Simulation time 179491856304 ps
CPU time 330.24 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:11:33 PM PST 24
Peak memory 242252 kb
Host smart-f3c66f5f-9cb7-4f3c-b559-2531e3e5cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317206403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.317206403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1279164347
Short name T121
Test name
Test status
Simulation time 50719830471 ps
CPU time 702.7 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:17:49 PM PST 24
Peak memory 232368 kb
Host smart-5485b6c8-1ad2-458b-ad84-2f9099973d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279164347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1279164347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_error.534459324
Short name T551
Test name
Test status
Simulation time 102584167879 ps
CPU time 368.2 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:12:09 PM PST 24
Peak memory 249000 kb
Host smart-352b5ac3-6780-4b43-b39e-1e97d0727488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534459324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.534459324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.816574487
Short name T64
Test name
Test status
Simulation time 1816112444 ps
CPU time 1.7 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:05:55 PM PST 24
Peak memory 207436 kb
Host smart-a89fe463-920b-44d1-b239-8dca60b642d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816574487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.816574487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.4016750762
Short name T232
Test name
Test status
Simulation time 30395605 ps
CPU time 1.25 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:01 PM PST 24
Peak memory 215760 kb
Host smart-3152a539-b6f1-446e-aeac-1e57500e75c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016750762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.4016750762 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2483924890
Short name T215
Test name
Test status
Simulation time 57472386521 ps
CPU time 2073.45 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:40:19 PM PST 24
Peak memory 430964 kb
Host smart-2fd228e5-50ef-4c5c-a885-f4d64dc799a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483924890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2483924890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.2663572148
Short name T456
Test name
Test status
Simulation time 25004368891 ps
CPU time 326.76 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:11:21 PM PST 24
Peak memory 247420 kb
Host smart-6df234b0-3828-4251-ae3b-bfdbc9a5540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663572148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2663572148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3308295429
Short name T479
Test name
Test status
Simulation time 5118892750 ps
CPU time 12.96 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:06:05 PM PST 24
Peak memory 219016 kb
Host smart-9d84654c-7c5f-45ad-8cb7-595bad561f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308295429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3308295429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.182875131
Short name T39
Test name
Test status
Simulation time 122661864839 ps
CPU time 947.51 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:21:45 PM PST 24
Peak memory 361192 kb
Host smart-1abfc1a1-c537-4b64-90bb-19712a195283
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=182875131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.182875131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2461876699
Short name T531
Test name
Test status
Simulation time 171008250 ps
CPU time 4.48 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:06:15 PM PST 24
Peak memory 215692 kb
Host smart-1c6f907b-5d37-4bef-875a-5e027622ca88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461876699 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2461876699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.2832875885
Short name T258
Test name
Test status
Simulation time 337969515 ps
CPU time 4.5 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:20 PM PST 24
Peak memory 215648 kb
Host smart-4998d214-52a2-4cb8-9a61-a318d6d43879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832875885 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.2832875885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3711670148
Short name T193
Test name
Test status
Simulation time 64157170266 ps
CPU time 1789.52 seconds
Started Jan 07 01:06:08 PM PST 24
Finished Jan 07 01:35:59 PM PST 24
Peak memory 387784 kb
Host smart-86c6819a-d573-42f0-b622-bf1aa8ea4159
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3711670148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3711670148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2908117596
Short name T173
Test name
Test status
Simulation time 96118952952 ps
CPU time 1757.02 seconds
Started Jan 07 01:06:01 PM PST 24
Finished Jan 07 01:35:21 PM PST 24
Peak memory 376216 kb
Host smart-0ea5a9b5-529d-40f9-be90-970e43b6d5a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2908117596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2908117596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.4104518134
Short name T905
Test name
Test status
Simulation time 46311519412 ps
CPU time 1298.74 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:27:25 PM PST 24
Peak memory 330788 kb
Host smart-1cb7f405-66ff-4dd0-a33d-145c757a5043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4104518134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.4104518134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.3925966798
Short name T313
Test name
Test status
Simulation time 44512022114 ps
CPU time 789.01 seconds
Started Jan 07 01:05:49 PM PST 24
Finished Jan 07 01:18:59 PM PST 24
Peak memory 300516 kb
Host smart-bb5702bc-c96b-4e5d-9cc6-5fa510dd95f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3925966798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.3925966798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3842776154
Short name T589
Test name
Test status
Simulation time 449804321680 ps
CPU time 4356.3 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 02:18:40 PM PST 24
Peak memory 558196 kb
Host smart-27820c21-a6ec-4265-91c5-2d0bd90aab72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3842776154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3842776154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_app.1308719293
Short name T176
Test name
Test status
Simulation time 30936934308 ps
CPU time 219.86 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 240184 kb
Host smart-8a936ca9-88f7-4342-92a2-f81da5f9a1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308719293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1308719293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3441906233
Short name T291
Test name
Test status
Simulation time 35404304781 ps
CPU time 559.18 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:15:21 PM PST 24
Peak memory 230564 kb
Host smart-ce9fda2d-d30f-47ca-9b63-d34bbb0d55ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441906233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3441906233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1304247628
Short name T614
Test name
Test status
Simulation time 17882569929 ps
CPU time 95.96 seconds
Started Jan 07 01:05:48 PM PST 24
Finished Jan 07 01:07:25 PM PST 24
Peak memory 229240 kb
Host smart-eef9478d-b31d-4abe-b0fc-861b0102a7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304247628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1304247628 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.2754078019
Short name T311
Test name
Test status
Simulation time 66461053 ps
CPU time 1.35 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 215612 kb
Host smart-56f3c37d-f2b3-498c-a3c4-ba3733d42f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754078019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2754078019 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.895655149
Short name T375
Test name
Test status
Simulation time 16346224755 ps
CPU time 1096.51 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:24:02 PM PST 24
Peak memory 338316 kb
Host smart-04d7090d-a98f-45eb-9640-9b8fe9cb32fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895655149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an
d_output.895655149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3524859811
Short name T45
Test name
Test status
Simulation time 50047825387 ps
CPU time 331.06 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:11:40 PM PST 24
Peak memory 245840 kb
Host smart-be5425e9-be87-45f1-8218-7c780e16f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524859811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3524859811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2660721727
Short name T904
Test name
Test status
Simulation time 457247448 ps
CPU time 22.57 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:06:29 PM PST 24
Peak memory 218084 kb
Host smart-1b4a4d38-e518-4127-876f-7d6313a4e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660721727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2660721727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.3813547147
Short name T442
Test name
Test status
Simulation time 3145436391 ps
CPU time 254.34 seconds
Started Jan 07 01:05:44 PM PST 24
Finished Jan 07 01:10:00 PM PST 24
Peak memory 264860 kb
Host smart-f7345a5d-9791-40ea-a059-d9230332df8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3813547147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3813547147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_stress_all_with_rand_reset.4126557672
Short name T863
Test name
Test status
Simulation time 152933928745 ps
CPU time 703.29 seconds
Started Jan 07 01:06:08 PM PST 24
Finished Jan 07 01:17:53 PM PST 24
Peak memory 288020 kb
Host smart-8b00bc5b-7961-45db-b619-a537f5dc7ebf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126557672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.4126557672 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.247662071
Short name T925
Test name
Test status
Simulation time 63242414 ps
CPU time 3.73 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 215744 kb
Host smart-daeff467-52c9-4bb9-835c-50b231d4fd4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247662071 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_test_vectors_kmac.247662071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2579984682
Short name T850
Test name
Test status
Simulation time 635161847 ps
CPU time 4.65 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:06 PM PST 24
Peak memory 215676 kb
Host smart-931eeac7-e20c-4cbd-b298-61bc7b309ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579984682 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2579984682 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3838064159
Short name T596
Test name
Test status
Simulation time 83775957011 ps
CPU time 1756.03 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:35:25 PM PST 24
Peak memory 389076 kb
Host smart-102e7ddb-4846-4d4b-bbed-9b6aab08af3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3838064159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3838064159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2824276345
Short name T517
Test name
Test status
Simulation time 18037621251 ps
CPU time 1474.51 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:30:50 PM PST 24
Peak memory 375968 kb
Host smart-863395f9-b3c8-44bc-ab58-9dcb76d4c4cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2824276345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2824276345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.1055127402
Short name T638
Test name
Test status
Simulation time 13682892289 ps
CPU time 1036.83 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:23:23 PM PST 24
Peak memory 330120 kb
Host smart-92d4d956-e5d8-481d-8bbe-3a15a854117f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1055127402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.1055127402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3263645276
Short name T439
Test name
Test status
Simulation time 66649348618 ps
CPU time 890.24 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:21:06 PM PST 24
Peak memory 291004 kb
Host smart-9a359743-e3ff-4c20-aaf1-f32353d502cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3263645276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3263645276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.4026779708
Short name T868
Test name
Test status
Simulation time 505724952703 ps
CPU time 4514.89 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 02:21:22 PM PST 24
Peak memory 648824 kb
Host smart-fa5881ed-6e74-4ab2-835b-6cfa2cf7639e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4026779708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.4026779708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_alert_test.2103807393
Short name T437
Test name
Test status
Simulation time 20435998 ps
CPU time 0.81 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 205140 kb
Host smart-02c7484f-b92c-4ed0-9b51-c07d013641c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103807393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2103807393 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1679802588
Short name T142
Test name
Test status
Simulation time 7302008514 ps
CPU time 161.43 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:08:52 PM PST 24
Peak memory 236220 kb
Host smart-6e7cf9bd-f6ef-42ce-a679-8ab3256e0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679802588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1679802588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3833158465
Short name T727
Test name
Test status
Simulation time 8332600374 ps
CPU time 76.54 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:07:26 PM PST 24
Peak memory 220932 kb
Host smart-1e7982a3-5974-4452-913d-5fb4791f8f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833158465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3833158465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.983318735
Short name T104
Test name
Test status
Simulation time 38522364607 ps
CPU time 175.77 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:09:07 PM PST 24
Peak memory 234972 kb
Host smart-180aca26-38c0-4585-b4b7-38774490b3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983318735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.983318735 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.2890495855
Short name T8
Test name
Test status
Simulation time 1141553097 ps
CPU time 10.2 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 223944 kb
Host smart-7573c340-c139-4d4c-9e2b-3f46d1e84a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890495855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2890495855 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_sideload.2031728037
Short name T342
Test name
Test status
Simulation time 10883771286 ps
CPU time 237.89 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:10:11 PM PST 24
Peak memory 239328 kb
Host smart-f66acf24-173d-43db-bb36-7a250024a529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031728037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2031728037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1552320049
Short name T709
Test name
Test status
Simulation time 25896942 ps
CPU time 1.62 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:09 PM PST 24
Peak memory 215596 kb
Host smart-0010b1a6-e438-421c-bfc1-8d3f25471d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552320049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1552320049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.3956760541
Short name T760
Test name
Test status
Simulation time 93581552815 ps
CPU time 191.52 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:08:56 PM PST 24
Peak memory 240280 kb
Host smart-b08f288d-228a-4507-9dc2-e83da88b53bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3956760541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3956760541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1203562856
Short name T641
Test name
Test status
Simulation time 330531712 ps
CPU time 4.38 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 209012 kb
Host smart-45a2b27f-d4d8-4e54-a750-e687060c40f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203562856 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1203562856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.2501528806
Short name T558
Test name
Test status
Simulation time 37283865112 ps
CPU time 1462.08 seconds
Started Jan 07 01:05:53 PM PST 24
Finished Jan 07 01:30:18 PM PST 24
Peak memory 387872 kb
Host smart-08aa0e5f-7042-436e-859b-90ab08347bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2501528806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2501528806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.3090771372
Short name T837
Test name
Test status
Simulation time 630361762126 ps
CPU time 1709.33 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:34:44 PM PST 24
Peak memory 392108 kb
Host smart-883e4bf9-df85-4d6c-a812-490ca20ee56b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3090771372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3090771372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.33381696
Short name T326
Test name
Test status
Simulation time 95464667320 ps
CPU time 1243.17 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:26:56 PM PST 24
Peak memory 333348 kb
Host smart-5fd4150e-9532-473c-ac11-d95413469be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=33381696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.33381696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.281704533
Short name T476
Test name
Test status
Simulation time 44102382793 ps
CPU time 947.66 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:21:55 PM PST 24
Peak memory 300900 kb
Host smart-80f11764-de76-46fe-ab59-9fff0d5bdc5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=281704533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.281704533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.39943169
Short name T238
Test name
Test status
Simulation time 281012293572 ps
CPU time 3800.7 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 02:09:36 PM PST 24
Peak memory 643396 kb
Host smart-fa205887-c0dd-4700-aa6f-1de92542a024
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=39943169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.39943169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3011605334
Short name T892
Test name
Test status
Simulation time 584746003192 ps
CPU time 3993.75 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 02:12:52 PM PST 24
Peak memory 565464 kb
Host smart-e1d464a5-19c8-451b-b377-cdc068328fd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3011605334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3011605334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_app.1709966371
Short name T229
Test name
Test status
Simulation time 3051574236 ps
CPU time 71.23 seconds
Started Jan 07 01:03:57 PM PST 24
Finished Jan 07 01:05:12 PM PST 24
Peak memory 227368 kb
Host smart-330a08d6-a789-422b-9a0d-960640a47d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709966371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1709966371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.3101957622
Short name T772
Test name
Test status
Simulation time 11239673348 ps
CPU time 210.78 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 01:07:39 PM PST 24
Peak memory 239756 kb
Host smart-21a300ce-caac-4f90-8806-f5814dfbac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101957622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3101957622 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.598010159
Short name T123
Test name
Test status
Simulation time 15326080574 ps
CPU time 457.49 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:11:37 PM PST 24
Peak memory 229208 kb
Host smart-a7003b6d-8300-42e7-b27c-82b85cdf2545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598010159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.598010159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.3485963944
Short name T482
Test name
Test status
Simulation time 1051603930 ps
CPU time 15.82 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 223616 kb
Host smart-70270641-f7ce-493b-b682-ae5f91e9fbd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3485963944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3485963944 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.3577156663
Short name T520
Test name
Test status
Simulation time 2192276502 ps
CPU time 33.76 seconds
Started Jan 07 01:03:57 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 223776 kb
Host smart-0cdbf90f-5589-42c0-8ea4-7acbdcaf4de3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577156663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3577156663 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.537484054
Short name T35
Test name
Test status
Simulation time 23164271200 ps
CPU time 16.93 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 216716 kb
Host smart-f777387d-5173-449d-9e3a-89210c845998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537484054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.537484054 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.1670650182
Short name T518
Test name
Test status
Simulation time 4205898906 ps
CPU time 93.98 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:05:22 PM PST 24
Peak memory 229008 kb
Host smart-aecbfce8-f7a3-45c6-8ab4-6707e0e5e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670650182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1670650182 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.1420980593
Short name T540
Test name
Test status
Simulation time 14673672641 ps
CPU time 259.27 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:08:17 PM PST 24
Peak memory 254004 kb
Host smart-dbfc540c-702a-4e00-a663-1f4440323651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420980593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1420980593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.895007026
Short name T453
Test name
Test status
Simulation time 8589765842 ps
CPU time 5.82 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 207296 kb
Host smart-ada69628-97f5-4f5e-92a2-ae609ed8a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895007026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.895007026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.291667158
Short name T920
Test name
Test status
Simulation time 421248261 ps
CPU time 9.92 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 223844 kb
Host smart-b844781b-b3f0-43d8-a492-0a986338f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291667158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.291667158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.29149536
Short name T245
Test name
Test status
Simulation time 310803867812 ps
CPU time 1771.67 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:33:37 PM PST 24
Peak memory 372152 kb
Host smart-4cbf25e2-46bd-4384-b1a6-543badc90aab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29149536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_
output.29149536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3637056911
Short name T452
Test name
Test status
Simulation time 25550508258 ps
CPU time 117.01 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:05:46 PM PST 24
Peak memory 230948 kb
Host smart-76ec5d5a-daca-476e-9b7a-3925473913be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637056911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3637056911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1952078903
Short name T899
Test name
Test status
Simulation time 2686359934 ps
CPU time 28.15 seconds
Started Jan 07 01:04:02 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 223872 kb
Host smart-50c77a8a-2c32-48c7-86a0-0a60394561de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952078903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1952078903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2405079181
Short name T586
Test name
Test status
Simulation time 861003732 ps
CPU time 44.05 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:05:03 PM PST 24
Peak memory 218880 kb
Host smart-9dfa0b72-6ce7-4d79-89e4-c430bb045a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405079181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2405079181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.2337167945
Short name T854
Test name
Test status
Simulation time 50768815516 ps
CPU time 1362.97 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:26:36 PM PST 24
Peak memory 333844 kb
Host smart-1846ce40-c191-47da-92e7-9c4bc25bc791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337167945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.2337167945 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.1933112225
Short name T742
Test name
Test status
Simulation time 327814075 ps
CPU time 4.15 seconds
Started Jan 07 01:03:45 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 215716 kb
Host smart-e57349b9-c4bd-427c-a0d3-ae99e2624f64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933112225 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.1933112225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2836293951
Short name T800
Test name
Test status
Simulation time 18915041848 ps
CPU time 1506.13 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:29:22 PM PST 24
Peak memory 390140 kb
Host smart-b1351f6f-8da9-4ddc-aa5a-87e35ef3c7ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2836293951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2836293951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.3222602840
Short name T646
Test name
Test status
Simulation time 95220900380 ps
CPU time 1860.58 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:35:11 PM PST 24
Peak memory 372996 kb
Host smart-93c2273d-dab1-422c-b34b-032792b712cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3222602840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3222602840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3269540025
Short name T650
Test name
Test status
Simulation time 28245856692 ps
CPU time 1122.21 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:23:12 PM PST 24
Peak memory 333612 kb
Host smart-8f025a9f-535d-411e-b4d3-a4448044e336
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3269540025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3269540025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.1463712082
Short name T675
Test name
Test status
Simulation time 33188568298 ps
CPU time 931.67 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:19:59 PM PST 24
Peak memory 298028 kb
Host smart-9aeb98e1-e60b-407f-8293-59dcd55f7b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1463712082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.1463712082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.902464274
Short name T515
Test name
Test status
Simulation time 352639819403 ps
CPU time 4689.06 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 02:22:21 PM PST 24
Peak memory 653636 kb
Host smart-d7f944b7-57b0-4296-bde1-81c6b84fa250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=902464274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.902464274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.401792126
Short name T432
Test name
Test status
Simulation time 153433917368 ps
CPU time 3858.83 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 02:08:38 PM PST 24
Peak memory 581248 kb
Host smart-92cf69bf-75b9-452e-a260-942cdc446cc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=401792126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.401792126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.73345816
Short name T516
Test name
Test status
Simulation time 37327016 ps
CPU time 0.84 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:04:28 PM PST 24
Peak memory 205220 kb
Host smart-38004103-31df-4ad2-8e16-5bcf9db1b94d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73345816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.73345816 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.1200708632
Short name T244
Test name
Test status
Simulation time 5977020807 ps
CPU time 134.84 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:06:04 PM PST 24
Peak memory 233652 kb
Host smart-0d10472a-94af-4ed1-87b4-322f6bfe458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200708632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1200708632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1101348394
Short name T555
Test name
Test status
Simulation time 3093258670 ps
CPU time 51.16 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:04:40 PM PST 24
Peak memory 223304 kb
Host smart-c19bea9c-29de-4261-9345-4258e06590d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101348394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1101348394 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3703809405
Short name T924
Test name
Test status
Simulation time 159687454206 ps
CPU time 476.7 seconds
Started Jan 07 01:03:46 PM PST 24
Finished Jan 07 01:11:49 PM PST 24
Peak memory 229656 kb
Host smart-17caabdc-f1f4-4a27-a936-2a97f4b4b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703809405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3703809405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2225163767
Short name T364
Test name
Test status
Simulation time 2078388367 ps
CPU time 26.65 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:04:53 PM PST 24
Peak memory 223696 kb
Host smart-ecf42dc7-c8b0-4fbc-acba-21d0f4149fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225163767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2225163767 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3216962098
Short name T235
Test name
Test status
Simulation time 15346381407 ps
CPU time 112.94 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 230948 kb
Host smart-8bb318aa-0046-4b7e-beac-24ab66565cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216962098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3216962098 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.731371929
Short name T34
Test name
Test status
Simulation time 142514575147 ps
CPU time 387.1 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:10:23 PM PST 24
Peak memory 257688 kb
Host smart-c8f90504-cce9-4f7f-b3b0-fa447f5c5bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731371929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.731371929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.87115848
Short name T446
Test name
Test status
Simulation time 130994499 ps
CPU time 1.14 seconds
Started Jan 07 01:04:38 PM PST 24
Finished Jan 07 01:04:42 PM PST 24
Peak memory 215528 kb
Host smart-21650714-1cd1-44d2-b909-8863af6dd458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87115848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.87115848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.701907720
Short name T628
Test name
Test status
Simulation time 71156477083 ps
CPU time 1973.25 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:36:56 PM PST 24
Peak memory 421528 kb
Host smart-5259e919-3bf3-4f1b-b106-4801cd70617d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701907720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and
_output.701907720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1862781410
Short name T890
Test name
Test status
Simulation time 55825883995 ps
CPU time 226.4 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:07:36 PM PST 24
Peak memory 243028 kb
Host smart-f93a0324-c248-4788-b090-b879c7c2fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862781410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1862781410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.411492670
Short name T694
Test name
Test status
Simulation time 11029756182 ps
CPU time 58.38 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:58 PM PST 24
Peak memory 222432 kb
Host smart-d6024f3e-1fe3-469e-bea1-82078216db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411492670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.411492670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.2047073644
Short name T183
Test name
Test status
Simulation time 1159214438 ps
CPU time 25.48 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:19 PM PST 24
Peak memory 223884 kb
Host smart-ab51b3a6-4eb0-40b5-a05d-057a0ddd8033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047073644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2047073644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1501687905
Short name T908
Test name
Test status
Simulation time 196284279638 ps
CPU time 1093.52 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:22:34 PM PST 24
Peak memory 345044 kb
Host smart-0b3c1f9b-d5b8-4797-9822-c0519c53f715
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1501687905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1501687905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.1713177076
Short name T870
Test name
Test status
Simulation time 461451703433 ps
CPU time 387.07 seconds
Started Jan 07 01:04:14 PM PST 24
Finished Jan 07 01:10:44 PM PST 24
Peak memory 254008 kb
Host smart-61d376be-f532-4a77-97ad-2da1b0568142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713177076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.1713177076 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1911497457
Short name T281
Test name
Test status
Simulation time 275351611 ps
CPU time 4.24 seconds
Started Jan 07 01:03:46 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 215816 kb
Host smart-505f6d0e-fcfa-4cc2-8d84-075003bbb1f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911497457 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1911497457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1794073308
Short name T492
Test name
Test status
Simulation time 232368771 ps
CPU time 3.67 seconds
Started Jan 07 01:03:45 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 208620 kb
Host smart-52ef1e72-7b06-43e3-8ced-6ff7d8783bca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794073308 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1794073308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3061009061
Short name T230
Test name
Test status
Simulation time 64954409768 ps
CPU time 1730 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:32:39 PM PST 24
Peak memory 377168 kb
Host smart-ab3a4475-8b98-436c-aae9-f92c51e44169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3061009061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3061009061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.2650028460
Short name T550
Test name
Test status
Simulation time 229828030994 ps
CPU time 1375.95 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:26:47 PM PST 24
Peak memory 329728 kb
Host smart-537bbea0-f17a-491b-a75c-db6a8aa3ddfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2650028460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.2650028460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.36554803
Short name T845
Test name
Test status
Simulation time 19506573225 ps
CPU time 799.93 seconds
Started Jan 07 01:03:59 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 296104 kb
Host smart-dd8e1d56-b5cc-46c4-8fc4-4053615fec34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=36554803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.36554803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1279000205
Short name T270
Test name
Test status
Simulation time 177823828345 ps
CPU time 4548.73 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 02:19:43 PM PST 24
Peak memory 653536 kb
Host smart-5b3f4de9-5ec2-41e1-a641-fb2e3a10bb93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1279000205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1279000205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.2302916087
Short name T393
Test name
Test status
Simulation time 221641091918 ps
CPU time 4106.69 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 02:12:24 PM PST 24
Peak memory 546732 kb
Host smart-3f6e4d13-1b97-4c6f-a05d-f22b2cfd64e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2302916087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2302916087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.4029309208
Short name T591
Test name
Test status
Simulation time 49107480 ps
CPU time 0.77 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 205204 kb
Host smart-2ed7ddff-caee-434c-a05f-c27c55c85930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029309208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4029309208 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.2536229694
Short name T218
Test name
Test status
Simulation time 1296990538 ps
CPU time 47.81 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:05:19 PM PST 24
Peak memory 224004 kb
Host smart-4382fed8-8389-41be-84d4-e4ebdf689664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536229694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2536229694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2620123910
Short name T796
Test name
Test status
Simulation time 4046446544 ps
CPU time 131.91 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:06:38 PM PST 24
Peak memory 234416 kb
Host smart-d2e48d6a-07ef-4adc-8767-7a73986e9144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620123910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2620123910 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.4129253302
Short name T576
Test name
Test status
Simulation time 6094652523 ps
CPU time 123.45 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 01:06:33 PM PST 24
Peak memory 223352 kb
Host smart-29445e3b-f38a-4c20-aeb5-f0dc1befd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129253302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.4129253302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1939805193
Short name T790
Test name
Test status
Simulation time 831412917 ps
CPU time 19.94 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:53 PM PST 24
Peak memory 223752 kb
Host smart-ecf4ef03-6137-440f-9b0e-36efe1c03334
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1939805193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1939805193 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3271569319
Short name T242
Test name
Test status
Simulation time 18416032897 ps
CPU time 48.37 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:05:10 PM PST 24
Peak memory 223932 kb
Host smart-74199b7f-b1e5-4aa2-989b-5b993565ca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271569319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3271569319 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2977620425
Short name T331
Test name
Test status
Simulation time 2418237705 ps
CPU time 121.93 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 234712 kb
Host smart-f01f6a5b-38e2-4d2b-b024-ac81f3600745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977620425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2977620425 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.901025708
Short name T90
Test name
Test status
Simulation time 6761528610 ps
CPU time 84.64 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:05:52 PM PST 24
Peak memory 236860 kb
Host smart-6809df2e-b136-40e3-98ea-46579d88cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901025708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.901025708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.2223496045
Short name T309
Test name
Test status
Simulation time 170214780 ps
CPU time 1.54 seconds
Started Jan 07 01:04:05 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 207088 kb
Host smart-e57984cb-a1dd-493e-9429-2c8e677ec4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223496045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2223496045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.2026533927
Short name T267
Test name
Test status
Simulation time 408922445 ps
CPU time 5.74 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 216772 kb
Host smart-d8dba6fa-fa21-4b40-b5e2-d1c65f386c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026533927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2026533927 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_mubi.3451025002
Short name T312
Test name
Test status
Simulation time 5544245069 ps
CPU time 103.78 seconds
Started Jan 07 01:04:10 PM PST 24
Finished Jan 07 01:05:56 PM PST 24
Peak memory 230748 kb
Host smart-500b19e1-87af-4777-aed0-fb41e02d0666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451025002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3451025002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2536417177
Short name T883
Test name
Test status
Simulation time 39123547705 ps
CPU time 189.45 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 01:07:23 PM PST 24
Peak memory 234880 kb
Host smart-9c1ec761-bef4-4853-9e44-ff3600276fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536417177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2536417177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1471958363
Short name T818
Test name
Test status
Simulation time 1904179552 ps
CPU time 13.42 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:04:25 PM PST 24
Peak memory 218632 kb
Host smart-44b26d1a-5de1-4f22-b094-2e7332c02569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471958363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1471958363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1746782891
Short name T762
Test name
Test status
Simulation time 41697200302 ps
CPU time 816.48 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 312968 kb
Host smart-215be433-9950-43c0-a6e6-a456ec944e4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1746782891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1746782891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.1925990515
Short name T352
Test name
Test status
Simulation time 73656651669 ps
CPU time 299.53 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:09:21 PM PST 24
Peak memory 248828 kb
Host smart-3f2cf859-542e-4cba-86e1-6afb91df136a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925990515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.1925990515 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3677573674
Short name T389
Test name
Test status
Simulation time 252419331 ps
CPU time 4.7 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 215716 kb
Host smart-ac7f8e0d-f1cf-46ae-b341-69aa66712007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677573674 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3677573674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3757086697
Short name T691
Test name
Test status
Simulation time 129805301 ps
CPU time 3.66 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 215732 kb
Host smart-d94bfa8d-5b20-474d-99bf-bfaaed1c76a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757086697 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3757086697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.908018044
Short name T534
Test name
Test status
Simulation time 262423463897 ps
CPU time 1900.31 seconds
Started Jan 07 01:04:36 PM PST 24
Finished Jan 07 01:36:21 PM PST 24
Peak memory 395828 kb
Host smart-13160ed3-6ae8-4541-8e48-0c7c694fc483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=908018044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.908018044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3340909534
Short name T581
Test name
Test status
Simulation time 17780361415 ps
CPU time 1527.26 seconds
Started Jan 07 01:04:22 PM PST 24
Finished Jan 07 01:29:53 PM PST 24
Peak memory 375140 kb
Host smart-0ffb1a8e-4d39-425c-8c1e-a8ef640f342c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3340909534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3340909534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1578006511
Short name T301
Test name
Test status
Simulation time 196370342038 ps
CPU time 1285.07 seconds
Started Jan 07 01:04:22 PM PST 24
Finished Jan 07 01:25:51 PM PST 24
Peak memory 336128 kb
Host smart-95b8c05e-7b03-48e8-90c5-7fef6320f957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1578006511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1578006511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3123960839
Short name T885
Test name
Test status
Simulation time 49239000701 ps
CPU time 926.4 seconds
Started Jan 07 01:04:22 PM PST 24
Finished Jan 07 01:19:52 PM PST 24
Peak memory 292660 kb
Host smart-5c6f5ad5-6d92-487f-a382-3fdb73aee81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3123960839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3123960839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.4024302577
Short name T339
Test name
Test status
Simulation time 644847211936 ps
CPU time 4726.2 seconds
Started Jan 07 01:04:20 PM PST 24
Finished Jan 07 02:23:15 PM PST 24
Peak memory 663440 kb
Host smart-890ac6ea-cfbc-4a7a-af3d-931aac25947d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4024302577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.4024302577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3187634658
Short name T384
Test name
Test status
Simulation time 2671265290468 ps
CPU time 4214 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 02:14:42 PM PST 24
Peak memory 550048 kb
Host smart-a5e03081-9fdc-45ef-a2e7-164f67dbf99c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3187634658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3187634658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.1328088475
Short name T33
Test name
Test status
Simulation time 26371110 ps
CPU time 0.79 seconds
Started Jan 07 01:04:25 PM PST 24
Finished Jan 07 01:04:29 PM PST 24
Peak memory 205076 kb
Host smart-9058bd7c-afb0-485f-ae2a-95c2df17ddd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328088475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1328088475 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3723812628
Short name T294
Test name
Test status
Simulation time 6187681706 ps
CPU time 172.23 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:07:29 PM PST 24
Peak memory 240328 kb
Host smart-0a0c1dd2-f448-4be7-bb05-29d5fda7a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723812628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3723812628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1951221435
Short name T919
Test name
Test status
Simulation time 5114795585 ps
CPU time 189.89 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 01:07:32 PM PST 24
Peak memory 240908 kb
Host smart-b3af218c-0a18-4edf-8206-f9210a3b2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951221435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1951221435 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.1627152512
Short name T577
Test name
Test status
Simulation time 17243992772 ps
CPU time 342.24 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:10:12 PM PST 24
Peak memory 228432 kb
Host smart-c20c01a2-6c45-444d-bdf3-3480588ced47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627152512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1627152512 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.3197925510
Short name T350
Test name
Test status
Simulation time 1164617917 ps
CPU time 32.64 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 223672 kb
Host smart-1d14cab2-4b23-47d1-b1c2-0588f1851de8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197925510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3197925510 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2274438047
Short name T676
Test name
Test status
Simulation time 154803747 ps
CPU time 11.24 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 01:04:33 PM PST 24
Peak memory 223620 kb
Host smart-a6a63bce-79a9-4065-9406-02d6b1c0eaee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274438047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2274438047 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3996174235
Short name T298
Test name
Test status
Simulation time 2845288672 ps
CPU time 22.98 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:04:58 PM PST 24
Peak memory 216656 kb
Host smart-baacfdc4-8d51-4b51-9c5c-93fdb882b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996174235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3996174235 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.4226714927
Short name T478
Test name
Test status
Simulation time 9383266302 ps
CPU time 124.73 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:06:42 PM PST 24
Peak memory 231728 kb
Host smart-8a74d6b3-ebe0-4d10-aff8-77f44a1e71cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226714927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.4226714927 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.4058953078
Short name T749
Test name
Test status
Simulation time 14038343197 ps
CPU time 182.79 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:07:40 PM PST 24
Peak memory 250160 kb
Host smart-b6bd3043-27d0-4267-9491-9a6c71285991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058953078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4058953078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1514674238
Short name T661
Test name
Test status
Simulation time 1130171834 ps
CPU time 5.78 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:04:38 PM PST 24
Peak memory 207344 kb
Host smart-a011eca9-2191-4400-8a9e-3dda117c0c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514674238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1514674238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1181557701
Short name T426
Test name
Test status
Simulation time 24311507 ps
CPU time 1.21 seconds
Started Jan 07 01:04:21 PM PST 24
Finished Jan 07 01:04:25 PM PST 24
Peak memory 215716 kb
Host smart-70bcedb4-2bc3-44ba-8769-51b1351b0b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181557701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1181557701 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.3116941135
Short name T620
Test name
Test status
Simulation time 38743301587 ps
CPU time 512.99 seconds
Started Jan 07 01:04:20 PM PST 24
Finished Jan 07 01:12:56 PM PST 24
Peak memory 269108 kb
Host smart-e1142b2a-daa4-46b2-a70c-530e7bb13e0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116941135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.3116941135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_smoke.4038647819
Short name T431
Test name
Test status
Simulation time 3635056118 ps
CPU time 56.66 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:05:24 PM PST 24
Peak memory 215792 kb
Host smart-206e9877-4ae7-48b7-bafd-e5b324615f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038647819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.4038647819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.3353733304
Short name T41
Test name
Test status
Simulation time 35462008141 ps
CPU time 749.24 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:16:47 PM PST 24
Peak memory 292668 kb
Host smart-97c3e814-e60c-4e9e-b3e4-0209d38018e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3353733304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3353733304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.3696064756
Short name T332
Test name
Test status
Simulation time 167839095959 ps
CPU time 794.68 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:17:53 PM PST 24
Peak memory 306244 kb
Host smart-15488161-ee59-42f4-8396-455ec9f43e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696064756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.3696064756 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3318394034
Short name T889
Test name
Test status
Simulation time 452825840 ps
CPU time 3.85 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:04:25 PM PST 24
Peak memory 208516 kb
Host smart-39b38f7e-ef66-402b-9c77-3306989818a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318394034 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3318394034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.3129079924
Short name T327
Test name
Test status
Simulation time 70223345 ps
CPU time 3.95 seconds
Started Jan 07 01:04:10 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 208896 kb
Host smart-d37be687-4be4-4edb-a2d9-3b95228cc639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129079924 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.3129079924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.3330664697
Short name T542
Test name
Test status
Simulation time 412999918843 ps
CPU time 2130.57 seconds
Started Jan 07 01:04:17 PM PST 24
Finished Jan 07 01:39:51 PM PST 24
Peak memory 399436 kb
Host smart-ae645541-6397-4223-a2eb-2f5e4b113b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3330664697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.3330664697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.1178302404
Short name T196
Test name
Test status
Simulation time 18112091542 ps
CPU time 1467.56 seconds
Started Jan 07 01:04:26 PM PST 24
Finished Jan 07 01:28:57 PM PST 24
Peak memory 367292 kb
Host smart-a66690ba-6d35-41a2-a17e-b97f2354a221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1178302404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.1178302404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1231174476
Short name T306
Test name
Test status
Simulation time 34374901886 ps
CPU time 905.76 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:19:36 PM PST 24
Peak memory 294284 kb
Host smart-813ba2de-238e-4698-9ce0-a5ee94285671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1231174476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1231174476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.174124848
Short name T451
Test name
Test status
Simulation time 203310687803 ps
CPU time 3851.42 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 02:08:34 PM PST 24
Peak memory 647784 kb
Host smart-3e0932c7-b90f-43d8-9e01-7ab0404bc2d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=174124848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.174124848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3001894417
Short name T699
Test name
Test status
Simulation time 204418382636 ps
CPU time 3290.06 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:59:10 PM PST 24
Peak memory 554700 kb
Host smart-d6c1e771-a168-4b2d-98bc-49e093de2469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3001894417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3001894417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.617581035
Short name T886
Test name
Test status
Simulation time 16305428 ps
CPU time 0.79 seconds
Started Jan 07 01:04:42 PM PST 24
Finished Jan 07 01:04:45 PM PST 24
Peak memory 205196 kb
Host smart-7a36cc7c-3057-439b-9cd3-6ca8a4e3d8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617581035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.617581035 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3740901300
Short name T143
Test name
Test status
Simulation time 5461281559 ps
CPU time 235.71 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 01:08:18 PM PST 24
Peak memory 244024 kb
Host smart-7e8ca946-ab1f-4206-911e-946c08465e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740901300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3740901300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.710735193
Short name T71
Test name
Test status
Simulation time 687906124 ps
CPU time 15.29 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 219156 kb
Host smart-6660a69f-1763-4cda-9744-a0b852f08109
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710735193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.710735193 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2581696811
Short name T345
Test name
Test status
Simulation time 20800402400 ps
CPU time 50.92 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:05:35 PM PST 24
Peak memory 216924 kb
Host smart-a915a32e-6b2b-4e37-9075-b1d97a5bb306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581696811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2581696811 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.408379701
Short name T805
Test name
Test status
Simulation time 56457114119 ps
CPU time 259.69 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:09:03 PM PST 24
Peak memory 244204 kb
Host smart-87222e7c-d099-4d6f-b022-31aee0a8f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408379701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.408379701 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_key_error.3914588722
Short name T626
Test name
Test status
Simulation time 1352850738 ps
CPU time 3.68 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:38 PM PST 24
Peak memory 207260 kb
Host smart-4125c3c6-ad26-40ae-857f-9aa462661906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914588722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3914588722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2493909021
Short name T496
Test name
Test status
Simulation time 35947962 ps
CPU time 1.21 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 215704 kb
Host smart-97a30ef5-3ab3-4886-bd57-060900b4fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493909021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2493909021 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.706706353
Short name T464
Test name
Test status
Simulation time 151852755534 ps
CPU time 957.28 seconds
Started Jan 07 01:04:36 PM PST 24
Finished Jan 07 01:20:37 PM PST 24
Peak memory 302512 kb
Host smart-0f7641a9-91bd-4073-869b-30b1ac0eb560
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706706353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and
_output.706706353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.163860707
Short name T376
Test name
Test status
Simulation time 7488903784 ps
CPU time 190.89 seconds
Started Jan 07 01:04:43 PM PST 24
Finished Jan 07 01:07:56 PM PST 24
Peak memory 240312 kb
Host smart-e975e614-b351-49c3-970d-910910ccc640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163860707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.163860707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.268779799
Short name T413
Test name
Test status
Simulation time 77981777134 ps
CPU time 372.7 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:10:51 PM PST 24
Peak memory 246580 kb
Host smart-758bf6a5-b0ae-4055-9cbc-fee8e7319c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268779799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.268779799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1638216398
Short name T88
Test name
Test status
Simulation time 442880380813 ps
CPU time 1245.23 seconds
Started Jan 07 01:04:55 PM PST 24
Finished Jan 07 01:25:42 PM PST 24
Peak memory 337164 kb
Host smart-42e91b73-2632-4e28-98d0-13f1bd7a37ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638216398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1638216398 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.411815733
Short name T400
Test name
Test status
Simulation time 122908184 ps
CPU time 4.16 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 215700 kb
Host smart-e0e1e293-e492-4adb-a542-2ac7fc258e4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411815733 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.kmac_test_vectors_kmac.411815733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.870434168
Short name T217
Test name
Test status
Simulation time 967215780 ps
CPU time 4.76 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:38 PM PST 24
Peak memory 215632 kb
Host smart-49ee33f8-d17f-4f5e-b368-d34de5e15b76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870434168 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_test_vectors_kmac_xof.870434168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1594588891
Short name T880
Test name
Test status
Simulation time 169949214164 ps
CPU time 1865.75 seconds
Started Jan 07 01:04:48 PM PST 24
Finished Jan 07 01:35:55 PM PST 24
Peak memory 387712 kb
Host smart-60d5c7f2-8243-42b0-aea1-5cbffa64575c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1594588891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1594588891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.4107588434
Short name T927
Test name
Test status
Simulation time 63382269856 ps
CPU time 1805.24 seconds
Started Jan 07 01:04:29 PM PST 24
Finished Jan 07 01:34:43 PM PST 24
Peak memory 372112 kb
Host smart-ece22456-e77b-4c7b-8ee0-536c4aa46e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4107588434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.4107588434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3635385671
Short name T252
Test name
Test status
Simulation time 202435930622 ps
CPU time 1337.88 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:26:51 PM PST 24
Peak memory 332376 kb
Host smart-225466a4-b67e-46d5-ac04-ea18241d0d23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3635385671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3635385671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3809543719
Short name T335
Test name
Test status
Simulation time 156587759551 ps
CPU time 942.11 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:20:25 PM PST 24
Peak memory 294752 kb
Host smart-d3ee7d97-133e-4e39-aae4-0e52e39e74f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3809543719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3809543719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.340572213
Short name T856
Test name
Test status
Simulation time 527430623207 ps
CPU time 5267.96 seconds
Started Jan 07 01:04:47 PM PST 24
Finished Jan 07 02:32:37 PM PST 24
Peak memory 657652 kb
Host smart-9fe467aa-78a6-49ef-9379-300f331f00b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=340572213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.340572213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3685809978
Short name T251
Test name
Test status
Simulation time 43007743111 ps
CPU time 3331.03 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 02:00:09 PM PST 24
Peak memory 557568 kb
Host smart-5f70e38a-2541-4921-a19b-8b99d67586bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3685809978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3685809978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%