Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101501733	1			T47	8		T53	5		T48	1
all_values[1]	101501733	1			T47	8		T53	5		T48	1
all_values[2]	101501733	1			T47	8		T53	5		T48	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683007

1

T47

7

T53

7

T48

3

auto[1]

303822192

1

T47

17

T53

8

T54

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302946156

1

T47

12

T53

15

T48

3

auto[1]

1559043

1

T47

12

T51

9

T52

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	205330	1			T47	1		T53	2		T48	1
all_values[0]	auto[0]	auto[1]	2367	1			T47	1		T51	1		T52	1
all_values[0]	auto[1]	auto[0]	100776722	1			T47	3		T53	3		T54	2
all_values[0]	auto[1]	auto[1]	517314	1			T47	3		T51	2		T52	1
all_values[1]	auto[0]	auto[0]	236330	1			T47	1		T53	4		T48	1
all_values[1]	auto[0]	auto[1]	2002	1			T47	2		T51	1		T52	2
all_values[1]	auto[1]	auto[0]	100745722	1			T47	3		T53	1		T54	1
all_values[1]	auto[1]	auto[1]	517679	1			T47	2		T51	2		T135	2
all_values[2]	auto[0]	auto[0]	235174	1			T47	2		T53	1		T48	1
all_values[2]	auto[0]	auto[1]	1804	1			T52	1		T135	2		T136	1
all_values[2]	auto[1]	auto[0]	100746878	1			T47	2		T53	4		T54	5
all_values[2]	auto[1]	auto[1]	517877	1			T47	4		T51	3		T52	1