Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345222 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
292 |
auto[1] |
362582 |
1 |
|
|
T4 |
4 |
|
T5 |
18 |
|
T11 |
134 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
177401 |
1 |
|
|
T5 |
2 |
|
T6 |
69 |
|
T11 |
92 |
lower_val |
175205 |
1 |
|
|
T5 |
8 |
|
T6 |
84 |
|
T11 |
117 |
zero_val |
2090 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
353402 |
1 |
|
|
T4 |
2 |
|
T5 |
6 |
|
T6 |
134 |
lower_val |
354390 |
1 |
|
|
T4 |
4 |
|
T5 |
14 |
|
T6 |
158 |
zero_val |
12 |
1 |
|
|
T123 |
2 |
|
T124 |
2 |
|
T125 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43057 |
1 |
|
|
T6 |
28 |
|
T11 |
34 |
|
T13 |
5 |
higher_val |
higher_val |
auto[1] |
45749 |
1 |
|
|
T11 |
12 |
|
T17 |
29 |
|
T28 |
3 |
higher_val |
lower_val |
auto[0] |
43211 |
1 |
|
|
T6 |
41 |
|
T11 |
33 |
|
T13 |
1 |
higher_val |
lower_val |
auto[1] |
45381 |
1 |
|
|
T5 |
2 |
|
T11 |
13 |
|
T17 |
23 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T125 |
1 |
|
T126 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T127 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42630 |
1 |
|
|
T6 |
47 |
|
T11 |
45 |
|
T13 |
13 |
lower_val |
higher_val |
auto[1] |
44670 |
1 |
|
|
T5 |
1 |
|
T11 |
16 |
|
T17 |
34 |
lower_val |
lower_val |
auto[0] |
42848 |
1 |
|
|
T6 |
37 |
|
T11 |
40 |
|
T13 |
12 |
lower_val |
lower_val |
auto[1] |
45055 |
1 |
|
|
T5 |
7 |
|
T11 |
16 |
|
T17 |
23 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T123 |
1 |
|
T124 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
746 |
1 |
|
|
T5 |
1 |
|
T11 |
3 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
312 |
1 |
|
|
T11 |
1 |
|
T23 |
1 |
|
T128 |
1 |
zero_val |
lower_val |
auto[0] |
731 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T11 |
1 |
zero_val |
lower_val |
auto[1] |
301 |
1 |
|
|
T123 |
2 |
|
T129 |
2 |
|
T128 |
5 |