Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10354	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9288	1			T15	30		T16	26		T123	17
len_5001_7500	15372	1			T15	30		T16	63		T86	33
len_2501_5000	9467	1			T15	30		T16	15		T86	34
len_1025_2500	5472	1			T15	16		T16	10		T86	20
len_769_1024	6693	1			T6	16		T11	40		T15	4
len_513_768	7049	1			T5	4		T6	18		T11	40
len_257_512	21520	1			T4	1		T5	1		T6	33
len_0_256	261133	1			T4	1		T5	2		T6	21
len_keccak_block_sizes[72]	719	1			T15	3		T16	1		T86	2
len_keccak_block_sizes[104]	618	1			T15	3		T123	2		T129	2
len_keccak_block_sizes[136]	521	1			T15	3		T123	2		T129	2
len_keccak_block_sizes[144]	423	1			T15	3		T123	2		T29	1
len_keccak_block_sizes[168]	322	1			T15	3		T128	3		T151	3
len_1	755	1			T15	3		T86	2		T123	2
len_0	1275	1			T13	4		T15	3		T16	2