Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101501733	1			T47	8		T53	5		T48	1
all_pins[1]	101501733	1			T47	8		T53	5		T48	1
all_pins[2]	101501733	1			T47	8		T53	5		T48	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	245081601	1			T47	19		T53	12		T48	3
values[0x1]	59423598	1			T47	5		T53	3		T54	1
transitions[0x0=>0x1]	58947771	1			T47	3		T53	2		T54	1
transitions[0x1=>0x0]	58947793	1			T47	3		T53	3		T54	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100984419	1			T47	5		T53	5		T48	1
all_pins[0]	values[0x1]	517314	1			T47	3		T51	2		T52	1
all_pins[0]	transitions[0x0=>0x1]	220617	1			T47	1		T52	1		T136	1
all_pins[0]	transitions[0x1=>0x0]	58212438	1			T51	2		T52	3		T135	3
all_pins[1]	values[0x0]	42992598	1			T47	6		T53	5		T48	1
all_pins[1]	values[0x1]	58509135	1			T47	2		T51	4		T52	3
all_pins[1]	transitions[0x0=>0x1]	58332468	1			T47	2		T51	2		T52	2
all_pins[1]	transitions[0x1=>0x0]	220482	1			T53	3		T54	1		T51	1
all_pins[2]	values[0x0]	101104584	1			T47	8		T53	2		T48	1
all_pins[2]	values[0x1]	397149	1			T53	3		T54	1		T51	3
all_pins[2]	transitions[0x0=>0x1]	394686	1			T53	2		T54	1		T51	2
all_pins[2]	transitions[0x1=>0x0]	514873	1			T47	3		T51	1		T52	1