Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	700	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6145	1			T5	1		T6	18		T11	22
len_601_800	13688	1			T4	1		T5	2		T6	31
len_401_600	8957	1			T4	1		T5	3		T6	22
len_201_400	16865	1			T6	8		T11	25		T16	15
len_65_200	75005	1			T6	4		T11	13		T13	17
len_min_for_xof_require_squeeze	1014	1			T15	9		T128	9		T152	1
len_keccak_block_sizes[72]	757	1			T15	9		T128	9		T153	2
len_keccak_block_sizes[104]	762	1			T15	9		T128	9		T153	1
len_keccak_block_sizes[136]	779	1			T13	1		T15	9		T38	1
len_keccak_block_sizes[144]	278	1			T24	1		T152	1		T151	5
len_keccak_block_sizes[168]	297	1			T31	1		T151	5		T154	5
len_datapath_width	14506	1			T11	7		T13	2		T15	9
len_2_63	216952	1			T5	4		T6	63		T11	55
len_1	56	1			T153	1		T36	1		T155	2