Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T47 7 T53 4 T54 7
all_values[1] 284 1 T47 7 T53 4 T54 7
all_values[2] 284 1 T47 7 T53 4 T54 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 474 1 T47 10 T53 7 T54 13
auto[1] 378 1 T47 11 T53 5 T54 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 363 1 T47 11 T53 7 T54 10
auto[1] 489 1 T47 10 T53 5 T54 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 510 1 T47 13 T53 9 T54 10
auto[1] 342 1 T47 8 T53 3 T54 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 72 1 T47 2 T53 2 T54 3
all_values[0] auto[0] auto[0] auto[1] 21 1 T52 1 T135 1 T137 2
all_values[0] auto[0] auto[1] auto[0] 56 1 T47 1 T53 2 T54 2
all_values[0] auto[0] auto[1] auto[1] 24 1 T47 1 T51 1 T118 1
all_values[0] auto[1] auto[0] auto[1] 63 1 T47 2 T54 2 T51 1
all_values[0] auto[1] auto[1] auto[1] 48 1 T47 1 T51 1 T52 2
all_values[1] auto[0] auto[0] auto[0] 68 1 T47 2 T53 3 T54 2
all_values[1] auto[0] auto[0] auto[1] 24 1 T136 1 T118 1 T138 1
all_values[1] auto[0] auto[1] auto[0] 50 1 T47 2 T135 1 T136 1
all_values[1] auto[0] auto[1] auto[1] 27 1 T47 1 T51 2 T52 2
all_values[1] auto[1] auto[0] auto[1] 64 1 T47 1 T54 4 T51 2
all_values[1] auto[1] auto[1] auto[1] 51 1 T47 1 T53 1 T54 1
all_values[2] auto[0] auto[0] auto[0] 75 1 T47 3 T54 1 T52 4
all_values[2] auto[0] auto[0] auto[1] 22 1 T53 1 T139 1 T138 1
all_values[2] auto[0] auto[1] auto[0] 42 1 T47 1 T54 2 T136 3
all_values[2] auto[0] auto[1] auto[1] 29 1 T53 1 T51 1 T136 2
all_values[2] auto[1] auto[0] auto[1] 65 1 T53 1 T54 1 T51 4
all_values[2] auto[1] auto[1] auto[1] 51 1 T47 3 T53 1 T54 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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