Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
310330 |
1 |
|
|
T4 |
4530 |
|
T5 |
18 |
|
T6 |
242 |
auto[1] |
390577 |
1 |
|
|
T12 |
28 |
|
T13 |
746 |
|
T16 |
78 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175152 |
1 |
|
|
T4 |
1096 |
|
T5 |
4 |
|
T6 |
58 |
lower_val |
173966 |
1 |
|
|
T4 |
1172 |
|
T5 |
4 |
|
T6 |
58 |
zero_val |
2033 |
1 |
|
|
T4 |
11 |
|
T5 |
1 |
|
T6 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350626 |
1 |
|
|
T4 |
2254 |
|
T5 |
10 |
|
T6 |
112 |
lower_val |
350267 |
1 |
|
|
T4 |
2276 |
|
T5 |
8 |
|
T6 |
130 |
zero_val |
14 |
1 |
|
|
T42 |
2 |
|
T142 |
2 |
|
T143 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38608 |
1 |
|
|
T4 |
534 |
|
T5 |
3 |
|
T6 |
26 |
higher_val |
higher_val |
auto[1] |
48805 |
1 |
|
|
T12 |
1 |
|
T13 |
100 |
|
T16 |
8 |
higher_val |
lower_val |
auto[0] |
38727 |
1 |
|
|
T4 |
562 |
|
T5 |
1 |
|
T6 |
32 |
higher_val |
lower_val |
auto[1] |
49010 |
1 |
|
|
T12 |
1 |
|
T13 |
94 |
|
T16 |
11 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T145 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
38507 |
1 |
|
|
T4 |
600 |
|
T5 |
3 |
|
T6 |
30 |
lower_val |
higher_val |
auto[1] |
48541 |
1 |
|
|
T12 |
5 |
|
T13 |
85 |
|
T16 |
9 |
lower_val |
lower_val |
auto[0] |
38629 |
1 |
|
|
T4 |
572 |
|
T5 |
1 |
|
T6 |
28 |
lower_val |
lower_val |
auto[1] |
48285 |
1 |
|
|
T12 |
2 |
|
T13 |
91 |
|
T16 |
15 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T143 |
2 |
|
T144 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T42 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
706 |
1 |
|
|
T4 |
5 |
|
T5 |
1 |
|
T6 |
2 |
zero_val |
higher_val |
auto[1] |
281 |
1 |
|
|
T17 |
1 |
|
T24 |
1 |
|
T25 |
2 |
zero_val |
lower_val |
auto[0] |
742 |
1 |
|
|
T4 |
6 |
|
T6 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
304 |
1 |
|
|
T17 |
2 |
|
T25 |
5 |
|
T69 |
1 |