Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10267	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9225	1			T4	38		T13	19		T14	38
len_5001_7500	14925	1			T4	36		T13	18		T14	36
len_2501_5000	9390	1			T4	36		T13	18		T14	36
len_1025_2500	5502	1			T4	22		T13	11		T14	22
len_769_1024	6691	1			T4	4		T12	4		T13	2
len_513_768	6995	1			T4	4		T13	2		T14	4
len_257_512	21380	1			T4	52		T12	4		T13	2
len_0_256	258210	1			T4	2017		T5	9		T6	121
len_keccak_block_sizes[72]	724	1			T4	3		T13	2		T14	3
len_keccak_block_sizes[104]	618	1			T4	3		T13	2		T14	3
len_keccak_block_sizes[136]	522	1			T4	3		T13	2		T14	3
len_keccak_block_sizes[144]	417	1			T4	3		T14	3		T15	2
len_keccak_block_sizes[168]	324	1			T4	3		T14	3		T18	3
len_1	755	1			T4	3		T6	1		T13	2
len_0	1283	1			T4	3		T13	2		T14	3