Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100461876	1			T1	8		T57	5		T55	8
all_pins[1]	100461876	1			T1	8		T57	5		T55	8
all_pins[2]	100461876	1			T1	8		T57	5		T55	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	244303485	1			T1	17		T57	11		T55	19
values[0x1]	57082143	1			T1	7		T57	4		T55	5
transitions[0x0=>0x1]	56644058	1			T1	5		T57	3		T55	4
transitions[0x1=>0x0]	56644080	1			T1	5		T57	4		T55	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99950116	1			T1	4		T57	5		T55	6
all_pins[0]	values[0x1]	511760	1			T1	4		T55	2		T56	1
all_pins[0]	transitions[0x0=>0x1]	218816	1			T1	3		T55	1		T126	1
all_pins[0]	transitions[0x1=>0x0]	55958592	1			T57	1		T55	1		T98	3
all_pins[1]	values[0x0]	44210340	1			T1	7		T57	4		T55	6
all_pins[1]	values[0x1]	56251536	1			T1	1		T57	1		T55	2
all_pins[1]	transitions[0x0=>0x1]	56108311	1			T1	1		T57	1		T55	2
all_pins[1]	transitions[0x1=>0x0]	175622	1			T1	2		T57	3		T55	1
all_pins[2]	values[0x0]	100143029	1			T1	6		T57	2		T55	7
all_pins[2]	values[0x1]	318847	1			T1	2		T57	3		T55	1
all_pins[2]	transitions[0x0=>0x1]	316931	1			T1	1		T57	2		T55	1
all_pins[2]	transitions[0x1=>0x0]	509866	1			T1	3		T55	2		T56	1