Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	697	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5984	1			T16	5		T17	14		T23	17
len_601_800	13519	1			T12	7		T16	11		T17	23
len_401_600	9182	1			T12	1		T16	11		T17	20
len_201_400	16760	1			T4	251		T14	251		T16	3
len_65_200	73536	1			T4	680		T5	2		T6	71
len_min_for_xof_require_squeeze	994	1			T4	10		T6	2		T14	10
len_keccak_block_sizes[72]	730	1			T4	5		T6	1		T14	5
len_keccak_block_sizes[104]	738	1			T4	5		T6	1		T14	5
len_keccak_block_sizes[136]	762	1			T4	5		T14	5		T18	9
len_keccak_block_sizes[144]	289	1			T4	5		T14	5		T155	1
len_keccak_block_sizes[168]	282	1			T4	5		T14	5		T16	1
len_datapath_width	14510	1			T4	5		T5	2		T6	3
len_2_63	214895	1			T4	1329		T5	5		T6	47
len_1	62	1			T156	1		T157	1		T118	1