Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11258246 |
1 |
|
|
T4 |
47900 |
|
T5 |
225 |
|
T6 |
4851 |
auto[1] |
26479129 |
1 |
|
|
T4 |
141800 |
|
T5 |
528 |
|
T6 |
8418 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
37616627 |
1 |
|
|
T4 |
188764 |
|
T5 |
750 |
|
T6 |
13183 |
triple_byte_access |
40266 |
1 |
|
|
T4 |
310 |
|
T5 |
3 |
|
T6 |
25 |
halfword_access |
40411 |
1 |
|
|
T4 |
316 |
|
T6 |
31 |
|
T12 |
2 |
byte_access |
40071 |
1 |
|
|
T4 |
310 |
|
T6 |
30 |
|
T12 |
2 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11137498 |
1 |
|
|
T4 |
46964 |
|
T5 |
222 |
|
T6 |
4765 |
auto[0] |
triple_byte_access |
40266 |
1 |
|
|
T4 |
310 |
|
T5 |
3 |
|
T6 |
25 |
auto[0] |
halfword_access |
40411 |
1 |
|
|
T4 |
316 |
|
T6 |
31 |
|
T12 |
2 |
auto[0] |
byte_access |
40071 |
1 |
|
|
T4 |
310 |
|
T6 |
30 |
|
T12 |
2 |
auto[1] |
word_access |
26479129 |
1 |
|
|
T4 |
141800 |
|
T5 |
528 |
|
T6 |
8418 |