Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102618853	1			T98	1		T62	8		T99	1
all_values[1]	102618853	1			T98	1		T62	8		T99	1
all_values[2]	102618853	1			T98	1		T62	8		T99	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719657

1

T98

3

T62

6

T99

3

auto[1]

307136902

1

T62

18

T63

6

T64

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306302502

1

T98

3

T62

24

T99

3

auto[1]

1554057

1

T64

6

T110

12

T111

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	248792	1			T98	1		T62	2		T99	1
all_values[0]	auto[0]	auto[1]	2328	1			T110	1		T111	3		T167	2
all_values[0]	auto[1]	auto[0]	101852042	1			T62	6		T63	2		T64	3
all_values[0]	auto[1]	auto[1]	515691	1			T64	2		T110	3		T111	2
all_values[1]	auto[0]	auto[0]	215527	1			T98	1		T62	2		T99	1
all_values[1]	auto[0]	auto[1]	1800	1			T110	4		T111	5		T167	2
all_values[1]	auto[1]	auto[0]	101885307	1			T62	6		T63	2		T110	1
all_values[1]	auto[1]	auto[1]	516219	1			T64	2		T168	1		T167	1
all_values[2]	auto[0]	auto[0]	249247	1			T98	1		T62	2		T99	1
all_values[2]	auto[0]	auto[1]	1963	1			T64	2		T110	3		T111	1
all_values[2]	auto[1]	auto[0]	101851587	1			T62	6		T63	2		T64	3
all_values[2]	auto[1]	auto[1]	516056	1			T110	1		T111	4		T140	3