Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361742 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
30 |
auto[1] |
344408 |
1 |
|
|
T4 |
4528 |
|
T5 |
4528 |
|
T13 |
332 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176786 |
1 |
|
|
T4 |
1106 |
|
T5 |
1080 |
|
T6 |
6 |
lower_val |
174613 |
1 |
|
|
T4 |
1129 |
|
T5 |
1139 |
|
T6 |
6 |
zero_val |
2064 |
1 |
|
|
T4 |
5 |
|
T5 |
5 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
353934 |
1 |
|
|
T4 |
2236 |
|
T5 |
2180 |
|
T6 |
10 |
lower_val |
352206 |
1 |
|
|
T4 |
2294 |
|
T5 |
2350 |
|
T6 |
20 |
zero_val |
10 |
1 |
|
|
T154 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45633 |
1 |
|
|
T6 |
2 |
|
T14 |
42 |
|
T15 |
1 |
higher_val |
higher_val |
auto[1] |
43097 |
1 |
|
|
T4 |
552 |
|
T5 |
521 |
|
T13 |
33 |
higher_val |
lower_val |
auto[0] |
44997 |
1 |
|
|
T4 |
1 |
|
T6 |
4 |
|
T14 |
36 |
higher_val |
lower_val |
auto[1] |
43056 |
1 |
|
|
T4 |
553 |
|
T5 |
559 |
|
T13 |
43 |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T155 |
1 |
|
T157 |
1 |
|
T158 |
1 |
lower_val |
higher_val |
auto[0] |
44553 |
1 |
|
|
T6 |
2 |
|
T14 |
47 |
|
T16 |
541 |
lower_val |
higher_val |
auto[1] |
42834 |
1 |
|
|
T4 |
571 |
|
T5 |
529 |
|
T13 |
44 |
lower_val |
lower_val |
auto[0] |
44589 |
1 |
|
|
T5 |
1 |
|
T6 |
4 |
|
T14 |
39 |
lower_val |
lower_val |
auto[1] |
42635 |
1 |
|
|
T4 |
558 |
|
T5 |
609 |
|
T13 |
33 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T154 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
734 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T16 |
5 |
zero_val |
higher_val |
auto[1] |
292 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T17 |
4 |
zero_val |
lower_val |
auto[0] |
758 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
zero_val |
lower_val |
auto[1] |
280 |
1 |
|
|
T4 |
1 |
|
T5 |
3 |
|
T17 |
2 |