Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10318	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9552	1			T4	38		T5	38		T15	19
len_5001_7500	15758	1			T4	36		T5	36		T15	18
len_2501_5000	9487	1			T4	36		T5	36		T15	18
len_1025_2500	5538	1			T4	22		T5	22		T15	11
len_769_1024	6537	1			T4	4		T5	4		T6	4
len_513_768	7071	1			T4	4		T5	4		T6	3
len_257_512	21536	1			T4	52		T5	52		T6	2
len_0_256	259663	1			T4	2017		T5	2017		T6	2
len_keccak_block_sizes[72]	723	1			T4	3		T5	3		T15	2
len_keccak_block_sizes[104]	626	1			T4	3		T5	3		T15	2
len_keccak_block_sizes[136]	521	1			T4	3		T5	3		T15	2
len_keccak_block_sizes[144]	426	1			T4	3		T5	3		T16	3
len_keccak_block_sizes[168]	323	1			T4	3		T5	3		T16	3
len_1	763	1			T4	3		T5	3		T15	2
len_0	1294	1			T4	3		T5	3		T15	2