Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102618853	1			T98	1		T62	8		T99	1
all_pins[1]	102618853	1			T98	1		T62	8		T99	1
all_pins[2]	102618853	1			T98	1		T62	8		T99	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	247509949	1			T98	3		T62	16		T99	3
values[0x1]	60346610	1			T62	8		T63	1		T64	5
transitions[0x0=>0x1]	59880287	1			T62	6		T63	1		T64	3
transitions[0x1=>0x0]	59880305	1			T62	7		T63	1		T64	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102103162	1			T98	1		T62	8		T99	1
all_pins[0]	values[0x1]	515691	1			T64	2		T110	3		T111	2
all_pins[0]	transitions[0x0=>0x1]	220494	1			T64	1		T110	3		T111	2
all_pins[0]	transitions[0x1=>0x0]	59171009	1			T62	5		T63	1		T110	1
all_pins[1]	values[0x0]	43152647	1			T98	1		T62	3		T99	1
all_pins[1]	values[0x1]	59466206	1			T62	5		T63	1		T64	1
all_pins[1]	transitions[0x0=>0x1]	59297325	1			T62	4		T63	1		T64	1
all_pins[1]	transitions[0x1=>0x0]	195832	1			T62	2		T64	2		T168	1
all_pins[2]	values[0x0]	102254140	1			T98	1		T62	5		T99	1
all_pins[2]	values[0x1]	364713	1			T62	3		T64	2		T111	1
all_pins[2]	transitions[0x0=>0x1]	362468	1			T62	2		T64	1		T111	1
all_pins[2]	transitions[0x1=>0x0]	513464	1			T64	1		T110	3		T111	2