Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	783	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6138	1			T6	3		T13	26		T14	23
len_601_800	13876	1			T6	3		T13	56		T14	32
len_401_600	9159	1			T6	3		T13	44		T14	33
len_201_400	17013	1			T4	251		T5	251		T13	18
len_65_200	74563	1			T4	680		T5	680		T6	1
len_min_for_xof_require_squeeze	1009	1			T4	10		T5	10		T14	1
len_keccak_block_sizes[72]	763	1			T4	5		T5	5		T16	9
len_keccak_block_sizes[104]	752	1			T4	5		T5	5		T16	9
len_keccak_block_sizes[136]	757	1			T4	5		T5	5		T16	9
len_keccak_block_sizes[144]	302	1			T4	5		T5	5		T17	5
len_keccak_block_sizes[168]	291	1			T4	5		T5	5		T17	5
len_datapath_width	14409	1			T4	5		T5	5		T13	1
len_2_63	215919	1			T4	1329		T5	1329		T6	5
len_1	64	1			T18	1		T179	1		T58	1