Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101397793	1			T2	1		T53	8		T50	8
all_values[1]	101397793	1			T2	1		T53	8		T50	8
all_values[2]	101397793	1			T2	1		T53	8		T50	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839008

1

T2

3

T53

9

T50

8

auto[1]

303354371

1

T53

15

T50

16

T54

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302650332

1

T2

3

T53

24

T50

21

auto[1]

1543047

1

T50

3

T54

6

T51

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	268484	1			T2	1		T53	2		T50	1
all_values[0]	auto[0]	auto[1]	2471	1			T54	2		T51	1		T144	2
all_values[0]	auto[1]	auto[0]	100614960	1			T53	6		T50	6		T51	3
all_values[0]	auto[1]	auto[1]	511878	1			T50	1		T51	3		T52	4
all_values[1]	auto[0]	auto[0]	294905	1			T2	1		T53	2		T50	5
all_values[1]	auto[0]	auto[1]	2158	1			T50	1		T54	2		T144	2
all_values[1]	auto[1]	auto[0]	100588539	1			T53	6		T50	2		T54	2
all_values[1]	auto[1]	auto[1]	512191	1			T51	4		T52	4		T160	3
all_values[2]	auto[0]	auto[0]	269146	1			T2	1		T53	5		T50	1
all_values[2]	auto[0]	auto[1]	1844	1			T51	4		T52	2		T160	1
all_values[2]	auto[1]	auto[0]	100614298	1			T53	3		T50	6		T54	2
all_values[2]	auto[1]	auto[1]	512505	1			T50	1		T54	2		T144	2