Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
381894 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
338 |
auto[1] |
318632 |
1 |
|
|
T5 |
490 |
|
T15 |
92 |
|
T16 |
272 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175784 |
1 |
|
|
T5 |
126 |
|
T6 |
76 |
|
T7 |
73 |
lower_val |
173741 |
1 |
|
|
T4 |
1 |
|
T5 |
98 |
|
T6 |
87 |
zero_val |
2044 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350444 |
1 |
|
|
T5 |
254 |
|
T6 |
190 |
|
T7 |
148 |
lower_val |
350072 |
1 |
|
|
T4 |
2 |
|
T5 |
238 |
|
T6 |
148 |
zero_val |
10 |
1 |
|
|
T154 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48002 |
1 |
|
|
T6 |
41 |
|
T7 |
31 |
|
T13 |
97 |
higher_val |
higher_val |
auto[1] |
40011 |
1 |
|
|
T5 |
62 |
|
T15 |
19 |
|
T16 |
27 |
higher_val |
lower_val |
auto[0] |
47808 |
1 |
|
|
T6 |
35 |
|
T7 |
42 |
|
T13 |
100 |
higher_val |
lower_val |
auto[1] |
39958 |
1 |
|
|
T5 |
64 |
|
T15 |
14 |
|
T16 |
40 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T154 |
1 |
|
T155 |
1 |
|
T157 |
1 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T156 |
1 |
|
T158 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
47317 |
1 |
|
|
T6 |
52 |
|
T7 |
40 |
|
T13 |
96 |
lower_val |
higher_val |
auto[1] |
39610 |
1 |
|
|
T5 |
51 |
|
T15 |
15 |
|
T16 |
23 |
lower_val |
lower_val |
auto[0] |
46980 |
1 |
|
|
T4 |
1 |
|
T6 |
35 |
|
T7 |
40 |
lower_val |
lower_val |
auto[1] |
39831 |
1 |
|
|
T5 |
47 |
|
T15 |
9 |
|
T16 |
22 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T154 |
1 |
|
T155 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T158 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
749 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
259 |
1 |
|
|
T16 |
1 |
|
T61 |
2 |
|
T31 |
2 |
zero_val |
lower_val |
auto[0] |
763 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
273 |
1 |
|
|
T16 |
2 |
|
T116 |
1 |
|
T159 |
1 |