Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10267	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9259	1			T13	17		T14	24		T16	15
len_5001_7500	14909	1			T5	33		T13	17		T14	24
len_2501_5000	9342	1			T5	34		T13	17		T14	24
len_1025_2500	5418	1			T5	20		T13	10		T14	14
len_769_1024	6624	1			T5	4		T6	31		T13	2
len_513_768	6953	1			T5	3		T6	17		T13	2
len_257_512	21123	1			T5	4		T6	34		T13	2
len_0_256	259154	1			T5	148		T6	32		T7	163
len_keccak_block_sizes[72]	723	1			T5	2		T13	2		T14	2
len_keccak_block_sizes[104]	625	1			T13	2		T14	2		T17	2
len_keccak_block_sizes[136]	521	1			T13	2		T80	3		T82	2
len_keccak_block_sizes[144]	424	1			T13	2		T80	3		T82	2
len_keccak_block_sizes[168]	324	1			T6	1		T80	3		T115	3
len_1	762	1			T5	2		T7	2		T13	2
len_0	1311	1			T5	2		T7	2		T13	2