Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101397793	1			T2	1		T53	8		T50	8
all_pins[1]	101397793	1			T2	1		T53	8		T50	8
all_pins[2]	101397793	1			T2	1		T53	8		T50	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	243609581	1			T2	3		T53	20		T50	18
values[0x1]	60583798	1			T53	4		T50	6		T54	3
transitions[0x0=>0x1]	60100988	1			T53	2		T50	5		T54	3
transitions[0x1=>0x0]	60101017	1			T53	3		T50	5		T54	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100885915	1			T2	1		T53	8		T50	7
all_pins[0]	values[0x1]	511878	1			T50	1		T51	3		T52	4
all_pins[0]	transitions[0x0=>0x1]	218504	1			T50	1		T52	4		T160	1
all_pins[0]	transitions[0x1=>0x0]	59378024	1			T53	2		T50	2		T51	3
all_pins[1]	values[0x0]	41726395	1			T2	1		T53	6		T50	6
all_pins[1]	values[0x1]	59671398	1			T53	2		T50	2		T51	6
all_pins[1]	transitions[0x0=>0x1]	59484434	1			T53	1		T50	1		T51	6
all_pins[1]	transitions[0x1=>0x0]	213558	1			T53	1		T50	2		T54	3
all_pins[2]	values[0x0]	100997271	1			T2	1		T53	6		T50	5
all_pins[2]	values[0x1]	400522	1			T53	2		T50	3		T54	3
all_pins[2]	transitions[0x0=>0x1]	398050	1			T53	1		T50	3		T54	3
all_pins[2]	transitions[0x1=>0x0]	509435	1			T50	1		T51	3		T52	1