Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	706	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5835	1			T6	18		T15	7		T16	31
len_601_800	13432	1			T6	42		T15	17		T16	49
len_401_600	8854	1			T6	29		T15	7		T16	41
len_201_400	16722	1			T6	17		T15	8		T16	23
len_65_200	74313	1			T6	4		T7	85		T15	2
len_min_for_xof_require_squeeze	995	1			T80	10		T115	9		T166	9
len_keccak_block_sizes[72]	762	1			T7	2		T80	5		T115	9
len_keccak_block_sizes[104]	756	1			T7	2		T80	5		T115	9
len_keccak_block_sizes[136]	764	1			T7	2		T80	5		T115	9
len_keccak_block_sizes[144]	289	1			T80	5		T30	1		T167	5
len_keccak_block_sizes[168]	294	1			T7	1		T16	1		T80	5
len_datapath_width	14484	1			T5	246		T7	6		T16	9
len_2_63	214780	1			T6	58		T7	72		T13	390
len_1	73	1			T168	2		T169	1		T170	3