Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 290 1 T53 7 T50 7 T54 4
all_values[1] 290 1 T53 7 T50 7 T54 4
all_values[2] 290 1 T53 7 T50 7 T54 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 447 1 T53 7 T50 7 T54 8
auto[1] 423 1 T53 14 T50 14 T54 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 375 1 T53 8 T50 12 T54 4
auto[1] 495 1 T53 13 T50 9 T54 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 534 1 T53 12 T50 15 T54 8
auto[1] 336 1 T53 9 T50 6 T54 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 55 1 T53 1 T50 1 T54 1
all_values[0] auto[0] auto[0] auto[1] 35 1 T54 1 T144 1 T52 1
all_values[0] auto[0] auto[1] auto[0] 62 1 T53 6 T50 4 T144 1
all_values[0] auto[0] auto[1] auto[1] 27 1 T50 1 T51 1 T52 4
all_values[0] auto[1] auto[0] auto[1] 63 1 T54 2 T144 1 T52 2
all_values[0] auto[1] auto[1] auto[1] 48 1 T50 1 T51 4 T160 3
all_values[1] auto[0] auto[0] auto[0] 64 1 T50 3 T54 1 T51 1
all_values[1] auto[0] auto[0] auto[1] 28 1 T50 1 T54 1 T144 1
all_values[1] auto[0] auto[1] auto[0] 67 1 T53 1 T54 1 T52 3
all_values[1] auto[0] auto[1] auto[1] 21 1 T53 2 T51 3 T160 2
all_values[1] auto[1] auto[0] auto[1] 48 1 T53 2 T50 1 T144 3
all_values[1] auto[1] auto[1] auto[1] 62 1 T53 2 T50 2 T54 1
all_values[2] auto[0] auto[0] auto[0] 67 1 T50 1 T54 1 T51 3
all_values[2] auto[0] auto[0] auto[1] 22 1 T53 1 T51 1 T147 1
all_values[2] auto[0] auto[1] auto[0] 60 1 T50 3 T51 2 T144 2
all_values[2] auto[0] auto[1] auto[1] 26 1 T53 1 T50 1 T54 2
all_values[2] auto[1] auto[0] auto[1] 65 1 T53 3 T54 1 T51 1
all_values[2] auto[1] auto[1] auto[1] 50 1 T53 2 T50 2 T144 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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