Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102686413	1			T63	8		T60	1		T93	1
all_values[1]	102686413	1			T63	8		T60	1		T93	1
all_values[2]	102686413	1			T63	8		T60	1		T93	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711365

1

T63

18

T60

3

T93

3

auto[1]

307347874

1

T63

6

T65

10

T66

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306492201

1

T63

12

T60

3

T93

3

auto[1]

1567038

1

T63

12

T65

3

T66

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	221929	1			T63	3		T60	1		T93	1
all_values[0]	auto[0]	auto[1]	2680	1			T63	2		T66	2		T67	2
all_values[0]	auto[1]	auto[0]	101942138	1			T63	1		T65	2		T67	3
all_values[0]	auto[1]	auto[1]	519666	1			T63	2		T65	1		T66	2
all_values[1]	auto[0]	auto[0]	233050	1			T63	3		T60	1		T93	1
all_values[1]	auto[0]	auto[1]	1916	1			T63	2		T66	1		T156	1
all_values[1]	auto[1]	auto[0]	101931017	1			T63	1		T65	2		T66	1
all_values[1]	auto[1]	auto[1]	520430	1			T63	2		T65	1		T66	3
all_values[2]	auto[0]	auto[0]	249932	1			T63	4		T60	1		T93	1
all_values[2]	auto[0]	auto[1]	1858	1			T63	4		T66	1		T67	2
all_values[2]	auto[1]	auto[0]	101914135	1			T65	3		T66	1		T67	3
all_values[2]	auto[1]	auto[1]	520488	1			T65	1		T66	3		T156	2