Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323092 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
18 |
auto[1] |
387615 |
1 |
|
|
T4 |
16 |
|
T5 |
16 |
|
T13 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
177711 |
1 |
|
|
T4 |
4 |
|
T5 |
2 |
|
T6 |
2 |
lower_val |
175889 |
1 |
|
|
T4 |
4 |
|
T5 |
6 |
|
T6 |
2 |
zero_val |
2171 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
355530 |
1 |
|
|
T4 |
8 |
|
T5 |
14 |
|
T6 |
10 |
lower_val |
355171 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T6 |
8 |
zero_val |
6 |
1 |
|
|
T149 |
2 |
|
T150 |
4 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40200 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T14 |
574 |
higher_val |
higher_val |
auto[1] |
48772 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T13 |
1 |
higher_val |
lower_val |
auto[0] |
40233 |
1 |
|
|
T6 |
1 |
|
T14 |
532 |
|
T17 |
22 |
higher_val |
lower_val |
auto[1] |
48505 |
1 |
|
|
T4 |
2 |
|
T13 |
3 |
|
T15 |
87 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39955 |
1 |
|
|
T6 |
2 |
|
T13 |
1 |
|
T14 |
560 |
lower_val |
higher_val |
auto[1] |
48228 |
1 |
|
|
T4 |
2 |
|
T5 |
6 |
|
T13 |
2 |
lower_val |
lower_val |
auto[0] |
40027 |
1 |
|
|
T14 |
497 |
|
T17 |
22 |
|
T19 |
46 |
lower_val |
lower_val |
auto[1] |
47676 |
1 |
|
|
T4 |
2 |
|
T13 |
2 |
|
T15 |
91 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T149 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T150 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
787 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T14 |
2 |
zero_val |
higher_val |
auto[1] |
324 |
1 |
|
|
T29 |
1 |
|
T31 |
2 |
|
T151 |
1 |
zero_val |
lower_val |
auto[0] |
737 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
323 |
1 |
|
|
T30 |
2 |
|
T27 |
4 |
|
T151 |
1 |