Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10357	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9521	1			T14	38		T15	17		T34	24
len_5001_7500	15448	1			T14	36		T15	17		T16	33
len_2501_5000	9496	1			T14	36		T15	17		T16	34
len_1025_2500	5570	1			T14	22		T15	10		T16	20
len_769_1024	6892	1			T14	4		T15	2		T16	4
len_513_768	7346	1			T14	4		T15	2		T16	3
len_257_512	21671	1			T14	52		T15	2		T16	4
len_0_256	261759	1			T4	9		T5	9		T6	9
len_keccak_block_sizes[72]	723	1			T14	3		T15	2		T16	2
len_keccak_block_sizes[104]	621	1			T14	3		T15	2		T34	2
len_keccak_block_sizes[136]	527	1			T14	3		T15	2		T18	1
len_keccak_block_sizes[144]	440	1			T14	3		T15	2		T76	2
len_keccak_block_sizes[168]	324	1			T14	3		T26	1		T46	3
len_1	768	1			T14	3		T15	2		T16	2
len_0	1318	1			T14	3		T15	2		T16	2