Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102686413	1			T63	8		T60	1		T93	1
all_pins[1]	102686413	1			T63	8		T60	1		T93	1
all_pins[2]	102686413	1			T63	8		T60	1		T93	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	248822079	1			T63	22		T60	3		T93	3
values[0x1]	59237160	1			T63	2		T65	3		T66	8
transitions[0x0=>0x1]	58759062	1			T63	2		T65	2		T66	3
transitions[0x1=>0x0]	58759090	1			T63	2		T65	3		T66	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102166747	1			T63	6		T60	1		T93	1
all_pins[0]	values[0x1]	519666	1			T63	2		T65	1		T66	2
all_pins[0]	transitions[0x0=>0x1]	220822	1			T63	2		T65	1		T66	1
all_pins[0]	transitions[0x1=>0x0]	58044529	1			T66	2		T67	1		T157	2
all_pins[1]	values[0x0]	44343040	1			T63	8		T60	1		T93	1
all_pins[1]	values[0x1]	58343373	1			T66	3		T67	1		T156	1
all_pins[1]	transitions[0x0=>0x1]	58166415	1			T66	1		T67	1		T157	2
all_pins[1]	transitions[0x1=>0x0]	197163	1			T65	2		T66	1		T67	2
all_pins[2]	values[0x0]	102312292	1			T63	8		T60	1		T93	1
all_pins[2]	values[0x1]	374121	1			T65	2		T66	3		T67	2
all_pins[2]	transitions[0x0=>0x1]	371825	1			T65	1		T66	1		T67	2
all_pins[2]	transitions[0x1=>0x0]	517398	1			T63	2		T65	1		T66	1